TargetInstrInfo.h revision 6c1d2b90e31ea3337705372d1757727d6764686d
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 56fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// This file was developed by the LLVM research group and is distributed under 66fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// the University of Illinois Open Source License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 10a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// This file describes the target machine instructions to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos#include "llvm/CodeGen/MachineBasicBlock.h" 186c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng#include "llvm/CodeGen/MachineFunction.h" 19551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/DataTypes.h" 202cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner#include <vector> 21be67780f31958b05ad3c510ca3a973d327517e86Chris Lattner#include <cassert> 22a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 23d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 24d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 255684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass MachineInstr; 26f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattnerclass TargetMachine; 27c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adveclass MachineCodeForInstruction; 28ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetRegisterClass; 296c14147d934bd644fc9d24a3b36f3c38799a3401Evan Chengclass LiveVariables; 30a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 31f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 32f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner// Data types used to define information about a single machine instruction 33f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 34a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 35ab8672c8bb83e722b856eac67863542ea7e0cbb2Alkis Evlogimenostypedef short MachineOpCode; 36c188b733babbcdb0ff51613d0bb133e0496963b6Chris Lattnertypedef unsigned InstrSchedClass; 37a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 38a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//--------------------------------------------------------------------------- 393501feab811c86c9659248a4875fc31a3165f84dChris Lattner// struct TargetInstrDescriptor: 4000876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Predefined information about each machine instruction. 4100876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Designed to initialized statically. 423501feab811c86c9659248a4875fc31a3165f84dChris Lattner// 43a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 44f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BRANCH_FLAG = 1 << 0; 45f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_CALL_FLAG = 1 << 1; 46f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_RET_FLAG = 1 << 2; 47f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BARRIER_FLAG = 1 << 3; 48f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_DELAY_SLOT_FLAG = 1 << 4; 49f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_LOAD_FLAG = 1 << 5; 50f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_STORE_FLAG = 1 << 6; 5115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 52a1fd6504aaf62b87530e8230517957bad3facc96Evan Cheng// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 5315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// changed into a 3-address instruction if the first two operands cannot be 5415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// assigned to the same register. The target must implement the 5515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// TargetInstrInfo::convertToThreeAddress method for this instruction. 56a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; 5715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 5815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 5915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// Z), which produces the same result if Y and Z are exchanged. 60a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_COMMUTABLE = 1 << 8; 61a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 62075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 63075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// block? Typically this is things like return and branch instructions. 64075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// Various passes use this to insert code into the bottom of a basic block, but 65075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// before control flow occurs. 66a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_TERMINATOR_FLAG = 1 << 9; 67075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner 6809321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 6909321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// insertion support when the DAG scheduler is inserting it into a machine basic 7009321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// block. 71a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; 7209321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner 738d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 748d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng// operands in addition to the minimum number operands specified. 75a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_VARIABLE_OPS = 1 << 11; 768d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng 771b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner// M_PREDICATED - Set if this instruction has a predicate that controls its 781b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner// execution. 79a1fd6504aaf62b87530e8230517957bad3facc96Evan Chengconst unsigned M_PREDICATED = 1 << 12; 801b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner 815d5c93f659dd3f09375ea0fbe5d6c2df64791f73Evan Cheng// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 825d5c93f659dd3f09375ea0fbe5d6c2df64791f73Evan Cheng// at any time, e.g. constant generation, load from constant pool. 835d5c93f659dd3f09375ea0fbe5d6c2df64791f73Evan Chengconst unsigned M_REMATERIALIZIBLE = 1 << 13; 845d5c93f659dd3f09375ea0fbe5d6c2df64791f73Evan Cheng 851b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner 8621d03f2de0087d60dbf575d95924404a97852879Evan Cheng// Machine operand flags 8721d03f2de0087d60dbf575d95924404a97852879Evan Cheng// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 8821d03f2de0087d60dbf575d95924404a97852879Evan Cheng// requires a callback to look up its register class. 8921d03f2de0087d60dbf575d95924404a97852879Evan Chengconst unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 9021d03f2de0087d60dbf575d95924404a97852879Evan Cheng 915de723c1189c596a9c1b90ce4ee90c137f198ad4Evan Cheng/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the 925de723c1189c596a9c1b90ce4ee90c137f198ad4Evan Cheng/// predicate operand that controls an M_PREDICATED instruction. 93f6e8e6bace845cbbb6c1f6d859ffd8a3a154222bChris Lattnerconst unsigned M_PREDICATE_OPERAND = 1 << 1; 94f6e8e6bace845cbbb6c1f6d859ffd8a3a154222bChris Lattner 956c14147d934bd644fc9d24a3b36f3c38799a3401Evan Chengnamespace TOI { 966c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng // Operand constraints: only "tied_to" for now. 976c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng enum OperandConstraint { 986c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng TIED_TO = 0 // Must be allocated the same register as. 996c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng }; 1006c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng} 101f6e8e6bace845cbbb6c1f6d859ffd8a3a154222bChris Lattner 102ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// TargetOperandInfo - This holds information about one operand of a machine 103ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// instruction, indicating the register class for register operands, etc. 104ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// 105ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetOperandInfo { 106ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerpublic: 10760f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// RegClass - This specifies the register class enumeration of the operand 10860f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// if the operand is a register. If not, this contains 0. 10960f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned short RegClass; 11060f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned short Flags; 111e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// Lower 16 bits are used to specify which constraints are set. The higher 16 112e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// bits are used to specify the value of constraints (4 bits each). 113e2ba8975883874633a1035c245af3b948b940b25Evan Cheng unsigned int Constraints; 114ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// Currently no other information. 115ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner}; 116ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 117ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 1181fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerclass TargetInstrDescriptor { 1191fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerpublic: 12033247d537ddce29e65bc324bf8d40a15d2d88c01Evan Cheng MachineOpCode Opcode; // The opcode. 12133247d537ddce29e65bc324bf8d40a15d2d88c01Evan Cheng unsigned short numOperands; // Num of args (may be more if variable_ops). 1224683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner const char * Name; // Assembly language mnemonic for the opcode. 12375e961ae6b2e2801160e560057ad97ece4443986Chris Lattner InstrSchedClass schedClass; // enum identifying instr sched class 12475e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned Flags; // flags identifying machine instr class 12575e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned TSFlags; // Target Specific Flag values 126f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitUses; // Registers implicitly read by this instr 127f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 128ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 1296c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng 1306c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// getOperandConstraint - Returns the value of the specific constraint if 1316c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// it is set. Returns -1 if it is not set. 1326c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng int getOperandConstraint(unsigned OpNum, 1336c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng TOI::OperandConstraint Constraint) const { 134f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 135f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng "Invalid operand # of TargetInstrInfo"); 136f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng if (OpNum < numOperands && 137f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng (OpInfo[OpNum].Constraints & (1 << Constraint))) { 1386c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng unsigned Pos = 16 + Constraint * 4; 1396c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 1406c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng } 1416c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng return -1; 1426c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng } 143cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng 144cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng /// findTiedToSrcOperand - Returns the operand that is tied to the specified 145cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng /// dest operand. Returns -1 if there isn't one. 146cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng int findTiedToSrcOperand(unsigned OpNum) const; 147a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 148a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 149a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 1503501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 15134695381d626485a560594f162701088079589dfMisha Brukman/// 1523501feab811c86c9659248a4875fc31a3165f84dChris Lattner/// TargetInstrInfo - Interface to description of machine instructions 15334695381d626485a560594f162701088079589dfMisha Brukman/// 154075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 155075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner const TargetInstrDescriptor* desc; // raw array to allow static init'n 156bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned NumOpcodes; // number of entries in the desc array 157075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner unsigned numRealOpCodes; // number of non-dummy op codes 15834695381d626485a560594f162701088079589dfMisha Brukman 159075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 160075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 161a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 162bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 163075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 16470535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 1654ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner // Invariant opcodes: All instruction sets have these as their low opcodes. 1664ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner enum { 1674ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner PHI = 0, 1681ee29257428960fede862fcfdbe80d5d007927e9Jim Laskey INLINEASM = 1, 1691ee29257428960fede862fcfdbe80d5d007927e9Jim Laskey LABEL = 2 1704ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner }; 17134695381d626485a560594f162701088079589dfMisha Brukman 172bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 17334695381d626485a560594f162701088079589dfMisha Brukman 174e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 175e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 176e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 1772441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 1782441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner assert((unsigned)Opcode < NumOpcodes); 1792441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return desc[Opcode]; 180a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 1814683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 1822441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const char *getName(MachineOpCode Opcode) const { 1832441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Name; 1844683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner } 18534695381d626485a560594f162701088079589dfMisha Brukman 1862441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner int getNumOperands(MachineOpCode Opcode) const { 1872441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).numOperands; 188a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 189450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 1902441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 1912441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).schedClass; 192a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 193d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 1942441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitUses(MachineOpCode Opcode) const { 1952441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitUses; 196d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 197d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 1982441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 1992441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitDefs; 200d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 201d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 202450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 203a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 204a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Query instruction class flags according to the machine-independent 205a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // flags listed above. 20634695381d626485a560594f162701088079589dfMisha Brukman // 2072441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isReturn(MachineOpCode Opcode) const { 2082441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_RET_FLAG; 209a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 210450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 2111b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner bool isPredicated(MachineOpCode Opcode) const { 2121b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner return get(Opcode).Flags & M_PREDICATED; 2131b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner } 2145d5c93f659dd3f09375ea0fbe5d6c2df64791f73Evan Cheng bool isReMaterializable(MachineOpCode Opcode) const { 2155d5c93f659dd3f09375ea0fbe5d6c2df64791f73Evan Cheng return get(Opcode).Flags & M_REMATERIALIZIBLE; 2165d5c93f659dd3f09375ea0fbe5d6c2df64791f73Evan Cheng } 21713d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng bool isCommutableInstr(MachineOpCode Opcode) const { 21813d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng return get(Opcode).Flags & M_COMMUTABLE; 21913d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng } 220075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner bool isTerminatorInstr(unsigned Opcode) const { 221075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner return get(Opcode).Flags & M_TERMINATOR_FLAG; 222075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner } 2230271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 2240271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBranch(MachineOpCode Opcode) const { 2250271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BRANCH_FLAG; 2260271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2270271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 2280271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// isBarrier - Returns true if the specified instruction stops control flow 2290271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// from executing the instruction immediately following it. Examples include 2300271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// unconditional branches and return instructions. 2310271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBarrier(MachineOpCode Opcode) const { 2320271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BARRIER_FLAG; 2330271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2340271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 2350271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isCall(MachineOpCode Opcode) const { 2360271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_CALL_FLAG; 2370271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2380271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isLoad(MachineOpCode Opcode) const { 2390271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_LOAD_FLAG; 2400271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2410271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isStore(MachineOpCode Opcode) const { 2420271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_STORE_FLAG; 2430271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2440271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 245b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 246b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// which must be filled by the code generator. 247b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner bool hasDelaySlot(unsigned Opcode) const { 248b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 249b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 250b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 2510271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 2520271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 2530271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// machine basic block. 2540271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 2550271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 2560271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 257d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve 2588d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng bool hasVariableOperands(MachineOpCode Opcode) const { 2598d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng return get(Opcode).Flags & M_VARIABLE_OPS; 2608d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng } 2618d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng 262e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// getOperandConstraint - Returns the value of the specific constraint if 263e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// it is set. Returns -1 if it is not set. 264e2ba8975883874633a1035c245af3b948b940b25Evan Cheng int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 2656c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng TOI::OperandConstraint Constraint) const { 2666c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng return get(Opcode).getOperandConstraint(OpNum, Constraint); 267e2ba8975883874633a1035c245af3b948b940b25Evan Cheng } 268e2ba8975883874633a1035c245af3b948b940b25Evan Cheng 2690cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// Return true if the instruction is a register to register move 2700cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// and leave the source and dest operands in the passed parameters. 2715e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 2725e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& sourceReg, 2735e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& destReg) const { 2745e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 2755e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 276af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 277af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 278af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 279af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 280af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 281af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 282af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 283af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 284af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 285af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 286af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 287af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 288af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 289af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 290af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 291af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 292af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 293af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 2945e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 29515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 29615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 2976c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// may be able to convert a two-address instruction into one or moretrue 2986c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// three-address instructions on demand. This allows the X86 target (for 29915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 30015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 30115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 30215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 3036c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// performed, otherwise it returns the last new instruction. 30415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 3056c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng virtual MachineInstr * 3066c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng convertToThreeAddress(MachineFunction::iterator &MFI, 3076c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 30815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 30915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 31015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 311d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// commuteInstruction - If a target has any instructions that are commutable, 312d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// but require converting to a different instruction or making non-trivial 313d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// changes to commute them, this method can overloaded to do this. The 314d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// default implementation of this method simply swaps the first two operands 315d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// of MI and returns it. 316d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 317d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// If a target wants to make more aggressive changes, they can construct and 318d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// return a new machine instruction. If an instruction cannot commute, it 319d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// can also return null. 320d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 321d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 322d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 323b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 324b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 325b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 326b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 327b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 32872dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 32972dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 33072dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 331b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 3326c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 3. If this block ends with an conditional branch and it falls through to 3336c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// an successor block, it sets TBB to be the branch destination block and a 3346c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// list of operands that evaluate the condition. These 3356c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 3366c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 3376c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 4. If this block ends with an conditional branch and an unconditional 3386c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// block, it returns the 'true' destination in TBB, the 'false' destination 3396c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// in FBB, and a list of operands that evaluate the condition. These 3406c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 3416c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 342b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 343b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 344b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 345b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 346b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 347b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 348b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner std::vector<MachineOperand> &Cond) const { 349b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 350905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 351b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 352b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 353b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// this is only invoked in cases where AnalyzeBranch returns success. 354d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner virtual void RemoveBranch(MachineBasicBlock &MBB) const { 355b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 356b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 357b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 358b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// InsertBranch - Insert a branch into the end of the specified 359b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// MachineBasicBlock. This operands to this method are the same as those 36033644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 36133644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returns success and when an unconditional branch (TBB is non-null, FBB is 36233644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// null, Cond is empty) needs to be inserted. 363d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 364d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner MachineBasicBlock *FBB, 365d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner const std::vector<MachineOperand> &Cond) const { 36624321d7e23a482cbd0b7502f43e9026f87a3684dRafael Espindola assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 367b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 368b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 369c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// BlockHasNoFallThrough - Return true if the specified block does not 370c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// fall-through into its successor block. This is primarily used when a 371c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// branch is unanalyzable. It is useful for things like unconditional 372c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// indirect branches (jump tables). 373c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 374c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner return false; 375c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner } 376c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner 3775f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 3785f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 3795f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 3805f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 3815f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 382905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 3830271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 38465e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 38565e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 38665e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 38765e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner MachineBasicBlock::iterator MI) const { 38865e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner assert(0 && "Target didn't implement insertNoop!"); 38965e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner abort(); 39065e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner } 39121d03f2de0087d60dbf575d95924404a97852879Evan Cheng 3920402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// isPredicatable - True if the instruction can be converted into a 3930402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// predicated instruction. 3940402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng virtual bool isPredicatable(MachineInstr *MI) const { 3950402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng return false; 3960402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng } 3970402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 3980402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// PredicateInstruction - Convert the instruction into a predicated 3990402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// instruction. 4000402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng virtual void PredicateInstruction(MachineInstr *MI, 4010402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng std::vector<MachineOperand> &Cond) const { 4020402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng assert(0 && "Target didn't implement PredicateInstruction!"); 4030402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng abort(); 4040402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng } 4050402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 40621d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 40721d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// values. 40821d03f2de0087d60dbf575d95924404a97852879Evan Cheng virtual const TargetRegisterClass *getPointerRegClass() const { 40921d03f2de0087d60dbf575d95924404a97852879Evan Cheng assert(0 && "Target didn't implement getPointerRegClass!"); 41021d03f2de0087d60dbf575d95924404a97852879Evan Cheng abort(); 411fb062ece96092e70a835c0d462613b07228d60a3Jeff Cohen return 0; // Must return a value in order to compile with VS 2005 41221d03f2de0087d60dbf575d95924404a97852879Evan Cheng } 413a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 414a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 415d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 416d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 417a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 418