TargetInstrInfo.h revision a5dc45e3c8fa26e62b187284a240adf3879b56e2
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 1061e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman// This file describes the target machine instruction set to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#include "llvm/Target/TargetInstrDesc.h" 186c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng#include "llvm/CodeGen/MachineFunction.h" 19a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 20d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 21d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 22af76e592c7f9deff0e55c13dbb4a34f07f1c7f64Chris Lattnerclass MCAsmInfo; 23ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetRegisterClass; 24d923fc621ff5b5e500977edf9236c9e34e8d7ebcEvan Chengclass TargetRegisterInfo; 256c14147d934bd644fc9d24a3b36f3c38799a3401Evan Chengclass LiveVariables; 26d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Andersonclass CalleeSavedInfo; 2743dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SDNode; 2843dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SelectionDAG; 29a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 30f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersontemplate<class T> class SmallVectorImpl; 31f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 32a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 333501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 3434695381d626485a560594f162701088079589dfMisha Brukman/// 3561e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman/// TargetInstrInfo - Interface to description of machine instruction set 3634695381d626485a560594f162701088079589dfMisha Brukman/// 37075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 38749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 39749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner unsigned NumOpcodes; // Number of entries in the desc array 4034695381d626485a560594f162701088079589dfMisha Brukman 41075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 42075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 43a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 44749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 45075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 4670535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 474ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner // Invariant opcodes: All instruction sets have these as their low opcodes. 484ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner enum { 494ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner PHI = 0, 501ee29257428960fede862fcfdbe80d5d007927e9Jim Laskey INLINEASM = 1, 514406604047423576e36657c7ede266ca42e79642Dan Gohman DBG_LABEL = 2, 524406604047423576e36657c7ede266ca42e79642Dan Gohman EH_LABEL = 3, 534406604047423576e36657c7ede266ca42e79642Dan Gohman GC_LABEL = 4, 5426207e5bf1123a793bd9b38bcda2f569a6b45ef2Jakob Stoklund Olesen 5526207e5bf1123a793bd9b38bcda2f569a6b45ef2Jakob Stoklund Olesen /// KILL - This instruction is a noop that is used only to adjust the liveness 5626207e5bf1123a793bd9b38bcda2f569a6b45ef2Jakob Stoklund Olesen /// of registers. This can be useful when dealing with sub-registers. 5726207e5bf1123a793bd9b38bcda2f569a6b45ef2Jakob Stoklund Olesen KILL = 5, 5873099b105869f02ece79c2cea982286744635c4aDan Gohman 5973099b105869f02ece79c2cea982286744635c4aDan Gohman /// EXTRACT_SUBREG - This instruction takes two operands: a register 6073099b105869f02ece79c2cea982286744635c4aDan Gohman /// that has subregisters, and a subregister index. It returns the 6173099b105869f02ece79c2cea982286744635c4aDan Gohman /// extracted subregister value. This is commonly used to implement 6273099b105869f02ece79c2cea982286744635c4aDan Gohman /// truncation operations on target architectures which support it. 634406604047423576e36657c7ede266ca42e79642Dan Gohman EXTRACT_SUBREG = 6, 6473099b105869f02ece79c2cea982286744635c4aDan Gohman 6573099b105869f02ece79c2cea982286744635c4aDan Gohman /// INSERT_SUBREG - This instruction takes three operands: a register 6673099b105869f02ece79c2cea982286744635c4aDan Gohman /// that has subregisters, a register providing an insert value, and a 6773099b105869f02ece79c2cea982286744635c4aDan Gohman /// subregister index. It returns the value of the first register with 6873099b105869f02ece79c2cea982286744635c4aDan Gohman /// the value of the second register inserted. The first register is 6973099b105869f02ece79c2cea982286744635c4aDan Gohman /// often defined by an IMPLICIT_DEF, as is commonly used to implement 7073099b105869f02ece79c2cea982286744635c4aDan Gohman /// anyext operations on target architectures which support it. 714406604047423576e36657c7ede266ca42e79642Dan Gohman INSERT_SUBREG = 7, 7273099b105869f02ece79c2cea982286744635c4aDan Gohman 7373099b105869f02ece79c2cea982286744635c4aDan Gohman /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 744406604047423576e36657c7ede266ca42e79642Dan Gohman IMPLICIT_DEF = 8, 7573099b105869f02ece79c2cea982286744635c4aDan Gohman 7673099b105869f02ece79c2cea982286744635c4aDan Gohman /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 7773099b105869f02ece79c2cea982286744635c4aDan Gohman /// that the first operand is an immediate integer constant. This constant 7873099b105869f02ece79c2cea982286744635c4aDan Gohman /// is often zero, as is commonly used to implement zext operations on 7973099b105869f02ece79c2cea982286744635c4aDan Gohman /// target architectures which support it, such as with x86-64 (with 8073099b105869f02ece79c2cea982286744635c4aDan Gohman /// zext from i32 to i64 via implicit zero-extension). 81f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman SUBREG_TO_REG = 9, 82f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 8388c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 84f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// register-to-register copy into a specific register class. This is only 85f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// used between instruction selection and MachineInstr creation, before 8688c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman /// virtual registers have been created for all the instructions, and it's 8788c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman /// only needed in cases where the register classes implied by the 8888c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman /// instructions are insufficient. The actual MachineInstrs to perform 8988c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 9088c7af096b09ad26cbcebfdf40151e04094b7460Dan Gohman COPY_TO_REGCLASS = 10 916634e26aa11b0e2eabde8b3b463bb943364f8d9dChristopher Lamb }; 9234695381d626485a560594f162701088079589dfMisha Brukman 93bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 9434695381d626485a560594f162701088079589dfMisha Brukman 95e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 96e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 97e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 98749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc &get(unsigned Opcode) const { 99749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner assert(Opcode < NumOpcodes && "Invalid opcode!"); 100749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return Descriptors[Opcode]; 101a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 1024683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 103041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isTriviallyReMaterializable - Return true if the instruction is trivially 104d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// rematerializable, meaning it has no side effects and requires no operands 105d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// that aren't always available. 106a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman bool isTriviallyReMaterializable(const MachineInstr *MI, 107a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman AliasAnalysis *AA = 0) const { 108a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return MI->getOpcode() == IMPLICIT_DEF || 109a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman (MI->getDesc().isRematerializable() && 1103731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman (isReallyTriviallyReMaterializable(MI, AA) || 111a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman isReallyTriviallyReMaterializableGeneric(MI, AA))); 112d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 113d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 114d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanprotected: 115041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isReallyTriviallyReMaterializable - For instructions with opcodes for 116a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 117a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// specify whether the instruction is actually trivially rematerializable, 118a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// taking into consideration its operands. This predicate must return false 119a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// if the instruction has any side effects other than producing a value, or 120a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// if it requres any address registers that are not always available. 1213731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 1223731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman AliasAnalysis *AA) const { 123a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 124d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 125d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 126a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohmanprivate: 127a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 128a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// for which the M_REMATERIALIZABLE flag is set and the target hook 129a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// isReallyTriviallyReMaterializable returns false, this function does 130a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// target-independent tests to determine if the instruction is really 131a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// trivially rematerializable. 132a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 133a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman AliasAnalysis *AA) const; 134a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 135d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanpublic: 136c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// isMoveInstr - Return true if the instruction is a register to register 137c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// move and return the source and dest operands and their sub-register 138c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// indices by reference. 1395e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 14004ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& SrcReg, unsigned& DstReg, 14104ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 1425e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 1435e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 144c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng 145c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// isIdentityCopy - Return true if the instruction is a copy (or 146c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 147c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// destination registers are the same. 148a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng bool isIdentityCopy(const MachineInstr &MI) const { 149a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 150c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 151c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng SrcReg == DstReg) 152c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng return true; 153c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng 154a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && 155a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 156a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng return true; 157c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng 158a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || 159a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && 160a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 161a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng return true; 162c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng return false; 163c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng } 164af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 165af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 166af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 167af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 168af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 169af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 170cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 171cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 172af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 173af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 174af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 175af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 176af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 177af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 178af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 179af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 180cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 181cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 182af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 183af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 1845e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 185ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// reMaterialize - Re-issue the specified 'original' instruction at the 186ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// specific location targeting a new destination register. 187ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 188ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 189378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, 190ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng const MachineInstr *Orig) const = 0; 191ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 19215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 19315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1942c8c3e2e31e641085060edce0ddde3833ffa53daDan Gohman /// may be able to convert a two-address instruction into one or more true 1956c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// three-address instructions on demand. This allows the X86 target (for 19615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 19715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 19815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 19915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 2006c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// performed, otherwise it returns the last new instruction. 20115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 2026c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng virtual MachineInstr * 2036c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng convertToThreeAddress(MachineFunction::iterator &MFI, 204f660c171c838793b87b7e58e91609cecf256378dOwen Anderson MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 20515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 20615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 20715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 208d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// commuteInstruction - If a target has any instructions that are commutable, 209d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// but require converting to a different instruction or making non-trivial 210d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// changes to commute them, this method can overloaded to do this. The 211d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// default implementation of this method simply swaps the first two operands 212d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// of MI and returns it. 213d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 214d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// If a target wants to make more aggressive changes, they can construct and 215d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// return a new machine instruction. If an instruction cannot commute, it 216d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// can also return null. 217d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 21858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng /// If NewMI is true, then a new machine instruction must be created. 21958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng /// 22058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 22158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const = 0; 222d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 223261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng /// findCommutedOpIndices - If specified MI is commutable, return the two 224261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng /// operand indices that would swap value. Return true if the instruction 225261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng /// is not in a form which this routine understands. 226261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 227261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const = 0; 228f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 229b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 230b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 231b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 232b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 233b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 23472dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 23572dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 23672dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 237b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 2386c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 3. If this block ends with an conditional branch and it falls through to 239a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// a successor block, it sets TBB to be the branch destination block and 240c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// a list of operands that evaluate the condition. These 2416c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 2426c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 243a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// 4. If this block ends with a conditional branch followed by an 244a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// unconditional branch, it returns the 'true' destination in TBB, the 245a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// 'false' destination in FBB, and a list of operands that evaluate the 246a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// condition. These operands can be passed to other TargetInstrInfo 247a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// methods to create new branches. 248b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 249b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 250b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 251b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 252dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// If AllowModify is true, then this routine is allowed to modify the basic 253dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// block (e.g. delete instructions after the unconditional branch). 254dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// 255b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 256b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 257dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 258dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify = false) const { 259b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 260905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 261a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman 262b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 2638c8b2a89f9173aaa06e91ff43c3a46276f23b355Dan Gohman /// This is only invoked in cases where AnalyzeBranch returns success. It 264b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// returns the number of instructions that were removed. 265b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 266b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 267b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 268b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 269a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman 270a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// InsertBranch - Insert branch code into the end of the specified 271a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// MachineBasicBlock. The operands to this method are the same as those 272a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// returned by AnalyzeBranch. This is only invoked in cases where 273a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// AnalyzeBranch returns success. It returns the number of instructions 274a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// inserted. 275c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// 276c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// It is also invoked by tail merging to add unconditional branches in 277c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// cases where AnalyzeBranch doesn't apply because there was no original 278c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// branch to analyze. At least this much must be implemented, else tail 279c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// merging needs to be disabled. 280b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 281d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner MachineBasicBlock *FBB, 28244eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Cond) const { 28324321d7e23a482cbd0b7502f43e9026f87a3684dRafael Espindola assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 284b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 285b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 286b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 287a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// copyRegToReg - Emit instructions to copy between a pair of registers. It 288a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// returns false if the target does not how to copy between the specified 289a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// registers. 290940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson virtual bool copyRegToReg(MachineBasicBlock &MBB, 291d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator MI, 292d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 293d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 294d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *SrcRC) const { 295d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 296c93457053cfecb24105ee3800c8e53921b950d8fCedric Venet return false; 297d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 298d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 29995a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// storeRegToStackSlot - Store the specified register of the given register 30095a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class to the specified stack frame index. The store instruction is to be 30195a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 30295a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. If isKill is true, the register operand is the last use and 30395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// must be marked kill. 304f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 305f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 306f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 307f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 308f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 309f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 310f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 31195a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// loadRegFromStackSlot - Load the specified register of the given register 31295a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class from the specified stack frame index. The load instruction is to be 31395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 31495a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. 315f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 316f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 317f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 318f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 319f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 320f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 321f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 322d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 323d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// saved registers and returns true if it isn't possible / profitable to do 324d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// so by issuing a series of store instructions via 325d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// storeRegToStackSlot(). Returns false otherwise. 326d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 327d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 328d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson const std::vector<CalleeSavedInfo> &CSI) const { 329d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson return false; 330d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson } 331d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 332d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 333d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// saved registers and returns true if it isn't possible / profitable to do 334d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// so by issuing a series of load instructions via loadRegToStackSlot(). 335d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// Returns false otherwise. 336d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 337d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 338d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson const std::vector<CalleeSavedInfo> &CSI) const { 339d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson return false; 340d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson } 341d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 34243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 34343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// slot into the specified machine instruction for the specified operand(s). 34443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// If this is possible, a new instruction is returned with the specified 34543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// operand folded, otherwise NULL is returned. The client is responsible for 34643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// removing the old instruction and adding the new one in the instruction 34743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stream. 348c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* foldMemoryOperand(MachineFunction &MF, 349c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 350c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 351c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const; 35243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 35343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Same as the previous version except it allows folding 35443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// of any load and store from / to any address, not just from a specific 35543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stack slot. 356c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* foldMemoryOperand(MachineFunction &MF, 357c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 358c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 359c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const; 360c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 361c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanprotected: 362c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 363c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 364c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 365c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 3665fd79d0560570fed977788a86fa038b898564dfaEvan Cheng MachineInstr* MI, 3678e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops, 368c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const { 369c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return 0; 370c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman } 371c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 372c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 373c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 374c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 375c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 376c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 377c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 378c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 37943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 38043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 38143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 382c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanpublic: 3832b00aebda9705b7d76e90e632a5de511e59c739dDan Gohman /// canFoldMemoryOperand - Returns true for the specified load / store if 38443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding is possible. 38543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual 3868e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman bool canFoldMemoryOperand(const MachineInstr *MI, 3878e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops) const { 38843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 38943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 39043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 39143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// unfoldMemoryOperand - Separate a single instruction which folded a load or 39243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// a store or a load and a store into two or more instruction. If this is 39343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible, returns true as well as the new instructions by reference. 39443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 39543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 396c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng SmallVectorImpl<MachineInstr*> &NewMIs) const{ 39743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 39843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 39943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 40043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 40143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<SDNode*> &NewNodes) const { 40243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 40343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 40443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 40543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 40643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// instruction after load / store are unfolded from an instruction of the 40743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified opcode. It returns zero if the specified unfolding is not 40843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible. 40943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 41043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson bool UnfoldLoad, bool UnfoldStore) const { 41143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 41243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 41343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 414c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// BlockHasNoFallThrough - Return true if the specified block does not 415c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// fall-through into its successor block. This is primarily used when a 416c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// branch is unanalyzable. It is useful for things like unconditional 417c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// indirect branches (jump tables). 4188e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 419c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner return false; 420c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner } 421c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner 4225f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 4235f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 4245f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 42544eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 42644eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 4275f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 428905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 4290271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 43065e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 43165e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 43265e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 433b6bbfebdc683a6a123410bca1175e14d264d4bc2Chris Lattner MachineBasicBlock::iterator MI) const; 434b6bbfebdc683a6a123410bca1175e14d264d4bc2Chris Lattner 435bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isPredicated - Returns true if the instruction is already predicated. 4364f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// 437f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual bool isPredicated(const MachineInstr *MI) const { 4384f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 4394f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 4404f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 441bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isUnpredicatedTerminator - Returns true if the instruction is a 442bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// terminator instruction that has not been predicated. 443318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 444bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng 4450402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// PredicateInstruction - Convert the instruction into a predicated 44602c602b333ed2a1a13a17981f3c3f2f5463d5e5cEvan Cheng /// instruction. It returns true if the operation was successful. 447f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 448f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool PredicateInstruction(MachineInstr *MI, 44944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const = 0; 4504f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 451bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// SubsumesPredicate - Returns true if the first specified predicate 4524f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// subsumes the second, e.g. GE subsumes GT. 453f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 45444eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 45544eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred2) const { 4564f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 4574f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 4580402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 459ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// DefinesPredicate - If the specified instruction defines any predicate 460ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// or condition code register(s) used for predication, returns true as well 461ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// as the definition predicate(s) by reference. 462ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng virtual bool DefinesPredicate(MachineInstr *MI, 463ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng std::vector<MachineOperand> &Pred) const { 464ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return false; 465ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 466ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 4674350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 4684350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// instruction that defines the specified register class. 4694350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 47023066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng return true; 47123066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng } 47223066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng 47352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// GetInstSize - Returns the size of the specified Instruction. 47452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 47552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 47652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 47752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 0; 47852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 47952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 480d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// GetFunctionSizeInBytes - Returns the size of the specified 481d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// MachineFunction. 48252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 48352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 484d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner 485d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// Measure the specified inline asm to determine an approximation of its 486d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// length. 487d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner virtual unsigned getInlineAsmLength(const char *Str, 48833adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo &MAI) const; 489a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 490a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 491641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfoImpl - This is the default implementation of 492641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfo, which just provides a couple of default implementations 493641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// for various methods. This separated out because it is implemented in 494641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// libcodegen, not in libtarget. 495641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass TargetInstrInfoImpl : public TargetInstrInfo { 496641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerprotected: 497749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 498641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfo(desc, NumOpcodes) {} 499641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerpublic: 50058dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 50158dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const; 502261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 503261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const; 504641055225092833197efe8e5bce01d50bcf1daaeChris Lattner virtual bool PredicateInstruction(MachineInstr *MI, 50544eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const; 506ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 507ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 508378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubReg, 509ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng const MachineInstr *Orig) const; 51052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 511641055225092833197efe8e5bce01d50bcf1daaeChris Lattner}; 512641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 513d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 514d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 515a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 516