TargetInstrInfo.h revision ae72f4a642192abab5a2d10592200a94fcba61de
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 56fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// This file was developed by the LLVM research group and is distributed under 66fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// the University of Illinois Open Source License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 10a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// This file describes the target machine instructions to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos#include "llvm/CodeGen/MachineBasicBlock.h" 18551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/DataTypes.h" 192cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner#include <vector> 20be67780f31958b05ad3c510ca3a973d327517e86Chris Lattner#include <cassert> 21a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 22d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 23d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 245684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass MachineInstr; 25f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattnerclass TargetMachine; 265684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass Value; 27588668d4681bf928e09534c373b1bcf86757f899Vikram S. Adveclass Type; 285684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass Instruction; 292cc214c06cbb94f95928636981c9805d6300cff1Chris Lattnerclass Constant; 30e7506a366e8bd56c97d10beb68e4db953aebaecaChris Lattnerclass Function; 31c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adveclass MachineCodeForInstruction; 32ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetRegisterClass; 33a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 34f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 35f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner// Data types used to define information about a single machine instruction 36f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 37a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 38ab8672c8bb83e722b856eac67863542ea7e0cbb2Alkis Evlogimenostypedef short MachineOpCode; 39c188b733babbcdb0ff51613d0bb133e0496963b6Chris Lattnertypedef unsigned InstrSchedClass; 40a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 41a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//--------------------------------------------------------------------------- 423501feab811c86c9659248a4875fc31a3165f84dChris Lattner// struct TargetInstrDescriptor: 4300876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Predefined information about each machine instruction. 4400876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Designed to initialized statically. 453501feab811c86c9659248a4875fc31a3165f84dChris Lattner// 46a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 4700876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_NOP_FLAG = 1 << 0; 4800876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_BRANCH_FLAG = 1 << 1; 4900876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_CALL_FLAG = 1 << 2; 5000876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_RET_FLAG = 1 << 3; 5100876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_BARRIER_FLAG = 1 << 4; 5200876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_DELAY_SLOT_FLAG = 1 << 5; 5300876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_CC_FLAG = 1 << 6; 5400876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_LOAD_FLAG = 1 << 7; 5500876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_STORE_FLAG = 1 << 8; 5615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 5715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 5800876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukmanconst unsigned M_2_ADDR_FLAG = 1 << 9; 5915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 6015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 6115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// changed into a 3-address instruction if the first two operands cannot be 6215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// assigned to the same register. The target must implement the 6315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// TargetInstrInfo::convertToThreeAddress method for this instruction. 6415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattnerconst unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 10; 6515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 6615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 6715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// Z), which produces the same result if Y and Z are exchanged. 6815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattnerconst unsigned M_COMMUTABLE = 1 << 11; 69a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 70075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 71075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// block? Typically this is things like return and branch instructions. 72075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// Various passes use this to insert code into the bottom of a basic block, but 73075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// before control flow occurs. 7415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattnerconst unsigned M_TERMINATOR_FLAG = 1 << 12; 75075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner 76ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// TargetOperandInfo - This holds information about one operand of a machine 77ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// instruction, indicating the register class for register operands, etc. 78ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// 79ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetOperandInfo { 80ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerpublic: 81ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// RegClass - This specifies the register class of the operand if the 82ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// operand is a register. If not, this contains null. 83ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner const TargetRegisterClass *RegClass; 84ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 85ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// Currently no other information. 86ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner}; 87ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 88ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 891fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerclass TargetInstrDescriptor { 901fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerpublic: 914683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner const char * Name; // Assembly language mnemonic for the opcode. 92c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner int numOperands; // Number of args; -1 if variable #args 93c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner int resultPos; // Position of the result; -1 if no result 94e28adaa633393d5beea7f8e97951cbe1e3cd1646Brian Gaeke unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0. 9500876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 9675e961ae6b2e2801160e560057ad97ece4443986Chris Lattner // smallest -ve value is -(maxImmedConst+1). 97c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned numDelaySlots; // Number of delay slots after instruction 9875e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned latency; // Latency in machine cycles 9975e961ae6b2e2801160e560057ad97ece4443986Chris Lattner InstrSchedClass schedClass; // enum identifying instr sched class 10075e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned Flags; // flags identifying machine instr class 10175e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned TSFlags; // Target Specific Flag values 102f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitUses; // Registers implicitly read by this instr 103f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 104ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 105a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 106a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 107a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 1083501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 10934695381d626485a560594f162701088079589dfMisha Brukman/// 1103501feab811c86c9659248a4875fc31a3165f84dChris Lattner/// TargetInstrInfo - Interface to description of machine instructions 11134695381d626485a560594f162701088079589dfMisha Brukman/// 112075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 113075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner const TargetInstrDescriptor* desc; // raw array to allow static init'n 114bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned NumOpcodes; // number of entries in the desc array 115075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner unsigned numRealOpCodes; // number of non-dummy op codes 11634695381d626485a560594f162701088079589dfMisha Brukman 117075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 118075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 119a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 120bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 121075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 12270535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 1239ca5a2a33e98b0a93dc335a00f4d63aeb9a192b8Chris Lattner // Invariant: All instruction sets use opcode #0 as the PHI instruction 1249ca5a2a33e98b0a93dc335a00f4d63aeb9a192b8Chris Lattner enum { PHI = 0 }; 12534695381d626485a560594f162701088079589dfMisha Brukman 126bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 12734695381d626485a560594f162701088079589dfMisha Brukman 128e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 129e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 130e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 1312441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 1322441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner assert((unsigned)Opcode < NumOpcodes); 1332441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return desc[Opcode]; 134a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 1354683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 1362441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const char *getName(MachineOpCode Opcode) const { 1372441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Name; 1384683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner } 13934695381d626485a560594f162701088079589dfMisha Brukman 1402441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner int getNumOperands(MachineOpCode Opcode) const { 1412441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).numOperands; 142a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 143450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 144450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 1452441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 1462441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).schedClass; 147a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 148d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 1492441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitUses(MachineOpCode Opcode) const { 1502441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitUses; 151d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 152d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 1532441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 1542441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitDefs; 155d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 156d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 157450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 158a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 159a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Query instruction class flags according to the machine-independent 160a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // flags listed above. 16134695381d626485a560594f162701088079589dfMisha Brukman // 1622441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isReturn(MachineOpCode Opcode) const { 1632441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_RET_FLAG; 164a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 165450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 1662441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isTwoAddrInstr(MachineOpCode Opcode) const { 1672441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_2_ADDR_FLAG; 1689ada014ec09579a7dd3833f779a1de82bd71bce1Misha Brukman } 169075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner bool isTerminatorInstr(unsigned Opcode) const { 170075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner return get(Opcode).Flags & M_TERMINATOR_FLAG; 171075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner } 172d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve 1730cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// Return true if the instruction is a register to register move 1740cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// and leave the source and dest operands in the passed parameters. 1755e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 1765e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& sourceReg, 1775e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& destReg) const { 1785e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 1795e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 1805e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 18115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 18215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 18315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// may be able to convert a two-address instruction into a true 18415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// three-address instruction on demand. This allows the X86 target (for 18515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 18615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 18715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 18815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 18915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// performed, otherwise it returns the new instruction. 19015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 19115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 19215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 19315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 19415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 195d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// commuteInstruction - If a target has any instructions that are commutable, 196d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// but require converting to a different instruction or making non-trivial 197d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// changes to commute them, this method can overloaded to do this. The 198d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// default implementation of this method simply swaps the first two operands 199d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// of MI and returns it. 200d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 201d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// If a target wants to make more aggressive changes, they can construct and 202d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// return a new machine instruction. If an instruction cannot commute, it 203d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// can also return null. 204d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 205d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 206d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 207e4d32f6cf96566f8d37e50212e4f67330150ee20Alkis Evlogimenos /// Insert a goto (unconditional branch) sequence to TMBB, at the 208e4d32f6cf96566f8d37e50212e4f67330150ee20Alkis Evlogimenos /// end of MBB 209e4d32f6cf96566f8d37e50212e4f67330150ee20Alkis Evlogimenos virtual void insertGoto(MachineBasicBlock& MBB, 210e4d32f6cf96566f8d37e50212e4f67330150ee20Alkis Evlogimenos MachineBasicBlock& TMBB) const { 211905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos assert(0 && "Target didn't implement insertGoto!"); 212905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 213450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 2140cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// Reverses the branch condition of the MachineInstr pointed by 2150cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// MI. The instruction is replaced and the new MI is returned. 216905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos virtual MachineBasicBlock::iterator 217096f58b09adb03b5b060e12b327cff57329909f7Alkis Evlogimenos reverseBranchCondition(MachineBasicBlock::iterator MI) const { 218905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos assert(0 && "Target didn't implement reverseBranchCondition!"); 219c2df129da9828406d97f708989b5151ed04dec6bChris Lattner abort(); 220c2df129da9828406d97f708989b5151ed04dec6bChris Lattner return MI; 221905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 222450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 223450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner //------------------------------------------------------------------------- 224450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner // Code generation support for creating individual machine instructions 225450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner // 226450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner // WARNING: These methods are Sparc specific 227450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner // 228450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED! 229450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner // 230450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner //------------------------------------------------------------------------- 231450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 2322441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner unsigned getNumDelaySlots(MachineOpCode Opcode) const { 2332441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).numDelaySlots; 234450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner } 2352441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isCCInstr(MachineOpCode Opcode) const { 2362441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_CC_FLAG; 237450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner } 2382441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isNop(MachineOpCode Opcode) const { 2392441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_NOP_FLAG; 240450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner } 2412441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isBranch(MachineOpCode Opcode) const { 2422441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_BRANCH_FLAG; 243450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner } 2442441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner /// isBarrier - Returns true if the specified instruction stops control flow 2452441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner /// from executing the instruction immediately following it. Examples include 2462441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner /// unconditional branches and return instructions. 2472441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isBarrier(MachineOpCode Opcode) const { 2482441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_BARRIER_FLAG; 249450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner } 250dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner 2512441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isCall(MachineOpCode Opcode) const { 2522441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_CALL_FLAG; 253450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner } 2542441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isLoad(MachineOpCode Opcode) const { 2552441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_LOAD_FLAG; 256450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner } 2572441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isStore(MachineOpCode Opcode) const { 2582441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_STORE_FLAG; 2592441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner } 260dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner 261dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 262dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner /// which must be filled by the code generator. 263dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner bool hasDelaySlot(unsigned Opcode) const { 26449db6fe193168239be2f5aa8b4201614b739e840Chris Lattner return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 265dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner } 266dcc4a6f705bacb66b98c58bb3b8c738d3e6df37bChris Lattner 2672441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner virtual bool hasResultInterlock(MachineOpCode Opcode) const { 268a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return true; 269a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 270b2f30a3792c84790fcf7f20bf581b963bb0a25d3Brian Gaeke 27134695381d626485a560594f162701088079589dfMisha Brukman // 272a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Latencies for individual instructions and instruction pairs 27334695381d626485a560594f162701088079589dfMisha Brukman // 2742441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner virtual int minLatency(MachineOpCode Opcode) const { 2752441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).latency; 276a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 27734695381d626485a560594f162701088079589dfMisha Brukman 2782441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner virtual int maxLatency(MachineOpCode Opcode) const { 2792441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).latency; 280a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 2814c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve 2824c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve // 2834c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve // Which operand holds an immediate constant? Returns -1 if none 28434695381d626485a560594f162701088079589dfMisha Brukman // 2852441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner virtual int getImmedConstantPos(MachineOpCode Opcode) const { 2864c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve return -1; // immediate position is machine specific, so say -1 == "none" 2874c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve } 28834695381d626485a560594f162701088079589dfMisha Brukman 289a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Check if the specified constant fits in the immediate field 290a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // of this machine instruction 29134695381d626485a560594f162701088079589dfMisha Brukman // 2922441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner virtual bool constantFitsInImmedField(MachineOpCode Opcode, 29300876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman int64_t intValue) const; 29434695381d626485a560594f162701088079589dfMisha Brukman 295e28adaa633393d5beea7f8e97951cbe1e3cd1646Brian Gaeke // Return the largest positive constant that can be held in the IMMED field 296a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // of this machine instruction. 297a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // isSignExtended is set to true if the value is sign-extended before use 298a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // (this is true for all immediate fields in SPARC instructions). 299a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Return 0 if the instruction has no IMMED field. 30034695381d626485a560594f162701088079589dfMisha Brukman // 3012441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner virtual uint64_t maxImmedConstant(MachineOpCode Opcode, 30200876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman bool &isSignExtended) const { 3032441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner isSignExtended = get(Opcode).immedIsSignExtended; 3042441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).maxImmedConst; 305a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 306a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 307a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 308d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 309d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 310a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 311