TargetInstrInfo.h revision 00b05bd703b0d50133aecf4ce9f48e96d14504b3
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===----------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_TARGETINSTRINFO_H 8#define LLVM_TARGET_TARGETINSTRINFO_H 9 10#include "Support/DataTypes.h" 11#include <vector> 12 13class MachineInstr; 14class TargetMachine; 15class Value; 16class Instruction; 17class Constant; 18class Function; 19class MachineCodeForInstruction; 20 21//--------------------------------------------------------------------------- 22// Data types used to define information about a single machine instruction 23//--------------------------------------------------------------------------- 24 25typedef int MachineOpCode; 26typedef unsigned InstrSchedClass; 27 28const MachineOpCode INVALID_MACHINE_OPCODE = -1; 29 30 31//--------------------------------------------------------------------------- 32// struct TargetInstrDescriptor: 33// Predefined information about each machine instruction. 34// Designed to initialized statically. 35// 36 37const unsigned M_NOP_FLAG = 1 << 0; 38const unsigned M_BRANCH_FLAG = 1 << 1; 39const unsigned M_CALL_FLAG = 1 << 2; 40const unsigned M_RET_FLAG = 1 << 3; 41const unsigned M_ARITH_FLAG = 1 << 4; 42const unsigned M_CC_FLAG = 1 << 6; 43const unsigned M_LOGICAL_FLAG = 1 << 6; 44const unsigned M_INT_FLAG = 1 << 7; 45const unsigned M_FLOAT_FLAG = 1 << 8; 46const unsigned M_CONDL_FLAG = 1 << 9; 47const unsigned M_LOAD_FLAG = 1 << 10; 48const unsigned M_PREFETCH_FLAG = 1 << 11; 49const unsigned M_STORE_FLAG = 1 << 12; 50const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 51const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction 52// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub 53const unsigned M_2_ADDR_FLAG = 1 << 15; 54 55// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 56// block? Typically this is things like return and branch instructions. 57// Various passes use this to insert code into the bottom of a basic block, but 58// before control flow occurs. 59const unsigned M_TERMINATOR_FLAG = 1 << 16; 60 61struct TargetInstrDescriptor { 62 const char * Name; // Assembly language mnemonic for the opcode. 63 int numOperands; // Number of args; -1 if variable #args 64 int resultPos; // Position of the result; -1 if no result 65 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 66 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 67 // smallest -ve value is -(maxImmedConst+1). 68 unsigned numDelaySlots; // Number of delay slots after instruction 69 unsigned latency; // Latency in machine cycles 70 InstrSchedClass schedClass; // enum identifying instr sched class 71 unsigned Flags; // flags identifying machine instr class 72 unsigned TSFlags; // Target Specific Flag values 73 const unsigned *ImplicitUses; // Registers implicitly read by this instr 74 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 75}; 76 77 78//--------------------------------------------------------------------------- 79/// 80/// TargetInstrInfo - Interface to description of machine instructions 81/// 82class TargetInstrInfo { 83 const TargetInstrDescriptor* desc; // raw array to allow static init'n 84 unsigned descSize; // number of entries in the desc array 85 unsigned numRealOpCodes; // number of non-dummy op codes 86 87 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 88 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 89public: 90 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize, 91 unsigned numRealOpCodes); 92 virtual ~TargetInstrInfo(); 93 94 // Invariant: All instruction sets use opcode #0 as the PHI instruction and 95 // opcode #1 as the noop instruction. 96 enum { 97 PHI = 0, NOOP = 1 98 }; 99 100 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 101 unsigned getNumTotalOpCodes() const { return descSize; } 102 103 /// get - Return the machine instruction descriptor that corresponds to the 104 /// specified instruction opcode. 105 /// 106 const TargetInstrDescriptor& get(MachineOpCode opCode) const { 107 assert(opCode >= 0 && opCode < (int)descSize); 108 return desc[opCode]; 109 } 110 111 /// print - Print out the specified machine instruction in the appropriate 112 /// target specific assembly language. If this method is not overridden, the 113 /// default implementation uses the crummy machine independant printer. 114 /// 115 virtual void print(const MachineInstr *MI, std::ostream &O, 116 const TargetMachine &TM) const; 117 118 const char *getName(MachineOpCode opCode) const { 119 return get(opCode).Name; 120 } 121 122 int getNumOperands(MachineOpCode opCode) const { 123 return get(opCode).numOperands; 124 } 125 126 int getResultPos(MachineOpCode opCode) const { 127 return get(opCode).resultPos; 128 } 129 130 unsigned getNumDelaySlots(MachineOpCode opCode) const { 131 return get(opCode).numDelaySlots; 132 } 133 134 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 135 return get(opCode).schedClass; 136 } 137 138 // 139 // Query instruction class flags according to the machine-independent 140 // flags listed above. 141 // 142 bool isNop(MachineOpCode opCode) const { 143 return get(opCode).Flags & M_NOP_FLAG; 144 } 145 bool isBranch(MachineOpCode opCode) const { 146 return get(opCode).Flags & M_BRANCH_FLAG; 147 } 148 bool isCall(MachineOpCode opCode) const { 149 return get(opCode).Flags & M_CALL_FLAG; 150 } 151 bool isReturn(MachineOpCode opCode) const { 152 return get(opCode).Flags & M_RET_FLAG; 153 } 154 bool isControlFlow(MachineOpCode opCode) const { 155 return get(opCode).Flags & M_BRANCH_FLAG 156 || get(opCode).Flags & M_CALL_FLAG 157 || get(opCode).Flags & M_RET_FLAG; 158 } 159 bool isArith(MachineOpCode opCode) const { 160 return get(opCode).Flags & M_ARITH_FLAG; 161 } 162 bool isCCInstr(MachineOpCode opCode) const { 163 return get(opCode).Flags & M_CC_FLAG; 164 } 165 bool isLogical(MachineOpCode opCode) const { 166 return get(opCode).Flags & M_LOGICAL_FLAG; 167 } 168 bool isIntInstr(MachineOpCode opCode) const { 169 return get(opCode).Flags & M_INT_FLAG; 170 } 171 bool isFloatInstr(MachineOpCode opCode) const { 172 return get(opCode).Flags & M_FLOAT_FLAG; 173 } 174 bool isConditional(MachineOpCode opCode) const { 175 return get(opCode).Flags & M_CONDL_FLAG; 176 } 177 bool isLoad(MachineOpCode opCode) const { 178 return get(opCode).Flags & M_LOAD_FLAG; 179 } 180 bool isPrefetch(MachineOpCode opCode) const { 181 return get(opCode).Flags & M_PREFETCH_FLAG; 182 } 183 bool isLoadOrPrefetch(MachineOpCode opCode) const { 184 return get(opCode).Flags & M_LOAD_FLAG 185 || get(opCode).Flags & M_PREFETCH_FLAG; 186 } 187 bool isStore(MachineOpCode opCode) const { 188 return get(opCode).Flags & M_STORE_FLAG; 189 } 190 bool isMemoryAccess(MachineOpCode opCode) const { 191 return get(opCode).Flags & M_LOAD_FLAG 192 || get(opCode).Flags & M_PREFETCH_FLAG 193 || get(opCode).Flags & M_STORE_FLAG; 194 } 195 bool isDummyPhiInstr(MachineOpCode opCode) const { 196 return get(opCode).Flags & M_DUMMY_PHI_FLAG; 197 } 198 bool isPseudoInstr(MachineOpCode opCode) const { 199 return get(opCode).Flags & M_PSEUDO_FLAG; 200 } 201 bool isTwoAddrInstr(MachineOpCode opCode) const { 202 return get(opCode).Flags & M_2_ADDR_FLAG; 203 } 204 bool isTerminatorInstr(unsigned Opcode) const { 205 return get(Opcode).Flags & M_TERMINATOR_FLAG; 206 } 207 208 // Check if an instruction can be issued before its operands are ready, 209 // or if a subsequent instruction that uses its result can be issued 210 // before the results are ready. 211 // Default to true since most instructions on many architectures allow this. 212 // 213 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 214 return true; 215 } 216 217 virtual bool hasResultInterlock(MachineOpCode opCode) const { 218 return true; 219 } 220 221 // 222 // Latencies for individual instructions and instruction pairs 223 // 224 virtual int minLatency(MachineOpCode opCode) const { 225 return get(opCode).latency; 226 } 227 228 virtual int maxLatency(MachineOpCode opCode) const { 229 return get(opCode).latency; 230 } 231 232 // 233 // Which operand holds an immediate constant? Returns -1 if none 234 // 235 virtual int getImmedConstantPos(MachineOpCode opCode) const { 236 return -1; // immediate position is machine specific, so say -1 == "none" 237 } 238 239 // Check if the specified constant fits in the immediate field 240 // of this machine instruction 241 // 242 virtual bool constantFitsInImmedField(MachineOpCode opCode, 243 int64_t intValue) const; 244 245 // Return the largest +ve constant that can be held in the IMMMED field 246 // of this machine instruction. 247 // isSignExtended is set to true if the value is sign-extended before use 248 // (this is true for all immediate fields in SPARC instructions). 249 // Return 0 if the instruction has no IMMED field. 250 // 251 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 252 bool &isSignExtended) const { 253 isSignExtended = get(opCode).immedIsSignExtended; 254 return get(opCode).maxImmedConst; 255 } 256 257 //------------------------------------------------------------------------- 258 // Queries about representation of LLVM quantities (e.g., constants) 259 //------------------------------------------------------------------------- 260 261 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 262 /// from memory into a register, i.e., cannot be set bitwise in register and 263 /// cannot use immediate fields of instructions. Note that this only makes 264 /// sense for primitive types. 265 /// 266 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 267 268 // Test if this constant may not fit in the immediate field of the 269 // machine instructions (probably) generated for this instruction. 270 // 271 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 272 const Instruction* I) const { 273 return true; // safe but very conservative 274 } 275 276 277 /// createNOPinstr - returns the target's implementation of NOP, which is 278 /// usually a pseudo-instruction, implemented by a degenerate version of 279 /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0 280 /// 281 virtual MachineInstr* createNOPinstr() const = 0; 282 283 /// isNOPinstr - since we no longer have a special NOP opcode, we need to know 284 /// if a given instruction is interpreted as an `official' NOP instr, i.e., 285 /// there may be more than one way to `do nothing' but only one canonical 286 /// way to slack off. 287 /// 288 virtual bool isNOPinstr(const MachineInstr &MI) const = 0; 289 290 //------------------------------------------------------------------------- 291 // Code generation support for creating individual machine instructions 292 // 293 // WARNING: These methods are Sparc specific 294 // 295 //------------------------------------------------------------------------- 296 297 // Get certain common op codes for the current target. this and all the 298 // Create* methods below should be moved to a machine code generation class 299 // 300 virtual MachineOpCode getNOPOpCode() const { abort(); } 301 302 // Create an instruction sequence to put the constant `val' into 303 // the virtual register `dest'. `val' may be a Constant or a 304 // GlobalValue, viz., the constant address of a global variable or function. 305 // The generated instructions are returned in `mvec'. 306 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 307 // Symbolic constants or constants that must be accessed from memory 308 // are added to the constant pool via MachineFunction::get(F). 309 // 310 virtual void CreateCodeToLoadConst(const TargetMachine& target, 311 Function* F, 312 Value* val, 313 Instruction* dest, 314 std::vector<MachineInstr*>& mvec, 315 MachineCodeForInstruction& mcfi) const { 316 abort(); 317 } 318 319 // Create an instruction sequence to copy an integer value `val' 320 // to a floating point value `dest' by copying to memory and back. 321 // val must be an integral type. dest must be a Float or Double. 322 // The generated instructions are returned in `mvec'. 323 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 324 // Any stack space required is allocated via mcff. 325 // 326 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 327 Function* F, 328 Value* val, 329 Instruction* dest, 330 std::vector<MachineInstr*>& mvec, 331 MachineCodeForInstruction& MI) const { 332 abort(); 333 } 334 335 // Similarly, create an instruction sequence to copy an FP value 336 // `val' to an integer value `dest' by copying to memory and back. 337 // The generated instructions are returned in `mvec'. 338 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 339 // Any stack space required is allocated via mcff. 340 // 341 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 342 Function* F, 343 Value* val, 344 Instruction* dest, 345 std::vector<MachineInstr*>& mvec, 346 MachineCodeForInstruction& MI) const { 347 abort(); 348 } 349 350 // Create instruction(s) to copy src to dest, for arbitrary types 351 // The generated instructions are returned in `mvec'. 352 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 353 // Any stack space required is allocated via mcff. 354 // 355 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 356 Function* F, 357 Value* src, 358 Instruction* dest, 359 std::vector<MachineInstr*>& mvec, 360 MachineCodeForInstruction& MI) const { 361 abort(); 362 } 363 364 // Create instruction sequence to produce a sign-extended register value 365 // from an arbitrary sized value (sized in bits, not bytes). 366 // The generated instructions are appended to `mvec'. 367 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 368 // Any stack space required is allocated via mcff. 369 // 370 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 371 Function* F, 372 Value* srcVal, 373 Value* destVal, 374 unsigned numLowBits, 375 std::vector<MachineInstr*>& mvec, 376 MachineCodeForInstruction& MI) const { 377 abort(); 378 } 379 380 // Create instruction sequence to produce a zero-extended register value 381 // from an arbitrary sized value (sized in bits, not bytes). 382 // The generated instructions are appended to `mvec'. 383 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 384 // Any stack space required is allocated via mcff. 385 // 386 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 387 Function* F, 388 Value* srcVal, 389 Value* destVal, 390 unsigned srcSizeInBits, 391 std::vector<MachineInstr*>& mvec, 392 MachineCodeForInstruction& mcfi) const { 393 abort(); 394 } 395}; 396 397#endif 398