TargetInstrInfo.h revision 21d03f2de0087d60dbf575d95924404a97852879
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/Support/DataTypes.h" 19#include <vector> 20#include <cassert> 21 22namespace llvm { 23 24class MachineInstr; 25class TargetMachine; 26class Value; 27class Type; 28class Instruction; 29class Constant; 30class Function; 31class MachineCodeForInstruction; 32class TargetRegisterClass; 33 34//--------------------------------------------------------------------------- 35// Data types used to define information about a single machine instruction 36//--------------------------------------------------------------------------- 37 38typedef short MachineOpCode; 39typedef unsigned InstrSchedClass; 40 41//--------------------------------------------------------------------------- 42// struct TargetInstrDescriptor: 43// Predefined information about each machine instruction. 44// Designed to initialized statically. 45// 46 47const unsigned M_BRANCH_FLAG = 1 << 0; 48const unsigned M_CALL_FLAG = 1 << 1; 49const unsigned M_RET_FLAG = 1 << 2; 50const unsigned M_BARRIER_FLAG = 1 << 3; 51const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 52const unsigned M_LOAD_FLAG = 1 << 5; 53const unsigned M_STORE_FLAG = 1 << 6; 54 55// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 56const unsigned M_2_ADDR_FLAG = 1 << 7; 57 58// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 59// changed into a 3-address instruction if the first two operands cannot be 60// assigned to the same register. The target must implement the 61// TargetInstrInfo::convertToThreeAddress method for this instruction. 62const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8; 63 64// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 65// Z), which produces the same result if Y and Z are exchanged. 66const unsigned M_COMMUTABLE = 1 << 9; 67 68// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 69// block? Typically this is things like return and branch instructions. 70// Various passes use this to insert code into the bottom of a basic block, but 71// before control flow occurs. 72const unsigned M_TERMINATOR_FLAG = 1 << 10; 73 74// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 75// insertion support when the DAG scheduler is inserting it into a machine basic 76// block. 77const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11; 78 79// Machine operand flags 80// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 81// requires a callback to look up its register class. 82const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 83 84/// TargetOperandInfo - This holds information about one operand of a machine 85/// instruction, indicating the register class for register operands, etc. 86/// 87class TargetOperandInfo { 88public: 89 /// RegClass - This specifies the register class of the operand if the 90 /// operand is a register. If not, this contains null. 91 const TargetRegisterClass *RegClass; 92 unsigned Flags; 93 /// Currently no other information. 94}; 95 96 97class TargetInstrDescriptor { 98public: 99 const char * Name; // Assembly language mnemonic for the opcode. 100 int numOperands; // Number of args; -1 if variable #args 101 InstrSchedClass schedClass; // enum identifying instr sched class 102 unsigned Flags; // flags identifying machine instr class 103 unsigned TSFlags; // Target Specific Flag values 104 const unsigned *ImplicitUses; // Registers implicitly read by this instr 105 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 106 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 107}; 108 109 110//--------------------------------------------------------------------------- 111/// 112/// TargetInstrInfo - Interface to description of machine instructions 113/// 114class TargetInstrInfo { 115 const TargetInstrDescriptor* desc; // raw array to allow static init'n 116 unsigned NumOpcodes; // number of entries in the desc array 117 unsigned numRealOpCodes; // number of non-dummy op codes 118 119 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 120 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 121public: 122 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 123 virtual ~TargetInstrInfo(); 124 125 // Invariant opcodes: All instruction sets have these as their low opcodes. 126 enum { 127 PHI = 0, 128 INLINEASM = 1 129 }; 130 131 unsigned getNumOpcodes() const { return NumOpcodes; } 132 133 /// get - Return the machine instruction descriptor that corresponds to the 134 /// specified instruction opcode. 135 /// 136 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 137 assert((unsigned)Opcode < NumOpcodes); 138 return desc[Opcode]; 139 } 140 141 const char *getName(MachineOpCode Opcode) const { 142 return get(Opcode).Name; 143 } 144 145 const TargetRegisterClass 146 *getInstrOperandRegClass(const TargetInstrDescriptor *II, unsigned Op) const { 147 const TargetOperandInfo &toi = II->OpInfo[Op]; 148 return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS) 149 ? getPointerRegClass() : toi.RegClass; 150 } 151 152 int getNumOperands(MachineOpCode Opcode) const { 153 return get(Opcode).numOperands; 154 } 155 156 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 157 return get(Opcode).schedClass; 158 } 159 160 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 161 return get(Opcode).ImplicitUses; 162 } 163 164 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 165 return get(Opcode).ImplicitDefs; 166 } 167 168 169 // 170 // Query instruction class flags according to the machine-independent 171 // flags listed above. 172 // 173 bool isReturn(MachineOpCode Opcode) const { 174 return get(Opcode).Flags & M_RET_FLAG; 175 } 176 177 bool isTwoAddrInstr(MachineOpCode Opcode) const { 178 return get(Opcode).Flags & M_2_ADDR_FLAG; 179 } 180 bool isCommutableInstr(MachineOpCode Opcode) const { 181 return get(Opcode).Flags & M_COMMUTABLE; 182 } 183 bool isTerminatorInstr(unsigned Opcode) const { 184 return get(Opcode).Flags & M_TERMINATOR_FLAG; 185 } 186 187 bool isBranch(MachineOpCode Opcode) const { 188 return get(Opcode).Flags & M_BRANCH_FLAG; 189 } 190 191 /// isBarrier - Returns true if the specified instruction stops control flow 192 /// from executing the instruction immediately following it. Examples include 193 /// unconditional branches and return instructions. 194 bool isBarrier(MachineOpCode Opcode) const { 195 return get(Opcode).Flags & M_BARRIER_FLAG; 196 } 197 198 bool isCall(MachineOpCode Opcode) const { 199 return get(Opcode).Flags & M_CALL_FLAG; 200 } 201 bool isLoad(MachineOpCode Opcode) const { 202 return get(Opcode).Flags & M_LOAD_FLAG; 203 } 204 bool isStore(MachineOpCode Opcode) const { 205 return get(Opcode).Flags & M_STORE_FLAG; 206 } 207 208 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 209 /// custom insertion support when the DAG scheduler is inserting it into a 210 /// machine basic block. 211 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 212 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 213 } 214 215 /// Return true if the instruction is a register to register move 216 /// and leave the source and dest operands in the passed parameters. 217 virtual bool isMoveInstr(const MachineInstr& MI, 218 unsigned& sourceReg, 219 unsigned& destReg) const { 220 return false; 221 } 222 223 /// isLoadFromStackSlot - If the specified machine instruction is a direct 224 /// load from a stack slot, return the virtual or physical register number of 225 /// the destination along with the FrameIndex of the loaded stack slot. If 226 /// not, return 0. This predicate must return 0 if the instruction has 227 /// any side effects other than loading from the stack slot. 228 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 229 return 0; 230 } 231 232 /// isStoreToStackSlot - If the specified machine instruction is a direct 233 /// store to a stack slot, return the virtual or physical register number of 234 /// the source reg along with the FrameIndex of the loaded stack slot. If 235 /// not, return 0. This predicate must return 0 if the instruction has 236 /// any side effects other than storing to the stack slot. 237 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 238 return 0; 239 } 240 241 /// convertToThreeAddress - This method must be implemented by targets that 242 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 243 /// may be able to convert a two-address instruction into a true 244 /// three-address instruction on demand. This allows the X86 target (for 245 /// example) to convert ADD and SHL instructions into LEA instructions if they 246 /// would require register copies due to two-addressness. 247 /// 248 /// This method returns a null pointer if the transformation cannot be 249 /// performed, otherwise it returns the new instruction. 250 /// 251 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 252 return 0; 253 } 254 255 /// commuteInstruction - If a target has any instructions that are commutable, 256 /// but require converting to a different instruction or making non-trivial 257 /// changes to commute them, this method can overloaded to do this. The 258 /// default implementation of this method simply swaps the first two operands 259 /// of MI and returns it. 260 /// 261 /// If a target wants to make more aggressive changes, they can construct and 262 /// return a new machine instruction. If an instruction cannot commute, it 263 /// can also return null. 264 /// 265 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 266 267 /// Insert a goto (unconditional branch) sequence to TMBB, at the 268 /// end of MBB 269 virtual void insertGoto(MachineBasicBlock& MBB, 270 MachineBasicBlock& TMBB) const { 271 assert(0 && "Target didn't implement insertGoto!"); 272 } 273 274 /// Reverses the branch condition of the MachineInstr pointed by 275 /// MI. The instruction is replaced and the new MI is returned. 276 virtual MachineBasicBlock::iterator 277 reverseBranchCondition(MachineBasicBlock::iterator MI) const { 278 assert(0 && "Target didn't implement reverseBranchCondition!"); 279 abort(); 280 return MI; 281 } 282 283 /// insertNoop - Insert a noop into the instruction stream at the specified 284 /// point. 285 virtual void insertNoop(MachineBasicBlock &MBB, 286 MachineBasicBlock::iterator MI) const { 287 assert(0 && "Target didn't implement insertNoop!"); 288 abort(); 289 } 290 291 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 292 /// values. 293 virtual const TargetRegisterClass *getPointerRegClass() const { 294 assert(0 && "Target didn't implement getPointerRegClass!"); 295 abort(); 296 } 297 298 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 299 /// which must be filled by the code generator. 300 bool hasDelaySlot(unsigned Opcode) const { 301 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 302 } 303}; 304 305} // End llvm namespace 306 307#endif 308