TargetInstrInfo.h revision 23ed52752bb40a9085c9d36bbc6603972c3e0080
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Support/ErrorHandling.h" 18#include "llvm/Target/TargetInstrDesc.h" 19#include "llvm/CodeGen/MachineFunction.h" 20 21namespace llvm { 22 23class TargetRegisterClass; 24class TargetRegisterInfo; 25class LiveVariables; 26class CalleeSavedInfo; 27class SDNode; 28class SelectionDAG; 29 30template<class T> class SmallVectorImpl; 31 32 33//--------------------------------------------------------------------------- 34/// 35/// TargetInstrInfo - Interface to description of machine instruction set 36/// 37class TargetInstrInfo { 38 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 39 unsigned NumOpcodes; // Number of entries in the desc array 40 41 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 42 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 43public: 44 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 45 virtual ~TargetInstrInfo(); 46 47 // Invariant opcodes: All instruction sets have these as their low opcodes. 48 enum { 49 PHI = 0, 50 INLINEASM = 1, 51 DBG_LABEL = 2, 52 EH_LABEL = 3, 53 GC_LABEL = 4, 54 DECLARE = 5, 55 56 /// EXTRACT_SUBREG - This instruction takes two operands: a register 57 /// that has subregisters, and a subregister index. It returns the 58 /// extracted subregister value. This is commonly used to implement 59 /// truncation operations on target architectures which support it. 60 EXTRACT_SUBREG = 6, 61 62 /// INSERT_SUBREG - This instruction takes three operands: a register 63 /// that has subregisters, a register providing an insert value, and a 64 /// subregister index. It returns the value of the first register with 65 /// the value of the second register inserted. The first register is 66 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 67 /// anyext operations on target architectures which support it. 68 INSERT_SUBREG = 7, 69 70 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 71 IMPLICIT_DEF = 8, 72 73 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 74 /// that the first operand is an immediate integer constant. This constant 75 /// is often zero, as is commonly used to implement zext operations on 76 /// target architectures which support it, such as with x86-64 (with 77 /// zext from i32 to i64 via implicit zero-extension). 78 SUBREG_TO_REG = 9, 79 80 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 81 /// register-to-register copy into a specific register class. This is only 82 /// used between instruction selection and MachineInstr creation, before 83 /// virtual registers have been created for all the instructions, and it's 84 /// only needed in cases where the register classes implied by the 85 /// instructions are insufficient. The actual MachineInstrs to perform 86 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 87 COPY_TO_REGCLASS = 10 88 }; 89 90 unsigned getNumOpcodes() const { return NumOpcodes; } 91 92 /// get - Return the machine instruction descriptor that corresponds to the 93 /// specified instruction opcode. 94 /// 95 const TargetInstrDesc &get(unsigned Opcode) const { 96 assert(Opcode < NumOpcodes && "Invalid opcode!"); 97 return Descriptors[Opcode]; 98 } 99 100 /// isTriviallyReMaterializable - Return true if the instruction is trivially 101 /// rematerializable, meaning it has no side effects and requires no operands 102 /// that aren't always available. 103 bool isTriviallyReMaterializable(const MachineInstr *MI) const { 104 return MI->getDesc().isRematerializable() && 105 isReallyTriviallyReMaterializable(MI); 106 } 107 108protected: 109 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 110 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 111 /// instruction itself is actually trivially rematerializable, considering 112 /// its operands. This is used for targets that have instructions that are 113 /// only trivially rematerializable for specific uses. This predicate must 114 /// return false if the instruction has any side effects other than 115 /// producing a value, or if it requres any address registers that are not 116 /// always available. 117 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 118 return true; 119 } 120 121public: 122 /// Return true if the instruction is a register to register move and return 123 /// the source and dest operands and their sub-register indices by reference. 124 virtual bool isMoveInstr(const MachineInstr& MI, 125 unsigned& SrcReg, unsigned& DstReg, 126 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 127 return false; 128 } 129 130 /// isLoadFromStackSlot - If the specified machine instruction is a direct 131 /// load from a stack slot, return the virtual or physical register number of 132 /// the destination along with the FrameIndex of the loaded stack slot. If 133 /// not, return 0. This predicate must return 0 if the instruction has 134 /// any side effects other than loading from the stack slot. 135 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 136 int &FrameIndex) const { 137 return 0; 138 } 139 140 /// isStoreToStackSlot - If the specified machine instruction is a direct 141 /// store to a stack slot, return the virtual or physical register number of 142 /// the source reg along with the FrameIndex of the loaded stack slot. If 143 /// not, return 0. This predicate must return 0 if the instruction has 144 /// any side effects other than storing to the stack slot. 145 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 146 int &FrameIndex) const { 147 return 0; 148 } 149 150 /// reMaterialize - Re-issue the specified 'original' instruction at the 151 /// specific location targeting a new destination register. 152 virtual void reMaterialize(MachineBasicBlock &MBB, 153 MachineBasicBlock::iterator MI, 154 unsigned DestReg, unsigned SubIdx, 155 const MachineInstr *Orig) const = 0; 156 157 /// isInvariantLoad - Return true if the specified instruction (which is 158 /// marked mayLoad) is loading from a location whose value is invariant across 159 /// the function. For example, loading a value from the constant pool or from 160 /// from the argument area of a function if it does not change. This should 161 /// only return true of *all* loads the instruction does are invariant (if it 162 /// does multiple loads). 163 virtual bool isInvariantLoad(const MachineInstr *MI) const { 164 return false; 165 } 166 167 /// convertToThreeAddress - This method must be implemented by targets that 168 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 169 /// may be able to convert a two-address instruction into one or more true 170 /// three-address instructions on demand. This allows the X86 target (for 171 /// example) to convert ADD and SHL instructions into LEA instructions if they 172 /// would require register copies due to two-addressness. 173 /// 174 /// This method returns a null pointer if the transformation cannot be 175 /// performed, otherwise it returns the last new instruction. 176 /// 177 virtual MachineInstr * 178 convertToThreeAddress(MachineFunction::iterator &MFI, 179 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 180 return 0; 181 } 182 183 /// commuteInstruction - If a target has any instructions that are commutable, 184 /// but require converting to a different instruction or making non-trivial 185 /// changes to commute them, this method can overloaded to do this. The 186 /// default implementation of this method simply swaps the first two operands 187 /// of MI and returns it. 188 /// 189 /// If a target wants to make more aggressive changes, they can construct and 190 /// return a new machine instruction. If an instruction cannot commute, it 191 /// can also return null. 192 /// 193 /// If NewMI is true, then a new machine instruction must be created. 194 /// 195 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 196 bool NewMI = false) const = 0; 197 198 /// findCommutedOpIndices - If specified MI is commutable, return the two 199 /// operand indices that would swap value. Return true if the instruction 200 /// is not in a form which this routine understands. 201 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 202 unsigned &SrcOpIdx2) const = 0; 203 204 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 205 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 206 /// implemented for a target). Upon success, this returns false and returns 207 /// with the following information in various cases: 208 /// 209 /// 1. If this block ends with no branches (it just falls through to its succ) 210 /// just return false, leaving TBB/FBB null. 211 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 212 /// the destination block. 213 /// 3. If this block ends with an conditional branch and it falls through to 214 /// an successor block, it sets TBB to be the branch destination block and 215 /// a list of operands that evaluate the condition. These 216 /// operands can be passed to other TargetInstrInfo methods to create new 217 /// branches. 218 /// 4. If this block ends with an conditional branch and an unconditional 219 /// block, it returns the 'true' destination in TBB, the 'false' 220 /// destination in FBB, and a list of operands that evaluate the condition. 221 /// These operands can be passed to other TargetInstrInfo methods to create 222 /// new branches. 223 /// 224 /// Note that RemoveBranch and InsertBranch must be implemented to support 225 /// cases where this method returns success. 226 /// 227 /// If AllowModify is true, then this routine is allowed to modify the basic 228 /// block (e.g. delete instructions after the unconditional branch). 229 /// 230 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 231 MachineBasicBlock *&FBB, 232 SmallVectorImpl<MachineOperand> &Cond, 233 bool AllowModify = false) const { 234 return true; 235 } 236 237 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 238 /// This is only invoked in cases where AnalyzeBranch returns success. It 239 /// returns the number of instructions that were removed. 240 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 241 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 242 return 0; 243 } 244 245 /// InsertBranch - Insert a branch into the end of the specified 246 /// MachineBasicBlock. This operands to this method are the same as those 247 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 248 /// returns success and when an unconditional branch (TBB is non-null, FBB is 249 /// null, Cond is empty) needs to be inserted. It returns the number of 250 /// instructions inserted. 251 /// 252 /// It is also invoked by tail merging to add unconditional branches in 253 /// cases where AnalyzeBranch doesn't apply because there was no original 254 /// branch to analyze. At least this much must be implemented, else tail 255 /// merging needs to be disabled. 256 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 257 MachineBasicBlock *FBB, 258 const SmallVectorImpl<MachineOperand> &Cond) const { 259 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 260 return 0; 261 } 262 263 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 264 /// returns false if the target does not how to copy between the specified 265 /// registers. 266 virtual bool copyRegToReg(MachineBasicBlock &MBB, 267 MachineBasicBlock::iterator MI, 268 unsigned DestReg, unsigned SrcReg, 269 const TargetRegisterClass *DestRC, 270 const TargetRegisterClass *SrcRC) const { 271 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 272 return false; 273 } 274 275 /// storeRegToStackSlot - Store the specified register of the given register 276 /// class to the specified stack frame index. The store instruction is to be 277 /// added to the given machine basic block before the specified machine 278 /// instruction. If isKill is true, the register operand is the last use and 279 /// must be marked kill. 280 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 281 MachineBasicBlock::iterator MI, 282 unsigned SrcReg, bool isKill, int FrameIndex, 283 const TargetRegisterClass *RC) const { 284 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 285 } 286 287 /// loadRegFromStackSlot - Load the specified register of the given register 288 /// class from the specified stack frame index. The load instruction is to be 289 /// added to the given machine basic block before the specified machine 290 /// instruction. 291 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 292 MachineBasicBlock::iterator MI, 293 unsigned DestReg, int FrameIndex, 294 const TargetRegisterClass *RC) const { 295 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 296 } 297 298 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 299 /// saved registers and returns true if it isn't possible / profitable to do 300 /// so by issuing a series of store instructions via 301 /// storeRegToStackSlot(). Returns false otherwise. 302 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 303 MachineBasicBlock::iterator MI, 304 const std::vector<CalleeSavedInfo> &CSI) const { 305 return false; 306 } 307 308 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 309 /// saved registers and returns true if it isn't possible / profitable to do 310 /// so by issuing a series of load instructions via loadRegToStackSlot(). 311 /// Returns false otherwise. 312 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 313 MachineBasicBlock::iterator MI, 314 const std::vector<CalleeSavedInfo> &CSI) const { 315 return false; 316 } 317 318 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 319 /// slot into the specified machine instruction for the specified operand(s). 320 /// If this is possible, a new instruction is returned with the specified 321 /// operand folded, otherwise NULL is returned. The client is responsible for 322 /// removing the old instruction and adding the new one in the instruction 323 /// stream. 324 MachineInstr* foldMemoryOperand(MachineFunction &MF, 325 MachineInstr* MI, 326 const SmallVectorImpl<unsigned> &Ops, 327 int FrameIndex) const; 328 329 /// foldMemoryOperand - Same as the previous version except it allows folding 330 /// of any load and store from / to any address, not just from a specific 331 /// stack slot. 332 MachineInstr* foldMemoryOperand(MachineFunction &MF, 333 MachineInstr* MI, 334 const SmallVectorImpl<unsigned> &Ops, 335 MachineInstr* LoadMI) const; 336 337protected: 338 /// foldMemoryOperandImpl - Target-dependent implementation for 339 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 340 /// take care of adding a MachineMemOperand to the newly created instruction. 341 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 342 MachineInstr* MI, 343 const SmallVectorImpl<unsigned> &Ops, 344 int FrameIndex) const { 345 return 0; 346 } 347 348 /// foldMemoryOperandImpl - Target-dependent implementation for 349 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 350 /// take care of adding a MachineMemOperand to the newly created instruction. 351 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 352 MachineInstr* MI, 353 const SmallVectorImpl<unsigned> &Ops, 354 MachineInstr* LoadMI) const { 355 return 0; 356 } 357 358public: 359 /// canFoldMemoryOperand - Returns true for the specified load / store if 360 /// folding is possible. 361 virtual 362 bool canFoldMemoryOperand(const MachineInstr *MI, 363 const SmallVectorImpl<unsigned> &Ops) const { 364 return false; 365 } 366 367 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 368 /// a store or a load and a store into two or more instruction. If this is 369 /// possible, returns true as well as the new instructions by reference. 370 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 371 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 372 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 373 return false; 374 } 375 376 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 377 SmallVectorImpl<SDNode*> &NewNodes) const { 378 return false; 379 } 380 381 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 382 /// instruction after load / store are unfolded from an instruction of the 383 /// specified opcode. It returns zero if the specified unfolding is not 384 /// possible. 385 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 386 bool UnfoldLoad, bool UnfoldStore) const { 387 return 0; 388 } 389 390 /// BlockHasNoFallThrough - Return true if the specified block does not 391 /// fall-through into its successor block. This is primarily used when a 392 /// branch is unanalyzable. It is useful for things like unconditional 393 /// indirect branches (jump tables). 394 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 395 return false; 396 } 397 398 /// ReverseBranchCondition - Reverses the branch condition of the specified 399 /// condition list, returning false on success and true if it cannot be 400 /// reversed. 401 virtual 402 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 403 return true; 404 } 405 406 /// insertNoop - Insert a noop into the instruction stream at the specified 407 /// point. 408 virtual void insertNoop(MachineBasicBlock &MBB, 409 MachineBasicBlock::iterator MI) const { 410 llvm_unreachable("Target didn't implement insertNoop!"); 411 } 412 413 /// isPredicated - Returns true if the instruction is already predicated. 414 /// 415 virtual bool isPredicated(const MachineInstr *MI) const { 416 return false; 417 } 418 419 /// isUnpredicatedTerminator - Returns true if the instruction is a 420 /// terminator instruction that has not been predicated. 421 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 422 423 /// PredicateInstruction - Convert the instruction into a predicated 424 /// instruction. It returns true if the operation was successful. 425 virtual 426 bool PredicateInstruction(MachineInstr *MI, 427 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 428 429 /// SubsumesPredicate - Returns true if the first specified predicate 430 /// subsumes the second, e.g. GE subsumes GT. 431 virtual 432 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 433 const SmallVectorImpl<MachineOperand> &Pred2) const { 434 return false; 435 } 436 437 /// DefinesPredicate - If the specified instruction defines any predicate 438 /// or condition code register(s) used for predication, returns true as well 439 /// as the definition predicate(s) by reference. 440 virtual bool DefinesPredicate(MachineInstr *MI, 441 std::vector<MachineOperand> &Pred) const { 442 return false; 443 } 444 445 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 446 /// instruction that defines the specified register class. 447 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 448 return true; 449 } 450 451 /// isDeadInstruction - Return true if the instruction is considered dead. 452 /// This allows some late codegen passes to delete them. 453 virtual bool isDeadInstruction(const MachineInstr *MI) const = 0; 454 455 /// GetInstSize - Returns the size of the specified Instruction. 456 /// 457 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 458 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 459 return 0; 460 } 461 462 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction. 463 /// 464 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 465}; 466 467/// TargetInstrInfoImpl - This is the default implementation of 468/// TargetInstrInfo, which just provides a couple of default implementations 469/// for various methods. This separated out because it is implemented in 470/// libcodegen, not in libtarget. 471class TargetInstrInfoImpl : public TargetInstrInfo { 472protected: 473 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 474 : TargetInstrInfo(desc, NumOpcodes) {} 475public: 476 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 477 bool NewMI = false) const; 478 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 479 unsigned &SrcOpIdx2) const; 480 virtual bool PredicateInstruction(MachineInstr *MI, 481 const SmallVectorImpl<MachineOperand> &Pred) const; 482 virtual void reMaterialize(MachineBasicBlock &MBB, 483 MachineBasicBlock::iterator MI, 484 unsigned DestReg, unsigned SubReg, 485 const MachineInstr *Orig) const; 486 virtual bool isDeadInstruction(const MachineInstr *MI) const; 487 488 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 489}; 490 491/// getInstrOperandRegClass - Return register class of the operand of an 492/// instruction of the specified TargetInstrDesc. 493const TargetRegisterClass* 494getInstrOperandRegClass(const TargetRegisterInfo *TRI, 495 const TargetInstrDesc &II, unsigned Op); 496 497} // End llvm namespace 498 499#endif 500