TargetInstrInfo.h revision 4938d4528f80dd015c58dec9d6d72bc27bf26bbd
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file describes the target machine instructions to the code generator. 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===---------------------------------------------------------------------===// 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define LLVM_TARGET_MACHINEINSTRINFO_H 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 10f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles)#include "llvm/Target/TargetMachine.h" 11f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles)#include "llvm/Support/DataTypes.h" 12f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles)#include <vector> 13f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) 14f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles)class MachineInstrDescriptor; 15f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles)class TmpInstruction; 16f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles)class MachineInstr; 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class Value; 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class Instruction; 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)typedef int InstrSchedClass; 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Global variable holding an array of descriptors for machine instructions. 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The actual object needs to be created separately for each target machine. 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This variable is initialized and reset by class MachineInstrInfo. 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// FIXME: This should be a property of the target so that more than one target 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// at a time can be active... 295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)extern const MachineInstrDescriptor *TargetInstrDescriptors; 315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//--------------------------------------------------------------------------- 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// struct MachineInstrDescriptor: 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Predefined information about each machine instruction. 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Designed to initialized statically. 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// class MachineInstructionInfo 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Interface to description of machine instructions 405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//--------------------------------------------------------------------------- 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_NOP_FLAG = 1; 455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_BRANCH_FLAG = 1 << 1; 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_CALL_FLAG = 1 << 2; 475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_RET_FLAG = 1 << 3; 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_ARITH_FLAG = 1 << 4; 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_CC_FLAG = 1 << 6; 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_LOGICAL_FLAG = 1 << 6; 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_INT_FLAG = 1 << 7; 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_FLOAT_FLAG = 1 << 8; 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_CONDL_FLAG = 1 << 9; 545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_LOAD_FLAG = 1 << 10; 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_PREFETCH_FLAG = 1 << 11; 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_STORE_FLAG = 1 << 12; 575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const unsigned int M_DUMMY_PHI_FLAG = 1 << 13; 585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)struct MachineInstrDescriptor { 61 string opCodeString; // Assembly language mnemonic for the opcode. 62 int numOperands; // Number of args; -1 if variable #args 63 int resultPos; // Position of the result; -1 if no result 64 unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0. 65 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 66 // smallest -ve value is -(maxImmedConst+1). 67 unsigned int numDelaySlots; // Number of delay slots after instruction 68 unsigned int latency; // Latency in machine cycles 69 InstrSchedClass schedClass; // enum identifying instr sched class 70 unsigned int iclass; // flags identifying machine instr class 71}; 72 73 74class MachineInstrInfo : public NonCopyableV { 75public: 76 const TargetMachine& target; 77 78protected: 79 const MachineInstrDescriptor* desc; // raw array to allow static init'n 80 unsigned int descSize; // number of entries in the desc array 81 unsigned int numRealOpCodes; // number of non-dummy op codes 82 83public: 84 MachineInstrInfo(const TargetMachine& tgt, 85 const MachineInstrDescriptor *desc, unsigned descSize, 86 unsigned numRealOpCodes); 87 virtual ~MachineInstrInfo(); 88 89 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 90 unsigned getNumTotalOpCodes() const { return descSize; } 91 92 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const { 93 assert(opCode >= 0 && opCode < (int)descSize); 94 return desc[opCode]; 95 } 96 97 int getNumOperands(MachineOpCode opCode) const { 98 return getDescriptor(opCode).numOperands; 99 } 100 101 int getResultPos(MachineOpCode opCode) const { 102 return getDescriptor(opCode).resultPos; 103 } 104 105 unsigned getNumDelaySlots(MachineOpCode opCode) const { 106 return getDescriptor(opCode).numDelaySlots; 107 } 108 109 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 110 return getDescriptor(opCode).schedClass; 111 } 112 113 // 114 // Query instruction class flags according to the machine-independent 115 // flags listed above. 116 // 117 unsigned int getIClass(MachineOpCode opCode) const { 118 return getDescriptor(opCode).iclass; 119 } 120 bool isNop(MachineOpCode opCode) const { 121 return getDescriptor(opCode).iclass & M_NOP_FLAG; 122 } 123 bool isBranch(MachineOpCode opCode) const { 124 return getDescriptor(opCode).iclass & M_BRANCH_FLAG; 125 } 126 bool isCall(MachineOpCode opCode) const { 127 return getDescriptor(opCode).iclass & M_CALL_FLAG; 128 } 129 bool isReturn(MachineOpCode opCode) const { 130 return getDescriptor(opCode).iclass & M_RET_FLAG; 131 } 132 bool isControlFlow(MachineOpCode opCode) const { 133 return getDescriptor(opCode).iclass & M_BRANCH_FLAG 134 || getDescriptor(opCode).iclass & M_CALL_FLAG 135 || getDescriptor(opCode).iclass & M_RET_FLAG; 136 } 137 bool isArith(MachineOpCode opCode) const { 138 return getDescriptor(opCode).iclass & M_RET_FLAG; 139 } 140 bool isCCInstr(MachineOpCode opCode) const { 141 return getDescriptor(opCode).iclass & M_CC_FLAG; 142 } 143 bool isLogical(MachineOpCode opCode) const { 144 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG; 145 } 146 bool isIntInstr(MachineOpCode opCode) const { 147 return getDescriptor(opCode).iclass & M_INT_FLAG; 148 } 149 bool isFloatInstr(MachineOpCode opCode) const { 150 return getDescriptor(opCode).iclass & M_FLOAT_FLAG; 151 } 152 bool isConditional(MachineOpCode opCode) const { 153 return getDescriptor(opCode).iclass & M_CONDL_FLAG; 154 } 155 bool isLoad(MachineOpCode opCode) const { 156 return getDescriptor(opCode).iclass & M_LOAD_FLAG; 157 } 158 bool isPrefetch(MachineOpCode opCode) const { 159 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 160 } 161 bool isLoadOrPrefetch(MachineOpCode opCode) const { 162 return getDescriptor(opCode).iclass & M_LOAD_FLAG 163 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 164 } 165 bool isStore(MachineOpCode opCode) const { 166 return getDescriptor(opCode).iclass & M_STORE_FLAG; 167 } 168 bool isMemoryAccess(MachineOpCode opCode) const { 169 return getDescriptor(opCode).iclass & M_LOAD_FLAG 170 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG 171 || getDescriptor(opCode).iclass & M_STORE_FLAG; 172 } 173 bool isDummyPhiInstr(const MachineOpCode opCode) const { 174 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG; 175 } 176 177 178 // delete this later ******* 179 bool isPhi(const MachineOpCode opCode) { return isDummyPhiInstr(opCode); } 180 181 182 // Check if an instruction can be issued before its operands are ready, 183 // or if a subsequent instruction that uses its result can be issued 184 // before the results are ready. 185 // Default to true since most instructions on many architectures allow this. 186 // 187 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 188 return true; 189 } 190 191 virtual bool hasResultInterlock(MachineOpCode opCode) const { 192 return true; 193 } 194 195 // 196 // Latencies for individual instructions and instruction pairs 197 // 198 virtual int minLatency(MachineOpCode opCode) const { 199 return getDescriptor(opCode).latency; 200 } 201 202 virtual int maxLatency(MachineOpCode opCode) const { 203 return getDescriptor(opCode).latency; 204 } 205 206 // Check if the specified constant fits in the immediate field 207 // of this machine instruction 208 // 209 virtual bool constantFitsInImmedField(MachineOpCode opCode, 210 int64_t intValue) const; 211 212 // Return the largest +ve constant that can be held in the IMMMED field 213 // of this machine instruction. 214 // isSignExtended is set to true if the value is sign-extended before use 215 // (this is true for all immediate fields in SPARC instructions). 216 // Return 0 if the instruction has no IMMED field. 217 // 218 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 219 bool &isSignExtended) const { 220 isSignExtended = getDescriptor(opCode).immedIsSignExtended; 221 return getDescriptor(opCode).maxImmedConst; 222 } 223 224 //------------------------------------------------------------------------- 225 // Code generation support for creating individual machine instructions 226 //------------------------------------------------------------------------- 227 228 // Create an instruction sequence to put the constant `val' into 229 // the virtual register `dest'. `val' may be a ConstPoolVal or a 230 // GlobalValue, viz., the constant address of a global variable or function. 231 // The generated instructions are returned in `minstrVec'. 232 // Any temp. registers (TmpInstruction) created are returned in `tempVec'. 233 // 234 virtual void CreateCodeToLoadConst(Value* val, 235 Instruction* dest, 236 vector<MachineInstr*>& minstrVec, 237 vector<TmpInstruction*>& temps) const =0; 238 239 // Create an instruction sequence to copy an integer value `val' 240 // to a floating point value `dest' by copying to memory and back. 241 // val must be an integral type. dest must be a Float or Double. 242 // The generated instructions are returned in `minstrVec'. 243 // Any temp. registers (TmpInstruction) created are returned in `tempVec'. 244 // 245 virtual void CreateCodeToCopyIntToFloat(Method* method, 246 Value* val, 247 Instruction* dest, 248 vector<MachineInstr*>& minstrVec, 249 vector<TmpInstruction*>& tempVec, 250 TargetMachine& target) const = 0; 251 252 // Similarly, create an instruction sequence to copy an FP value 253 // `val' to an integer value `dest' by copying to memory and back. 254 // See the previous function for information about return values. 255 // 256 virtual void CreateCodeToCopyFloatToInt(Method* method, 257 Value* val, 258 Instruction* dest, 259 vector<MachineInstr*>& minstrVec, 260 vector<TmpInstruction*>& tempVec, 261 TargetMachine& target) const = 0; 262}; 263 264#endif 265