TargetInstrInfo.h revision 749c6f6b5ed301c84aac562e414486549d7b98eb
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/Support/DataTypes.h" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class TargetRegisterClass; 26class LiveVariables; 27class CalleeSavedInfo; 28class SDNode; 29class SelectionDAG; 30 31template<class T> class SmallVectorImpl; 32 33//===----------------------------------------------------------------------===// 34// Machine Operand Flags and Description 35//===----------------------------------------------------------------------===// 36 37namespace TOI { 38 // Operand constraints: only "tied_to" for now. 39 enum OperandConstraint { 40 TIED_TO = 0 // Must be allocated the same register as. 41 }; 42 43 /// OperandFlags - These are flags set on operands, but should be considered 44 /// private, all access should go through the TargetOperandInfo accessors. 45 /// See the accessors for a description of what these are. 46 enum OperandFlags { 47 LookupPtrRegClass = 0, 48 Predicate, 49 OptionalDef 50 }; 51} 52 53/// TargetOperandInfo - This holds information about one operand of a machine 54/// instruction, indicating the register class for register operands, etc. 55/// 56class TargetOperandInfo { 57public: 58 /// RegClass - This specifies the register class enumeration of the operand 59 /// if the operand is a register. If not, this contains 0. 60 unsigned short RegClass; 61 unsigned short Flags; 62 /// Lower 16 bits are used to specify which constraints are set. The higher 16 63 /// bits are used to specify the value of constraints (4 bits each). 64 unsigned int Constraints; 65 /// Currently no other information. 66 67 /// isLookupPtrRegClass - Set if this operand is a pointer value and it 68 /// requires a callback to look up its register class. 69 bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);} 70 71 /// isPredicate - Set if this is one of the operands that made up of 72 /// the predicate operand that controls an isPredicable() instruction. 73 bool isPredicate() const { return Flags & (1 << TOI::Predicate); } 74 75 /// isOptionalDef - Set if this operand is a optional def. 76 /// 77 bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); } 78}; 79 80 81//===----------------------------------------------------------------------===// 82// Machine Instruction Flags and Description 83//===----------------------------------------------------------------------===// 84 85/// TargetInstrDesc flags - These should be considered private to the 86/// implementation of the TargetInstrDesc class. Clients should use the 87/// predicate methods on TargetInstrDesc, not use these directly. These 88/// all correspond to bitfields in the TargetInstrDesc::Flags field. 89namespace TID { 90 enum { 91 Variadic = 0, 92 HasOptionalDef, 93 Return, 94 Call, 95 ImplicitDef, 96 Barrier, 97 Terminator, 98 Branch, 99 IndirectBranch, 100 Predicable, 101 NotDuplicable, 102 DelaySlot, 103 SimpleLoad, 104 MayStore, 105 NeverHasSideEffects, 106 MayHaveSideEffects, 107 Commutable, 108 ConvertibleTo3Addr, 109 UsesCustomDAGSchedInserter, 110 Rematerializable 111 }; 112} 113 114/// TargetInstrDesc - Describe properties that are true of each 115/// instruction in the target description file. This captures information about 116/// side effects, register use and many other things. There is one instance of 117/// this struct for each target instruction class, and the MachineInstr class 118/// points to this struct directly to describe itself. 119class TargetInstrDesc { 120public: 121 unsigned short Opcode; // The opcode number. 122 unsigned short NumOperands; // Num of args (may be more if variable_ops) 123 unsigned short NumDefs; // Num of args that are definitions. 124 unsigned short SchedClass; // enum identifying instr sched class 125 const char * Name; // Name of the instruction record in td file. 126 unsigned Flags; // flags identifying machine instr class 127 unsigned TSFlags; // Target Specific Flag values 128 const unsigned *ImplicitUses; // Registers implicitly read by this instr 129 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 130 const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands. 131 132 /// getOperandConstraint - Returns the value of the specific constraint if 133 /// it is set. Returns -1 if it is not set. 134 int getOperandConstraint(unsigned OpNum, 135 TOI::OperandConstraint Constraint) const { 136 assert((OpNum < NumOperands || isVariadic()) && 137 "Invalid operand # of TargetInstrInfo"); 138 if (OpNum < NumOperands && 139 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 140 unsigned Pos = 16 + Constraint * 4; 141 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 142 } 143 return -1; 144 } 145 146 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 147 /// dest operand. Returns -1 if there isn't one. 148 int findTiedToSrcOperand(unsigned OpNum) const; 149 150 /// getOpcode - Return the opcode number for this descriptor. 151 unsigned getOpcode() const { 152 return Opcode; 153 } 154 155 /// getName - Return the name of the record in the .td file for this 156 /// instruction, for example "ADD8ri". 157 const char *getName() const { 158 return Name; 159 } 160 161 /// getNumOperands - Return the number of declared MachineOperands for this 162 /// MachineInstruction. Note that variadic (isVariadic() returns true) 163 /// instructions may have additional operands at the end of the list, and note 164 /// that the machine instruction may include implicit register def/uses as 165 /// well. 166 unsigned getNumOperands() const { 167 return NumOperands; 168 } 169 170 /// getNumDefs - Return the number of MachineOperands that are register 171 /// definitions. Register definitions always occur at the start of the 172 /// machine operand list. This is the number of "outs" in the .td file. 173 unsigned getNumDefs() const { 174 return NumDefs; 175 } 176 177 /// isVariadic - Return true if this instruction can have a variable number of 178 /// operands. In this case, the variable operands will be after the normal 179 /// operands but before the implicit definitions and uses (if any are 180 /// present). 181 bool isVariadic() const { 182 return Flags & (1 << TID::Variadic); 183 } 184 185 /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 186 /// ARM instructions which can set condition code if 's' bit is set. 187 bool hasOptionalDef() const { 188 return Flags & (1 << TID::HasOptionalDef); 189 } 190 191 /// getImplicitUses - Return a list of machine operands that are potentially 192 /// read by any instance of this machine instruction. For example, on X86, 193 /// the "adc" instruction adds two register operands and adds the carry bit in 194 /// from the flags register. In this case, the instruction is marked as 195 /// implicitly reading the flags. Likewise, the variable shift instruction on 196 /// X86 is marked as implicitly reading the 'CL' register, which it always 197 /// does. 198 /// 199 /// This method returns null if the instruction has no implicit uses. 200 const unsigned *getImplicitUses() const { 201 return ImplicitUses; 202 } 203 204 /// getImplicitDefs - Return a list of machine operands that are potentially 205 /// written by any instance of this machine instruction. For example, on X86, 206 /// many instructions implicitly set the flags register. In this case, they 207 /// are marked as setting the FLAGS. Likewise, many instructions always 208 /// deposit their result in a physical register. For example, the X86 divide 209 /// instruction always deposits the quotient and remainder in the EAX/EDX 210 /// registers. For that instruction, this will return a list containing the 211 /// EAX/EDX/EFLAGS registers. 212 /// 213 /// This method returns null if the instruction has no implicit uses. 214 const unsigned *getImplicitDefs() const { 215 return ImplicitDefs; 216 } 217 218 /// getSchedClass - Return the scheduling class for this instruction. The 219 /// scheduling class is an index into the InstrItineraryData table. This 220 /// returns zero if there is no known scheduling information for the 221 /// instruction. 222 /// 223 unsigned getSchedClass() const { 224 return SchedClass; 225 } 226 227 bool isReturn() const { 228 return Flags & (1 << TID::Return); 229 } 230 231 bool isCall() const { 232 return Flags & (1 << TID::Call); 233 } 234 235 /// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction, 236 /// which defines a register to an unspecified value. These basically 237 /// correspond to x = undef. 238 bool isImplicitDef() const { 239 return Flags & (1 << TID::ImplicitDef); 240 } 241 242 /// isBarrier - Returns true if the specified instruction stops control flow 243 /// from executing the instruction immediately following it. Examples include 244 /// unconditional branches and return instructions. 245 bool isBarrier() const { 246 return Flags & (1 << TID::Barrier); 247 } 248 249 /// isTerminator - Returns true if this instruction part of the terminator for 250 /// a basic block. Typically this is things like return and branch 251 /// instructions. 252 /// 253 /// Various passes use this to insert code into the bottom of a basic block, 254 /// but before control flow occurs. 255 bool isTerminator() const { 256 return Flags & (1 << TID::Terminator); 257 } 258 259 /// isBranch - Returns true if this is a conditional, unconditional, or 260 /// indirect branch. Predicates below can be used to discriminate between 261 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 262 /// get more information. 263 bool isBranch() const { 264 return Flags & (1 << TID::Branch); 265 } 266 267 /// isIndirectBranch - Return true if this is an indirect branch, such as a 268 /// branch through a register. 269 bool isIndirectBranch() const { 270 return Flags & (1 << TID::IndirectBranch); 271 } 272 273 /// isConditionalBranch - Return true if this is a branch which may fall 274 /// through to the next instruction or may transfer control flow to some other 275 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 276 /// information about this branch. 277 bool isConditionalBranch() const { 278 return isBranch() & !isBarrier() & !isIndirectBranch(); 279 } 280 281 /// isUnconditionalBranch - Return true if this is a branch which always 282 /// transfers control flow to some other block. The 283 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 284 /// about this branch. 285 bool isUnconditionalBranch() const { 286 return isBranch() & isBarrier() & !isIndirectBranch(); 287 } 288 289 // isPredicable - Return true if this instruction has a predicate operand that 290 // controls execution. It may be set to 'always', or may be set to other 291 /// values. There are various methods in TargetInstrInfo that can be used to 292 /// control and modify the predicate in this instruction. 293 bool isPredicable() const { 294 return Flags & (1 << TID::Predicable); 295 } 296 297 /// isNotDuplicable - Return true if this instruction cannot be safely 298 /// duplicated. For example, if the instruction has a unique labels attached 299 /// to it, duplicating it would cause multiple definition errors. 300 bool isNotDuplicable() const { 301 return Flags & (1 << TID::NotDuplicable); 302 } 303 304 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 305 /// which must be filled by the code generator. 306 bool hasDelaySlot() const { 307 return Flags & (1 << TID::DelaySlot); 308 } 309 310 /// isSimpleLoad - Return true for instructions that are simple loads from 311 /// memory. This should only be set on instructions that load a value from 312 /// memory and return it in their only virtual register definition. 313 /// Instructions that return a value loaded from memory and then modified in 314 /// some way should not return true for this. 315 bool isSimpleLoad() const { 316 return Flags & (1 << TID::SimpleLoad); 317 } 318 319 //===--------------------------------------------------------------------===// 320 // Side Effect Analysis 321 //===--------------------------------------------------------------------===// 322 323 /// mayStore - Return true if this instruction could possibly modify memory. 324 /// Instructions with this flag set are not necessarily simple store 325 /// instructions, they may store a modified value based on their operands, or 326 /// may not actually modify anything, for example. 327 bool mayStore() const { 328 return Flags & (1 << TID::MayStore); 329 } 330 331 // TODO: mayLoad. 332 333 /// hasNoSideEffects - Return true if all instances of this instruction are 334 /// guaranteed to have no side effects other than: 335 /// 1. The register operands that are def/used by the MachineInstr. 336 /// 2. Registers that are implicitly def/used by the MachineInstr. 337 /// 3. Memory Accesses captured by mayLoad() or mayStore(). 338 /// 339 /// Examples of other side effects would be calling a function, modifying 340 /// 'invisible' machine state like a control register, etc. 341 /// 342 /// If some instances of this instruction are side-effect free but others are 343 /// not, the hasConditionalSideEffects() property should return true, not this 344 /// one. 345 /// 346 /// Note that you should not call this method directly, instead, call the 347 /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis 348 /// of the machine instruction. 349 bool hasNoSideEffects() const { 350 return Flags & (1 << TID::NeverHasSideEffects); 351 } 352 353 /// hasConditionalSideEffects - Return true if some instances of this 354 /// instruction are guaranteed to have no side effects other than those listed 355 /// for hasNoSideEffects(). To determine whether a specific machineinstr has 356 /// side effects, the TargetInstrInfo::isReallySideEffectFree virtual method 357 /// is invoked to decide. 358 /// 359 /// Note that you should not call this method directly, instead, call the 360 /// TargetInstrInfo::hasUnmodelledSideEffects method, which handles analysis 361 /// of the machine instruction. 362 bool hasConditionalSideEffects() const { 363 return Flags & (1 << TID::MayHaveSideEffects); 364 } 365 366 //===--------------------------------------------------------------------===// 367 // Flags that indicate whether an instruction can be modified by a method. 368 //===--------------------------------------------------------------------===// 369 370 /// isCommutable - Return true if this may be a 2- or 3-address 371 /// instruction (of the form "X = op Y, Z, ..."), which produces the same 372 /// result if Y and Z are exchanged. If this flag is set, then the 373 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 374 /// instruction. 375 /// 376 /// Note that this flag may be set on instructions that are only commutable 377 /// sometimes. In these cases, the call to commuteInstruction will fail. 378 /// Also note that some instructions require non-trivial modification to 379 /// commute them. 380 bool isCommutable() const { 381 return Flags & (1 << TID::Commutable); 382 } 383 384 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 385 /// which can be changed into a 3-address instruction if needed. Doing this 386 /// transformation can be profitable in the register allocator, because it 387 /// means that the instruction can use a 2-address form if possible, but 388 /// degrade into a less efficient form if the source and dest register cannot 389 /// be assigned to the same register. For example, this allows the x86 390 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 391 /// is the same speed as the shift but has bigger code size. 392 /// 393 /// If this returns true, then the target must implement the 394 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 395 /// is allowed to fail if the transformation isn't valid for this specific 396 /// instruction (e.g. shl reg, 4 on x86). 397 /// 398 bool isConvertibleTo3Addr() const { 399 return Flags & (1 << TID::ConvertibleTo3Addr); 400 } 401 402 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 403 /// custom insertion support when the DAG scheduler is inserting it into a 404 /// machine basic block. If this is true for the instruction, it basically 405 /// means that it is a pseudo instruction used at SelectionDAG time that is 406 /// expanded out into magic code by the target when MachineInstrs are formed. 407 /// 408 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 409 /// is used to insert this into the MachineBasicBlock. 410 bool usesCustomDAGSchedInsertionHook() const { 411 return Flags & (1 << TID::UsesCustomDAGSchedInserter); 412 } 413 414 /// isRematerializable - Returns true if this instruction is a candidate for 415 /// remat. This flag is deprecated, please don't use it anymore. If this 416 /// flag is set, the isReallyTriviallyReMaterializable() method is called to 417 /// verify the instruction is really rematable. 418 bool isRematerializable() const { 419 return Flags & (1 << TID::Rematerializable); 420 } 421}; 422 423 424//--------------------------------------------------------------------------- 425/// 426/// TargetInstrInfo - Interface to description of machine instructions 427/// 428class TargetInstrInfo { 429 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 430 unsigned NumOpcodes; // Number of entries in the desc array 431 432 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 433 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 434public: 435 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 436 virtual ~TargetInstrInfo(); 437 438 // Invariant opcodes: All instruction sets have these as their low opcodes. 439 enum { 440 PHI = 0, 441 INLINEASM = 1, 442 LABEL = 2, 443 EXTRACT_SUBREG = 3, 444 INSERT_SUBREG = 4 445 }; 446 447 unsigned getNumOpcodes() const { return NumOpcodes; } 448 449 /// get - Return the machine instruction descriptor that corresponds to the 450 /// specified instruction opcode. 451 /// 452 const TargetInstrDesc &get(unsigned Opcode) const { 453 assert(Opcode < NumOpcodes && "Invalid opcode!"); 454 return Descriptors[Opcode]; 455 } 456 457 /// isTriviallyReMaterializable - Return true if the instruction is trivially 458 /// rematerializable, meaning it has no side effects and requires no operands 459 /// that aren't always available. 460 bool isTriviallyReMaterializable(MachineInstr *MI) const { 461 return MI->getDesc().isRematerializable() && 462 isReallyTriviallyReMaterializable(MI); 463 } 464 465 /// hasUnmodelledSideEffects - Returns true if the instruction has side 466 /// effects that are not captured by any operands of the instruction or other 467 /// flags. 468 bool hasUnmodelledSideEffects(MachineInstr *MI) const { 469 const TargetInstrDesc &TID = MI->getDesc(); 470 if (TID.hasNoSideEffects()) return false; 471 if (!TID.hasConditionalSideEffects()) return true; 472 return !isReallySideEffectFree(MI); // May have side effects 473 } 474protected: 475 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 476 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 477 /// instruction itself is actually trivially rematerializable, considering 478 /// its operands. This is used for targets that have instructions that are 479 /// only trivially rematerializable for specific uses. This predicate must 480 /// return false if the instruction has any side effects other than 481 /// producing a value, or if it requres any address registers that are not 482 /// always available. 483 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 484 return true; 485 } 486 487 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this 488 /// method is called to determine if the specific instance of this 489 /// instruction has side effects. This is useful in cases of instructions, 490 /// like loads, which generally always have side effects. A load from a 491 /// constant pool doesn't have side effects, though. So we need to 492 /// differentiate it from the general case. 493 virtual bool isReallySideEffectFree(MachineInstr *MI) const { 494 return false; 495 } 496public: 497 /// Return true if the instruction is a register to register move 498 /// and leave the source and dest operands in the passed parameters. 499 virtual bool isMoveInstr(const MachineInstr& MI, 500 unsigned& sourceReg, 501 unsigned& destReg) const { 502 return false; 503 } 504 505 /// isLoadFromStackSlot - If the specified machine instruction is a direct 506 /// load from a stack slot, return the virtual or physical register number of 507 /// the destination along with the FrameIndex of the loaded stack slot. If 508 /// not, return 0. This predicate must return 0 if the instruction has 509 /// any side effects other than loading from the stack slot. 510 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 511 return 0; 512 } 513 514 /// isStoreToStackSlot - If the specified machine instruction is a direct 515 /// store to a stack slot, return the virtual or physical register number of 516 /// the source reg along with the FrameIndex of the loaded stack slot. If 517 /// not, return 0. This predicate must return 0 if the instruction has 518 /// any side effects other than storing to the stack slot. 519 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 520 return 0; 521 } 522 523 /// convertToThreeAddress - This method must be implemented by targets that 524 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 525 /// may be able to convert a two-address instruction into one or more true 526 /// three-address instructions on demand. This allows the X86 target (for 527 /// example) to convert ADD and SHL instructions into LEA instructions if they 528 /// would require register copies due to two-addressness. 529 /// 530 /// This method returns a null pointer if the transformation cannot be 531 /// performed, otherwise it returns the last new instruction. 532 /// 533 virtual MachineInstr * 534 convertToThreeAddress(MachineFunction::iterator &MFI, 535 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 536 return 0; 537 } 538 539 /// commuteInstruction - If a target has any instructions that are commutable, 540 /// but require converting to a different instruction or making non-trivial 541 /// changes to commute them, this method can overloaded to do this. The 542 /// default implementation of this method simply swaps the first two operands 543 /// of MI and returns it. 544 /// 545 /// If a target wants to make more aggressive changes, they can construct and 546 /// return a new machine instruction. If an instruction cannot commute, it 547 /// can also return null. 548 /// 549 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0; 550 551 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 552 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 553 /// implemented for a target). Upon success, this returns false and returns 554 /// with the following information in various cases: 555 /// 556 /// 1. If this block ends with no branches (it just falls through to its succ) 557 /// just return false, leaving TBB/FBB null. 558 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 559 /// the destination block. 560 /// 3. If this block ends with an conditional branch and it falls through to 561 /// an successor block, it sets TBB to be the branch destination block and a 562 /// list of operands that evaluate the condition. These 563 /// operands can be passed to other TargetInstrInfo methods to create new 564 /// branches. 565 /// 4. If this block ends with an conditional branch and an unconditional 566 /// block, it returns the 'true' destination in TBB, the 'false' destination 567 /// in FBB, and a list of operands that evaluate the condition. These 568 /// operands can be passed to other TargetInstrInfo methods to create new 569 /// branches. 570 /// 571 /// Note that RemoveBranch and InsertBranch must be implemented to support 572 /// cases where this method returns success. 573 /// 574 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 575 MachineBasicBlock *&FBB, 576 std::vector<MachineOperand> &Cond) const { 577 return true; 578 } 579 580 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 581 /// this is only invoked in cases where AnalyzeBranch returns success. It 582 /// returns the number of instructions that were removed. 583 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 584 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 585 return 0; 586 } 587 588 /// InsertBranch - Insert a branch into the end of the specified 589 /// MachineBasicBlock. This operands to this method are the same as those 590 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 591 /// returns success and when an unconditional branch (TBB is non-null, FBB is 592 /// null, Cond is empty) needs to be inserted. It returns the number of 593 /// instructions inserted. 594 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 595 MachineBasicBlock *FBB, 596 const std::vector<MachineOperand> &Cond) const { 597 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 598 return 0; 599 } 600 601 /// copyRegToReg - Add a copy between a pair of registers 602 virtual void copyRegToReg(MachineBasicBlock &MBB, 603 MachineBasicBlock::iterator MI, 604 unsigned DestReg, unsigned SrcReg, 605 const TargetRegisterClass *DestRC, 606 const TargetRegisterClass *SrcRC) const { 607 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 608 } 609 610 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 611 MachineBasicBlock::iterator MI, 612 unsigned SrcReg, bool isKill, int FrameIndex, 613 const TargetRegisterClass *RC) const { 614 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 615 } 616 617 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 618 SmallVectorImpl<MachineOperand> &Addr, 619 const TargetRegisterClass *RC, 620 SmallVectorImpl<MachineInstr*> &NewMIs) const { 621 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 622 } 623 624 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 625 MachineBasicBlock::iterator MI, 626 unsigned DestReg, int FrameIndex, 627 const TargetRegisterClass *RC) const { 628 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 629 } 630 631 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 632 SmallVectorImpl<MachineOperand> &Addr, 633 const TargetRegisterClass *RC, 634 SmallVectorImpl<MachineInstr*> &NewMIs) const { 635 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 636 } 637 638 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 639 /// saved registers and returns true if it isn't possible / profitable to do 640 /// so by issuing a series of store instructions via 641 /// storeRegToStackSlot(). Returns false otherwise. 642 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 643 MachineBasicBlock::iterator MI, 644 const std::vector<CalleeSavedInfo> &CSI) const { 645 return false; 646 } 647 648 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 649 /// saved registers and returns true if it isn't possible / profitable to do 650 /// so by issuing a series of load instructions via loadRegToStackSlot(). 651 /// Returns false otherwise. 652 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 653 MachineBasicBlock::iterator MI, 654 const std::vector<CalleeSavedInfo> &CSI) const { 655 return false; 656 } 657 658 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 659 /// slot into the specified machine instruction for the specified operand(s). 660 /// If this is possible, a new instruction is returned with the specified 661 /// operand folded, otherwise NULL is returned. The client is responsible for 662 /// removing the old instruction and adding the new one in the instruction 663 /// stream. 664 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 665 SmallVectorImpl<unsigned> &Ops, 666 int FrameIndex) const { 667 return 0; 668 } 669 670 /// foldMemoryOperand - Same as the previous version except it allows folding 671 /// of any load and store from / to any address, not just from a specific 672 /// stack slot. 673 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 674 SmallVectorImpl<unsigned> &Ops, 675 MachineInstr* LoadMI) const { 676 return 0; 677 } 678 679 /// canFoldMemoryOperand - Returns true if the specified load / store is 680 /// folding is possible. 681 virtual 682 bool canFoldMemoryOperand(MachineInstr *MI, 683 SmallVectorImpl<unsigned> &Ops) const{ 684 return false; 685 } 686 687 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 688 /// a store or a load and a store into two or more instruction. If this is 689 /// possible, returns true as well as the new instructions by reference. 690 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 691 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 692 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 693 return false; 694 } 695 696 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 697 SmallVectorImpl<SDNode*> &NewNodes) const { 698 return false; 699 } 700 701 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 702 /// instruction after load / store are unfolded from an instruction of the 703 /// specified opcode. It returns zero if the specified unfolding is not 704 /// possible. 705 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 706 bool UnfoldLoad, bool UnfoldStore) const { 707 return 0; 708 } 709 710 /// BlockHasNoFallThrough - Return true if the specified block does not 711 /// fall-through into its successor block. This is primarily used when a 712 /// branch is unanalyzable. It is useful for things like unconditional 713 /// indirect branches (jump tables). 714 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 715 return false; 716 } 717 718 /// ReverseBranchCondition - Reverses the branch condition of the specified 719 /// condition list, returning false on success and true if it cannot be 720 /// reversed. 721 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 722 return true; 723 } 724 725 /// insertNoop - Insert a noop into the instruction stream at the specified 726 /// point. 727 virtual void insertNoop(MachineBasicBlock &MBB, 728 MachineBasicBlock::iterator MI) const { 729 assert(0 && "Target didn't implement insertNoop!"); 730 abort(); 731 } 732 733 /// isPredicated - Returns true if the instruction is already predicated. 734 /// 735 virtual bool isPredicated(const MachineInstr *MI) const { 736 return false; 737 } 738 739 /// isUnpredicatedTerminator - Returns true if the instruction is a 740 /// terminator instruction that has not been predicated. 741 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 742 743 /// PredicateInstruction - Convert the instruction into a predicated 744 /// instruction. It returns true if the operation was successful. 745 virtual 746 bool PredicateInstruction(MachineInstr *MI, 747 const std::vector<MachineOperand> &Pred) const = 0; 748 749 /// SubsumesPredicate - Returns true if the first specified predicate 750 /// subsumes the second, e.g. GE subsumes GT. 751 virtual 752 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 753 const std::vector<MachineOperand> &Pred2) const { 754 return false; 755 } 756 757 /// DefinesPredicate - If the specified instruction defines any predicate 758 /// or condition code register(s) used for predication, returns true as well 759 /// as the definition predicate(s) by reference. 760 virtual bool DefinesPredicate(MachineInstr *MI, 761 std::vector<MachineOperand> &Pred) const { 762 return false; 763 } 764 765 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 766 /// values. 767 virtual const TargetRegisterClass *getPointerRegClass() const { 768 assert(0 && "Target didn't implement getPointerRegClass!"); 769 abort(); 770 return 0; // Must return a value in order to compile with VS 2005 771 } 772}; 773 774/// TargetInstrInfoImpl - This is the default implementation of 775/// TargetInstrInfo, which just provides a couple of default implementations 776/// for various methods. This separated out because it is implemented in 777/// libcodegen, not in libtarget. 778class TargetInstrInfoImpl : public TargetInstrInfo { 779protected: 780 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 781 : TargetInstrInfo(desc, NumOpcodes) {} 782public: 783 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 784 virtual bool PredicateInstruction(MachineInstr *MI, 785 const std::vector<MachineOperand> &Pred) const; 786 787}; 788 789} // End llvm namespace 790 791#endif 792