TargetInstrInfo.h revision 8486cdd3f9850eb08fceea05deb6a0315e962574 
1//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==//
2//
3// This file describes the target machine instructions to the code generator.
4//
5//===---------------------------------------------------------------------===//
6
7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H
8#define LLVM_TARGET_MACHINEINSTRINFO_H
9
10#include "llvm/Target/TargetMachine.h"
11#include "llvm/Support/DataTypes.h"
12#include <vector>
13
14class MachineInstrDescriptor;
15class TmpInstruction;
16class MachineInstr;
17class Value;
18class Instruction;
19
20
21typedef int InstrSchedClass;
22
23// Global variable holding an array of descriptors for machine instructions.
24// The actual object needs to be created separately for each target machine.
25// This variable is initialized and reset by class MachineInstrInfo.
26//
27// FIXME: This should be a property of the target so that more than one target
28// at a time can be active...
29//
30extern const MachineInstrDescriptor *TargetInstrDescriptors;
31
32
33//---------------------------------------------------------------------------
34// struct MachineInstrDescriptor:
35//	Predefined information about each machine instruction.
36//	Designed to initialized statically.
37//
38// class MachineInstructionInfo
39//	Interface to description of machine instructions
40//
41//---------------------------------------------------------------------------
42
43
44const unsigned int	M_NOP_FLAG		= 1;
45const unsigned int	M_BRANCH_FLAG		= 1 << 1;
46const unsigned int	M_CALL_FLAG		= 1 << 2;
47const unsigned int	M_RET_FLAG		= 1 << 3;
48const unsigned int	M_ARITH_FLAG		= 1 << 4;
49const unsigned int	M_CC_FLAG		= 1 << 6;
50const unsigned int	M_LOGICAL_FLAG		= 1 << 6;
51const unsigned int	M_INT_FLAG		= 1 << 7;
52const unsigned int	M_FLOAT_FLAG		= 1 << 8;
53const unsigned int	M_CONDL_FLAG		= 1 << 9;
54const unsigned int	M_LOAD_FLAG		= 1 << 10;
55const unsigned int	M_PREFETCH_FLAG		= 1 << 11;
56const unsigned int	M_STORE_FLAG		= 1 << 12;
57const unsigned int	M_DUMMY_PHI_FLAG	= 1 << 13;
58
59
60struct MachineInstrDescriptor {
61  string	  opCodeString;  // Assembly language mnemonic for the opcode.
62  int		  numOperands;   // Number of args; -1 if variable #args
63  int		  resultPos;     // Position of the result; -1 if no result
64  unsigned int	  maxImmedConst; // Largest +ve constant in IMMMED field or 0.
65  bool		  immedIsSignExtended; // Is IMMED field sign-extended? If so,
66				 //   smallest -ve value is -(maxImmedConst+1).
67  unsigned int    numDelaySlots; // Number of delay slots after instruction
68  unsigned int    latency;	 // Latency in machine cycles
69  InstrSchedClass schedClass;	 // enum  identifying instr sched class
70  unsigned int	  iclass;	 // flags identifying machine instr class
71};
72
73
74class MachineInstrInfo : public NonCopyableV {
75public:
76  const TargetMachine& target;
77
78protected:
79  const MachineInstrDescriptor* desc;	// raw array to allow static init'n
80  unsigned int descSize;		// number of entries in the desc array
81  unsigned int numRealOpCodes;		// number of non-dummy op codes
82
83public:
84  MachineInstrInfo(const TargetMachine& tgt,
85                   const MachineInstrDescriptor *desc, unsigned descSize,
86		   unsigned numRealOpCodes);
87  virtual ~MachineInstrInfo();
88
89  unsigned getNumRealOpCodes()  const { return numRealOpCodes; }
90  unsigned getNumTotalOpCodes() const { return descSize; }
91
92  const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
93    assert(opCode >= 0 && opCode < (int)descSize);
94    return desc[opCode];
95  }
96
97  int getNumOperands(MachineOpCode opCode) const {
98    return getDescriptor(opCode).numOperands;
99  }
100
101  int getResultPos(MachineOpCode opCode) const {
102    return getDescriptor(opCode).resultPos;
103  }
104
105  unsigned getNumDelaySlots(MachineOpCode opCode) const {
106    return getDescriptor(opCode).numDelaySlots;
107  }
108
109  InstrSchedClass getSchedClass(MachineOpCode opCode) const {
110    return getDescriptor(opCode).schedClass;
111  }
112
113  //
114  // Query instruction class flags according to the machine-independent
115  // flags listed above.
116  //
117  unsigned int getIClass(MachineOpCode opCode) const {
118    return getDescriptor(opCode).iclass;
119  }
120  bool isNop(MachineOpCode opCode) const {
121    return getDescriptor(opCode).iclass & M_NOP_FLAG;
122  }
123  bool isBranch(MachineOpCode opCode) const {
124    return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
125  }
126  bool isCall(MachineOpCode opCode) const {
127    return getDescriptor(opCode).iclass & M_CALL_FLAG;
128  }
129  bool isReturn(MachineOpCode opCode) const {
130    return getDescriptor(opCode).iclass & M_RET_FLAG;
131  }
132  bool isControlFlow(MachineOpCode opCode) const {
133    return getDescriptor(opCode).iclass & M_BRANCH_FLAG
134        || getDescriptor(opCode).iclass & M_CALL_FLAG
135        || getDescriptor(opCode).iclass & M_RET_FLAG;
136  }
137  bool isArith(MachineOpCode opCode) const {
138    return getDescriptor(opCode).iclass & M_RET_FLAG;
139  }
140  bool isCCInstr(MachineOpCode opCode) const {
141    return getDescriptor(opCode).iclass & M_CC_FLAG;
142  }
143  bool isLogical(MachineOpCode opCode) const {
144    return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
145  }
146  bool isIntInstr(MachineOpCode opCode) const {
147    return getDescriptor(opCode).iclass & M_INT_FLAG;
148  }
149  bool isFloatInstr(MachineOpCode opCode) const {
150    return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
151  }
152  bool isConditional(MachineOpCode opCode) const {
153    return getDescriptor(opCode).iclass & M_CONDL_FLAG;
154  }
155  bool isLoad(MachineOpCode opCode) const {
156    return getDescriptor(opCode).iclass & M_LOAD_FLAG;
157  }
158  bool isPrefetch(MachineOpCode opCode) const {
159    return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
160  }
161  bool isLoadOrPrefetch(MachineOpCode opCode) const {
162    return getDescriptor(opCode).iclass & M_LOAD_FLAG
163        || getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
164  }
165  bool isStore(MachineOpCode opCode) const {
166    return getDescriptor(opCode).iclass & M_STORE_FLAG;
167  }
168  bool isMemoryAccess(MachineOpCode opCode) const {
169    return getDescriptor(opCode).iclass & M_LOAD_FLAG
170        || getDescriptor(opCode).iclass & M_PREFETCH_FLAG
171        || getDescriptor(opCode).iclass & M_STORE_FLAG;
172  }
173  bool isDummyPhiInstr(const MachineOpCode opCode) const {
174    return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
175  }
176
177
178  // delete this later *******
179  bool isPhi(const MachineOpCode opCode) const
180  { return isDummyPhiInstr(opCode); }
181
182
183  // Check if an instruction can be issued before its operands are ready,
184  // or if a subsequent instruction that uses its result can be issued
185  // before the results are ready.
186  // Default to true since most instructions on many architectures allow this.
187  //
188  virtual bool hasOperandInterlock(MachineOpCode opCode) const {
189    return true;
190  }
191
192  virtual bool hasResultInterlock(MachineOpCode opCode) const {
193    return true;
194  }
195
196  //
197  // Latencies for individual instructions and instruction pairs
198  //
199  virtual int minLatency(MachineOpCode opCode) const {
200    return getDescriptor(opCode).latency;
201  }
202
203  virtual int maxLatency(MachineOpCode opCode) const {
204    return getDescriptor(opCode).latency;
205  }
206
207  // Check if the specified constant fits in the immediate field
208  // of this machine instruction
209  //
210  virtual bool constantFitsInImmedField(MachineOpCode opCode,
211					int64_t intValue) const;
212
213  // Return the largest +ve constant that can be held in the IMMMED field
214  // of this machine instruction.
215  // isSignExtended is set to true if the value is sign-extended before use
216  // (this is true for all immediate fields in SPARC instructions).
217  // Return 0 if the instruction has no IMMED field.
218  //
219  virtual uint64_t maxImmedConstant(MachineOpCode opCode,
220				    bool &isSignExtended) const {
221    isSignExtended = getDescriptor(opCode).immedIsSignExtended;
222    return getDescriptor(opCode).maxImmedConst;
223  }
224
225  //-------------------------------------------------------------------------
226  // Code generation support for creating individual machine instructions
227  //-------------------------------------------------------------------------
228
229  // Create an instruction sequence to put the constant `val' into
230  // the virtual register `dest'.  `val' may be a ConstPoolVal or a
231  // GlobalValue, viz., the constant address of a global variable or function.
232  // The generated instructions are returned in `minstrVec'.
233  // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
234  //
235  virtual void  CreateCodeToLoadConst(Value* val,
236                                      Instruction* dest,
237                                      vector<MachineInstr*>& minstrVec,
238                                      vector<TmpInstruction*>& temps) const =0;
239
240  // Create an instruction sequence to copy an integer value `val'
241  // to a floating point value `dest' by copying to memory and back.
242  // val must be an integral type.  dest must be a Float or Double.
243  // The generated instructions are returned in `minstrVec'.
244  // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
245  //
246  virtual void  CreateCodeToCopyIntToFloat(Method* method,
247                                           Value* val,
248                                           Instruction* dest,
249                                           vector<MachineInstr*>& minstrVec,
250                                           vector<TmpInstruction*>& tempVec,
251                                           TargetMachine& target) const = 0;
252
253  // Similarly, create an instruction sequence to copy an FP value
254  // `val' to an integer value `dest' by copying to memory and back.
255  // See the previous function for information about return values.
256  //
257  virtual void  CreateCodeToCopyFloatToInt(Method* method,
258                                           Value* val,
259                                           Instruction* dest,
260                                           vector<MachineInstr*>& minstrVec,
261                                           vector<TmpInstruction*>& tempVec,
262                                           TargetMachine& target) const = 0;
263
264
265  // create copy instruction(s)
266  virtual void
267  CreateCopyInstructionsByType(const TargetMachine& target,
268			       Value* src,
269			       Instruction* dest,
270			       vector<MachineInstr*>& minstrVec) const = 0;
271
272
273
274};
275
276#endif
277