TargetInstrInfo.h revision 8ca5c67c6e95fdcf5ddb2f06586873c843dd0cde
1bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 21d580d0f6ee4f21eb309ba7b509d2c6d671c4044Bjorn Bringert// 3bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// The LLVM Compiler Infrastructure 4bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// 5bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// This file is distributed under the University of Illinois Open Source 6bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// License. See LICENSE.TXT for details. 7bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// 8bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor//===----------------------------------------------------------------------===// 9bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// 10bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// This file describes the target machine instructions to the code generator. 11bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// 12bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor//===----------------------------------------------------------------------===// 13bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor 14bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor#define LLVM_TARGET_TARGETINSTRINFO_H 16bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor 17bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor#include "llvm/CodeGen/MachineBasicBlock.h" 18bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor#include "llvm/CodeGen/MachineFunction.h" 191d580d0f6ee4f21eb309ba7b509d2c6d671c4044Bjorn Bringert#include "llvm/Support/DataTypes.h" 201d580d0f6ee4f21eb309ba7b509d2c6d671c4044Bjorn Bringert#include <vector> 21bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor#include <cassert> 22bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor 23bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnornamespace llvm { 24bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor 25bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnorclass MachineInstr; 26bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnorclass TargetMachine; 27bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnorclass TargetRegisterClass; 28bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnorclass LiveVariables; 29bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnorclass CalleeSavedInfo; 301d580d0f6ee4f21eb309ba7b509d2c6d671c4044Bjorn Bringertclass SDNode; 31bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnorclass SelectionDAG; 321d580d0f6ee4f21eb309ba7b509d2c6d671c4044Bjorn Bringert 33bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnortemplate<class T> class SmallVectorImpl; 34bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor 35bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor//===----------------------------------------------------------------------===// 36bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// Data types used to define information about a single machine instruction 37bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor//===----------------------------------------------------------------------===// 38bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor 39bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnortypedef short MachineOpCode; 40bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnortypedef unsigned InstrSchedClass; 41bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor 42bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor//===----------------------------------------------------------------------===// 43bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// struct TargetInstrDescriptor: 44bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// Predefined information about each machine instruction. 45bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// Designed to initialized statically. 46bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor// 47bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnor 48bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnorconst unsigned M_BRANCH_FLAG = 1 << 0; 49bfe2dd089341dcb4c1fb65a5b6b077ad0ebbf6dcDan Egnorconst unsigned M_CALL_FLAG = 1 << 1; 50const unsigned M_RET_FLAG = 1 << 2; 51const unsigned M_BARRIER_FLAG = 1 << 3; 52const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 53 54/// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads 55/// from memory. This should only be set on instructions that load a value from 56/// memory and return it in their only virtual register definition. 57const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5; 58 59/// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly 60/// modify memory. Instructions with this flag set are not necessarily simple 61/// store instructions, they may store a modified value based on their operands, 62/// or may not actually modify anything, for example. 63const unsigned M_MAY_STORE_FLAG = 1 << 6; 64 65const unsigned M_INDIRECT_FLAG = 1 << 7; 66const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8; 67 68// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 69// changed into a 3-address instruction if the first two operands cannot be 70// assigned to the same register. The target must implement the 71// TargetInstrInfo::convertToThreeAddress method for this instruction. 72const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9; 73 74// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 75// Z), which produces the same result if Y and Z are exchanged. 76const unsigned M_COMMUTABLE = 1 << 10; 77 78// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 79// block? Typically this is things like return and branch instructions. 80// Various passes use this to insert code into the bottom of a basic block, but 81// before control flow occurs. 82const unsigned M_TERMINATOR_FLAG = 1 << 11; 83 84// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 85// insertion support when the DAG scheduler is inserting it into a machine basic 86// block. 87const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12; 88 89// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 90// operands in addition to the minimum number operands specified. 91const unsigned M_VARIABLE_OPS = 1 << 13; 92 93// M_PREDICABLE - Set if this instruction has a predicate operand that 94// controls execution. It may be set to 'always'. 95const unsigned M_PREDICABLE = 1 << 14; 96 97// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 98// at any time, e.g. constant generation, load from constant pool. 99const unsigned M_REMATERIALIZIBLE = 1 << 15; 100 101// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated. 102// (e.g. instructions with unique labels attached). 103const unsigned M_NOT_DUPLICABLE = 1 << 16; 104 105// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g. 106// ARM instructions which can set condition code if 's' bit is set. 107const unsigned M_HAS_OPTIONAL_DEF = 1 << 17; 108 109// M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that 110// are not captured by any operands of the instruction or other flags, and when 111// *all* instances of the instruction of that opcode have no side effects. 112// 113// Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set 114// both! If neither flag is set, then the instruction *always* has side effects. 115const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18; 116 117// M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have 118// side effects. The virtual method "isReallySideEffectFree" is called to 119// determine this. Load instructions are an example of where this is useful. In 120// general, loads always have side effects. However, loads from constant pools 121// don't. We let the specific back end make this determination. 122// 123// Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set 124// both! If neither flag is set, then the instruction *always* has side effects. 125const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19; 126 127 128//===----------------------------------------------------------------------===// 129// Machine operand flags 130//===----------------------------------------------------------------------===// 131 132namespace TOI { 133 // Operand constraints: only "tied_to" for now. 134 enum OperandConstraint { 135 TIED_TO = 0 // Must be allocated the same register as. 136 }; 137 138 /// OperandFlags - These are flags set on operands, but should be considered 139 /// private, all access should go through the TargetOperandInfo accessors. 140 /// See the accessors for a description of what these are. 141 enum OperandFlags { 142 LookupPtrRegClass = 1 << 0, 143 Predicate = 1 << 1, 144 OptionalDef = 1 << 2 145 }; 146} 147 148/// TargetOperandInfo - This holds information about one operand of a machine 149/// instruction, indicating the register class for register operands, etc. 150/// 151class TargetOperandInfo { 152public: 153 /// RegClass - This specifies the register class enumeration of the operand 154 /// if the operand is a register. If not, this contains 0. 155 unsigned short RegClass; 156 unsigned short Flags; 157 /// Lower 16 bits are used to specify which constraints are set. The higher 16 158 /// bits are used to specify the value of constraints (4 bits each). 159 unsigned int Constraints; 160 /// Currently no other information. 161 162 /// isLookupPtrRegClass - Set if this operand is a pointer value and it 163 /// requires a callback to look up its register class. 164 bool isLookupPtrRegClass() const { return Flags & TOI::LookupPtrRegClass; } 165 166 /// isPredicate - Set if this is one of the operands that made up of 167 /// the predicate operand that controls an M_PREDICATED instruction. 168 bool isPredicate() const { return Flags & TOI::Predicate; } 169 170 /// isOptionalDef - Set if this operand is a optional def. 171 /// 172 bool isOptionalDef() const { return Flags & TOI::OptionalDef; } 173}; 174 175 176class TargetInstrDescriptor { 177public: 178 MachineOpCode Opcode; // The opcode. 179 unsigned short numOperands; // Num of args (may be more if variable_ops). 180 unsigned short numDefs; // Num of args that are definitions. 181 const char * Name; // Assembly language mnemonic for the opcode. 182 InstrSchedClass schedClass; // enum identifying instr sched class 183 unsigned Flags; // flags identifying machine instr class 184 unsigned TSFlags; // Target Specific Flag values 185 const unsigned *ImplicitUses; // Registers implicitly read by this instr 186 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 187 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 188 189 /// getOperandConstraint - Returns the value of the specific constraint if 190 /// it is set. Returns -1 if it is not set. 191 int getOperandConstraint(unsigned OpNum, 192 TOI::OperandConstraint Constraint) const { 193 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 194 "Invalid operand # of TargetInstrInfo"); 195 if (OpNum < numOperands && 196 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 197 unsigned Pos = 16 + Constraint * 4; 198 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 199 } 200 return -1; 201 } 202 203 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 204 /// dest operand. Returns -1 if there isn't one. 205 int findTiedToSrcOperand(unsigned OpNum) const; 206 207 bool isCall() const { 208 return Flags & M_CALL_FLAG; 209 } 210 211 bool isBranch() const { 212 return Flags & M_BRANCH_FLAG; 213 } 214 215 bool isTerminator() const { 216 return Flags & M_TERMINATOR_FLAG; 217 } 218 219 bool isIndirectBranch() const { 220 return Flags & M_INDIRECT_FLAG; 221 } 222 223 bool isPredicable() const { 224 return Flags & M_PREDICABLE; 225 } 226 227 bool isNotDuplicable() const { 228 return Flags & M_NOT_DUPLICABLE; 229 } 230 231 232 233 /// isSimpleLoad - Return true for instructions that are simple loads from 234 /// memory. This should only be set on instructions that load a value from 235 /// memory and return it in their only virtual register definition. 236 /// Instructions that return a value loaded from memory and then modified in 237 /// some way should not return true for this. 238 bool isSimpleLoad() const { 239 return Flags & M_SIMPLE_LOAD_FLAG; 240 } 241 242 /// mayStore - Return true if this instruction could possibly modify memory. 243 /// Instructions with this flag set are not necessarily simple store 244 /// instructions, they may store a modified value based on their operands, or 245 /// may not actually modify anything, for example. 246 bool mayStore() const { 247 return Flags & M_MAY_STORE_FLAG; 248 } 249 250 /// isBarrier - Returns true if the specified instruction stops control flow 251 /// from executing the instruction immediately following it. Examples include 252 /// unconditional branches and return instructions. 253 bool isBarrier() const { 254 return Flags & M_BARRIER_FLAG; 255 } 256 257 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 258 /// which must be filled by the code generator. 259 bool hasDelaySlot() const { 260 return Flags & M_DELAY_SLOT_FLAG; 261 } 262}; 263 264 265//--------------------------------------------------------------------------- 266/// 267/// TargetInstrInfo - Interface to description of machine instructions 268/// 269class TargetInstrInfo { 270 const TargetInstrDescriptor* desc; // raw array to allow static init'n 271 unsigned NumOpcodes; // number of entries in the desc array 272 unsigned numRealOpCodes; // number of non-dummy op codes 273 274 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 275 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 276public: 277 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 278 virtual ~TargetInstrInfo(); 279 280 // Invariant opcodes: All instruction sets have these as their low opcodes. 281 enum { 282 PHI = 0, 283 INLINEASM = 1, 284 LABEL = 2, 285 EXTRACT_SUBREG = 3, 286 INSERT_SUBREG = 4 287 }; 288 289 unsigned getNumOpcodes() const { return NumOpcodes; } 290 291 /// get - Return the machine instruction descriptor that corresponds to the 292 /// specified instruction opcode. 293 /// 294 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 295 assert((unsigned)Opcode < NumOpcodes); 296 return desc[Opcode]; 297 } 298 299 const char *getName(MachineOpCode Opcode) const { 300 return get(Opcode).Name; 301 } 302 303 int getNumOperands(MachineOpCode Opcode) const { 304 return get(Opcode).numOperands; 305 } 306 307 int getNumDefs(MachineOpCode Opcode) const { 308 return get(Opcode).numDefs; 309 } 310 311 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 312 return get(Opcode).schedClass; 313 } 314 315 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 316 return get(Opcode).ImplicitUses; 317 } 318 319 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 320 return get(Opcode).ImplicitDefs; 321 } 322 323 324 // 325 // Query instruction class flags according to the machine-independent 326 // flags listed above. 327 // 328 bool isReturn(MachineOpCode Opcode) const { 329 return get(Opcode).Flags & M_RET_FLAG; 330 } 331 332 bool isCommutableInstr(MachineOpCode Opcode) const { 333 return get(Opcode).Flags & M_COMMUTABLE; 334 } 335 336 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 337 /// custom insertion support when the DAG scheduler is inserting it into a 338 /// machine basic block. 339 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const { 340 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 341 } 342 343 bool hasVariableOperands(MachineOpCode Opcode) const { 344 return get(Opcode).Flags & M_VARIABLE_OPS; 345 } 346 347 bool hasOptionalDef(MachineOpCode Opcode) const { 348 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF; 349 } 350 351 /// isTriviallyReMaterializable - Return true if the instruction is trivially 352 /// rematerializable, meaning it has no side effects and requires no operands 353 /// that aren't always available. 354 bool isTriviallyReMaterializable(MachineInstr *MI) const { 355 return (MI->getDesc()->Flags & M_REMATERIALIZIBLE) && 356 isReallyTriviallyReMaterializable(MI); 357 } 358 359 /// hasUnmodelledSideEffects - Returns true if the instruction has side 360 /// effects that are not captured by any operands of the instruction or other 361 /// flags. 362 bool hasUnmodelledSideEffects(MachineInstr *MI) const { 363 const TargetInstrDescriptor *TID = MI->getDesc(); 364 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false; 365 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true; 366 return !isReallySideEffectFree(MI); // May have side effects 367 } 368protected: 369 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 370 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 371 /// instruction itself is actually trivially rematerializable, considering 372 /// its operands. This is used for targets that have instructions that are 373 /// only trivially rematerializable for specific uses. This predicate must 374 /// return false if the instruction has any side effects other than 375 /// producing a value, or if it requres any address registers that are not 376 /// always available. 377 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 378 return true; 379 } 380 381 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this 382 /// method is called to determine if the specific instance of this 383 /// instruction has side effects. This is useful in cases of instructions, 384 /// like loads, which generally always have side effects. A load from a 385 /// constant pool doesn't have side effects, though. So we need to 386 /// differentiate it from the general case. 387 virtual bool isReallySideEffectFree(MachineInstr *MI) const { 388 return false; 389 } 390public: 391 /// getOperandConstraint - Returns the value of the specific constraint if 392 /// it is set. Returns -1 if it is not set. 393 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 394 TOI::OperandConstraint Constraint) const { 395 return get(Opcode).getOperandConstraint(OpNum, Constraint); 396 } 397 398 /// Return true if the instruction is a register to register move 399 /// and leave the source and dest operands in the passed parameters. 400 virtual bool isMoveInstr(const MachineInstr& MI, 401 unsigned& sourceReg, 402 unsigned& destReg) const { 403 return false; 404 } 405 406 /// isLoadFromStackSlot - If the specified machine instruction is a direct 407 /// load from a stack slot, return the virtual or physical register number of 408 /// the destination along with the FrameIndex of the loaded stack slot. If 409 /// not, return 0. This predicate must return 0 if the instruction has 410 /// any side effects other than loading from the stack slot. 411 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 412 return 0; 413 } 414 415 /// isStoreToStackSlot - If the specified machine instruction is a direct 416 /// store to a stack slot, return the virtual or physical register number of 417 /// the source reg along with the FrameIndex of the loaded stack slot. If 418 /// not, return 0. This predicate must return 0 if the instruction has 419 /// any side effects other than storing to the stack slot. 420 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 421 return 0; 422 } 423 424 /// convertToThreeAddress - This method must be implemented by targets that 425 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 426 /// may be able to convert a two-address instruction into one or more true 427 /// three-address instructions on demand. This allows the X86 target (for 428 /// example) to convert ADD and SHL instructions into LEA instructions if they 429 /// would require register copies due to two-addressness. 430 /// 431 /// This method returns a null pointer if the transformation cannot be 432 /// performed, otherwise it returns the last new instruction. 433 /// 434 virtual MachineInstr * 435 convertToThreeAddress(MachineFunction::iterator &MFI, 436 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 437 return 0; 438 } 439 440 /// commuteInstruction - If a target has any instructions that are commutable, 441 /// but require converting to a different instruction or making non-trivial 442 /// changes to commute them, this method can overloaded to do this. The 443 /// default implementation of this method simply swaps the first two operands 444 /// of MI and returns it. 445 /// 446 /// If a target wants to make more aggressive changes, they can construct and 447 /// return a new machine instruction. If an instruction cannot commute, it 448 /// can also return null. 449 /// 450 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0; 451 452 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 453 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 454 /// implemented for a target). Upon success, this returns false and returns 455 /// with the following information in various cases: 456 /// 457 /// 1. If this block ends with no branches (it just falls through to its succ) 458 /// just return false, leaving TBB/FBB null. 459 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 460 /// the destination block. 461 /// 3. If this block ends with an conditional branch and it falls through to 462 /// an successor block, it sets TBB to be the branch destination block and a 463 /// list of operands that evaluate the condition. These 464 /// operands can be passed to other TargetInstrInfo methods to create new 465 /// branches. 466 /// 4. If this block ends with an conditional branch and an unconditional 467 /// block, it returns the 'true' destination in TBB, the 'false' destination 468 /// in FBB, and a list of operands that evaluate the condition. These 469 /// operands can be passed to other TargetInstrInfo methods to create new 470 /// branches. 471 /// 472 /// Note that RemoveBranch and InsertBranch must be implemented to support 473 /// cases where this method returns success. 474 /// 475 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 476 MachineBasicBlock *&FBB, 477 std::vector<MachineOperand> &Cond) const { 478 return true; 479 } 480 481 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 482 /// this is only invoked in cases where AnalyzeBranch returns success. It 483 /// returns the number of instructions that were removed. 484 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 485 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 486 return 0; 487 } 488 489 /// InsertBranch - Insert a branch into the end of the specified 490 /// MachineBasicBlock. This operands to this method are the same as those 491 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 492 /// returns success and when an unconditional branch (TBB is non-null, FBB is 493 /// null, Cond is empty) needs to be inserted. It returns the number of 494 /// instructions inserted. 495 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 496 MachineBasicBlock *FBB, 497 const std::vector<MachineOperand> &Cond) const { 498 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 499 return 0; 500 } 501 502 /// copyRegToReg - Add a copy between a pair of registers 503 virtual void copyRegToReg(MachineBasicBlock &MBB, 504 MachineBasicBlock::iterator MI, 505 unsigned DestReg, unsigned SrcReg, 506 const TargetRegisterClass *DestRC, 507 const TargetRegisterClass *SrcRC) const { 508 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 509 } 510 511 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 512 MachineBasicBlock::iterator MI, 513 unsigned SrcReg, bool isKill, int FrameIndex, 514 const TargetRegisterClass *RC) const { 515 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 516 } 517 518 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 519 SmallVectorImpl<MachineOperand> &Addr, 520 const TargetRegisterClass *RC, 521 SmallVectorImpl<MachineInstr*> &NewMIs) const { 522 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 523 } 524 525 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 526 MachineBasicBlock::iterator MI, 527 unsigned DestReg, int FrameIndex, 528 const TargetRegisterClass *RC) const { 529 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 530 } 531 532 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 533 SmallVectorImpl<MachineOperand> &Addr, 534 const TargetRegisterClass *RC, 535 SmallVectorImpl<MachineInstr*> &NewMIs) const { 536 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 537 } 538 539 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 540 /// saved registers and returns true if it isn't possible / profitable to do 541 /// so by issuing a series of store instructions via 542 /// storeRegToStackSlot(). Returns false otherwise. 543 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 544 MachineBasicBlock::iterator MI, 545 const std::vector<CalleeSavedInfo> &CSI) const { 546 return false; 547 } 548 549 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 550 /// saved registers and returns true if it isn't possible / profitable to do 551 /// so by issuing a series of load instructions via loadRegToStackSlot(). 552 /// Returns false otherwise. 553 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 554 MachineBasicBlock::iterator MI, 555 const std::vector<CalleeSavedInfo> &CSI) const { 556 return false; 557 } 558 559 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 560 /// slot into the specified machine instruction for the specified operand(s). 561 /// If this is possible, a new instruction is returned with the specified 562 /// operand folded, otherwise NULL is returned. The client is responsible for 563 /// removing the old instruction and adding the new one in the instruction 564 /// stream. 565 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 566 SmallVectorImpl<unsigned> &Ops, 567 int FrameIndex) const { 568 return 0; 569 } 570 571 /// foldMemoryOperand - Same as the previous version except it allows folding 572 /// of any load and store from / to any address, not just from a specific 573 /// stack slot. 574 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, 575 SmallVectorImpl<unsigned> &Ops, 576 MachineInstr* LoadMI) const { 577 return 0; 578 } 579 580 /// canFoldMemoryOperand - Returns true if the specified load / store is 581 /// folding is possible. 582 virtual 583 bool canFoldMemoryOperand(MachineInstr *MI, 584 SmallVectorImpl<unsigned> &Ops) const{ 585 return false; 586 } 587 588 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 589 /// a store or a load and a store into two or more instruction. If this is 590 /// possible, returns true as well as the new instructions by reference. 591 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 592 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 593 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 594 return false; 595 } 596 597 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 598 SmallVectorImpl<SDNode*> &NewNodes) const { 599 return false; 600 } 601 602 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 603 /// instruction after load / store are unfolded from an instruction of the 604 /// specified opcode. It returns zero if the specified unfolding is not 605 /// possible. 606 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 607 bool UnfoldLoad, bool UnfoldStore) const { 608 return 0; 609 } 610 611 /// BlockHasNoFallThrough - Return true if the specified block does not 612 /// fall-through into its successor block. This is primarily used when a 613 /// branch is unanalyzable. It is useful for things like unconditional 614 /// indirect branches (jump tables). 615 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 616 return false; 617 } 618 619 /// ReverseBranchCondition - Reverses the branch condition of the specified 620 /// condition list, returning false on success and true if it cannot be 621 /// reversed. 622 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 623 return true; 624 } 625 626 /// insertNoop - Insert a noop into the instruction stream at the specified 627 /// point. 628 virtual void insertNoop(MachineBasicBlock &MBB, 629 MachineBasicBlock::iterator MI) const { 630 assert(0 && "Target didn't implement insertNoop!"); 631 abort(); 632 } 633 634 /// isPredicated - Returns true if the instruction is already predicated. 635 /// 636 virtual bool isPredicated(const MachineInstr *MI) const { 637 return false; 638 } 639 640 /// isUnpredicatedTerminator - Returns true if the instruction is a 641 /// terminator instruction that has not been predicated. 642 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 643 644 /// PredicateInstruction - Convert the instruction into a predicated 645 /// instruction. It returns true if the operation was successful. 646 virtual 647 bool PredicateInstruction(MachineInstr *MI, 648 const std::vector<MachineOperand> &Pred) const = 0; 649 650 /// SubsumesPredicate - Returns true if the first specified predicate 651 /// subsumes the second, e.g. GE subsumes GT. 652 virtual 653 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 654 const std::vector<MachineOperand> &Pred2) const { 655 return false; 656 } 657 658 /// DefinesPredicate - If the specified instruction defines any predicate 659 /// or condition code register(s) used for predication, returns true as well 660 /// as the definition predicate(s) by reference. 661 virtual bool DefinesPredicate(MachineInstr *MI, 662 std::vector<MachineOperand> &Pred) const { 663 return false; 664 } 665 666 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 667 /// values. 668 virtual const TargetRegisterClass *getPointerRegClass() const { 669 assert(0 && "Target didn't implement getPointerRegClass!"); 670 abort(); 671 return 0; // Must return a value in order to compile with VS 2005 672 } 673}; 674 675/// TargetInstrInfoImpl - This is the default implementation of 676/// TargetInstrInfo, which just provides a couple of default implementations 677/// for various methods. This separated out because it is implemented in 678/// libcodegen, not in libtarget. 679class TargetInstrInfoImpl : public TargetInstrInfo { 680protected: 681 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes) 682 : TargetInstrInfo(desc, NumOpcodes) {} 683public: 684 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 685 virtual bool PredicateInstruction(MachineInstr *MI, 686 const std::vector<MachineOperand> &Pred) const; 687 688}; 689 690} // End llvm namespace 691 692#endif 693