TargetInstrInfo.h revision 8ed9c1a6d92083102867d0886dc0b6ed0fb05461
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/Support/DataTypes.h" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class MachineInstr; 26class TargetMachine; 27class TargetRegisterClass; 28class LiveVariables; 29class CalleeSavedInfo; 30 31template<class T> class SmallVectorImpl; 32 33//--------------------------------------------------------------------------- 34// Data types used to define information about a single machine instruction 35//--------------------------------------------------------------------------- 36 37typedef short MachineOpCode; 38typedef unsigned InstrSchedClass; 39 40//--------------------------------------------------------------------------- 41// struct TargetInstrDescriptor: 42// Predefined information about each machine instruction. 43// Designed to initialized statically. 44// 45 46const unsigned M_BRANCH_FLAG = 1 << 0; 47const unsigned M_CALL_FLAG = 1 << 1; 48const unsigned M_RET_FLAG = 1 << 2; 49const unsigned M_BARRIER_FLAG = 1 << 3; 50const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 51const unsigned M_LOAD_FLAG = 1 << 5; 52 53/// M_STORE_FLAG - This flag is set to any instruction that could possibly 54/// modify memory. Instructions with this flag set are not necessarily simple 55/// store instructions, they may store a modified value based on their operands, 56/// or may not actually modify anything, for example. 57const unsigned M_STORE_FLAG = 1 << 6; 58 59const unsigned M_INDIRECT_FLAG = 1 << 7; 60const unsigned M_IMPLICIT_DEF_FLAG = 1 << 8; 61 62// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 63// changed into a 3-address instruction if the first two operands cannot be 64// assigned to the same register. The target must implement the 65// TargetInstrInfo::convertToThreeAddress method for this instruction. 66const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9; 67 68// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 69// Z), which produces the same result if Y and Z are exchanged. 70const unsigned M_COMMUTABLE = 1 << 10; 71 72// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 73// block? Typically this is things like return and branch instructions. 74// Various passes use this to insert code into the bottom of a basic block, but 75// before control flow occurs. 76const unsigned M_TERMINATOR_FLAG = 1 << 11; 77 78// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 79// insertion support when the DAG scheduler is inserting it into a machine basic 80// block. 81const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12; 82 83// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 84// operands in addition to the minimum number operands specified. 85const unsigned M_VARIABLE_OPS = 1 << 13; 86 87// M_PREDICABLE - Set if this instruction has a predicate operand that 88// controls execution. It may be set to 'always'. 89const unsigned M_PREDICABLE = 1 << 14; 90 91// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 92// at any time, e.g. constant generation, load from constant pool. 93const unsigned M_REMATERIALIZIBLE = 1 << 15; 94 95// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated. 96// (e.g. instructions with unique labels attached). 97const unsigned M_NOT_DUPLICABLE = 1 << 16; 98 99// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g. 100// ARM instructions which can set condition code if 's' bit is set. 101const unsigned M_HAS_OPTIONAL_DEF = 1 << 17; 102 103// M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that 104// are not captured by any operands of the instruction or other flags, and when 105// *all* instances of the instruction of that opcode have no side effects. 106// 107// Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set 108// both! If neither flag is set, then the instruction *always* has side effects. 109const unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18; 110 111// M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have 112// side effects. The virtual method "isReallySideEffectFree" is called to 113// determine this. Load instructions are an example of where this is useful. In 114// general, loads always have side effects. However, loads from constant pools 115// don't. We let the specific back end make this determination. 116// 117// Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set 118// both! If neither flag is set, then the instruction *always* has side effects. 119const unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19; 120 121// Machine operand flags 122// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 123// requires a callback to look up its register class. 124const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 125 126/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the 127/// predicate operand that controls an M_PREDICATED instruction. 128const unsigned M_PREDICATE_OPERAND = 1 << 1; 129 130/// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def. 131/// 132const unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2; 133 134namespace TOI { 135 // Operand constraints: only "tied_to" for now. 136 enum OperandConstraint { 137 TIED_TO = 0 // Must be allocated the same register as. 138 }; 139} 140 141/// TargetOperandInfo - This holds information about one operand of a machine 142/// instruction, indicating the register class for register operands, etc. 143/// 144class TargetOperandInfo { 145public: 146 /// RegClass - This specifies the register class enumeration of the operand 147 /// if the operand is a register. If not, this contains 0. 148 unsigned short RegClass; 149 unsigned short Flags; 150 /// Lower 16 bits are used to specify which constraints are set. The higher 16 151 /// bits are used to specify the value of constraints (4 bits each). 152 unsigned int Constraints; 153 /// Currently no other information. 154}; 155 156 157class TargetInstrDescriptor { 158public: 159 MachineOpCode Opcode; // The opcode. 160 unsigned short numOperands; // Num of args (may be more if variable_ops). 161 unsigned short numDefs; // Num of args that are definitions. 162 const char * Name; // Assembly language mnemonic for the opcode. 163 InstrSchedClass schedClass; // enum identifying instr sched class 164 unsigned Flags; // flags identifying machine instr class 165 unsigned TSFlags; // Target Specific Flag values 166 const unsigned *ImplicitUses; // Registers implicitly read by this instr 167 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 168 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 169 170 /// getOperandConstraint - Returns the value of the specific constraint if 171 /// it is set. Returns -1 if it is not set. 172 int getOperandConstraint(unsigned OpNum, 173 TOI::OperandConstraint Constraint) const { 174 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 175 "Invalid operand # of TargetInstrInfo"); 176 if (OpNum < numOperands && 177 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 178 unsigned Pos = 16 + Constraint * 4; 179 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 180 } 181 return -1; 182 } 183 184 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 185 /// dest operand. Returns -1 if there isn't one. 186 int findTiedToSrcOperand(unsigned OpNum) const; 187}; 188 189 190//--------------------------------------------------------------------------- 191/// 192/// TargetInstrInfo - Interface to description of machine instructions 193/// 194class TargetInstrInfo { 195 const TargetInstrDescriptor* desc; // raw array to allow static init'n 196 unsigned NumOpcodes; // number of entries in the desc array 197 unsigned numRealOpCodes; // number of non-dummy op codes 198 199 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 200 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 201public: 202 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 203 virtual ~TargetInstrInfo(); 204 205 // Invariant opcodes: All instruction sets have these as their low opcodes. 206 enum { 207 PHI = 0, 208 INLINEASM = 1, 209 LABEL = 2, 210 EXTRACT_SUBREG = 3, 211 INSERT_SUBREG = 4 212 }; 213 214 unsigned getNumOpcodes() const { return NumOpcodes; } 215 216 /// get - Return the machine instruction descriptor that corresponds to the 217 /// specified instruction opcode. 218 /// 219 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 220 assert((unsigned)Opcode < NumOpcodes); 221 return desc[Opcode]; 222 } 223 224 const char *getName(MachineOpCode Opcode) const { 225 return get(Opcode).Name; 226 } 227 228 int getNumOperands(MachineOpCode Opcode) const { 229 return get(Opcode).numOperands; 230 } 231 232 int getNumDefs(MachineOpCode Opcode) const { 233 return get(Opcode).numDefs; 234 } 235 236 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 237 return get(Opcode).schedClass; 238 } 239 240 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 241 return get(Opcode).ImplicitUses; 242 } 243 244 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 245 return get(Opcode).ImplicitDefs; 246 } 247 248 249 // 250 // Query instruction class flags according to the machine-independent 251 // flags listed above. 252 // 253 bool isReturn(MachineOpCode Opcode) const { 254 return get(Opcode).Flags & M_RET_FLAG; 255 } 256 257 bool isCommutableInstr(MachineOpCode Opcode) const { 258 return get(Opcode).Flags & M_COMMUTABLE; 259 } 260 bool isTerminatorInstr(MachineOpCode Opcode) const { 261 return get(Opcode).Flags & M_TERMINATOR_FLAG; 262 } 263 264 bool isBranch(MachineOpCode Opcode) const { 265 return get(Opcode).Flags & M_BRANCH_FLAG; 266 } 267 268 bool isIndirectBranch(MachineOpCode Opcode) const { 269 return get(Opcode).Flags & M_INDIRECT_FLAG; 270 } 271 272 /// isBarrier - Returns true if the specified instruction stops control flow 273 /// from executing the instruction immediately following it. Examples include 274 /// unconditional branches and return instructions. 275 bool isBarrier(MachineOpCode Opcode) const { 276 return get(Opcode).Flags & M_BARRIER_FLAG; 277 } 278 279 bool isCall(MachineOpCode Opcode) const { 280 return get(Opcode).Flags & M_CALL_FLAG; 281 } 282 bool isLoad(MachineOpCode Opcode) const { 283 return get(Opcode).Flags & M_LOAD_FLAG; 284 } 285 286 /// isStore - Return true if this instruction could possibly modify memory. 287 /// Instructions with this flag set are not necessarily simple store 288 /// instructions, they may store a modified value based on their operands, or 289 /// may not actually modify anything, for example. 290 bool isStore(MachineOpCode Opcode) const { 291 return get(Opcode).Flags & M_STORE_FLAG; 292 } 293 294 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 295 /// which must be filled by the code generator. 296 bool hasDelaySlot(MachineOpCode Opcode) const { 297 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 298 } 299 300 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 301 /// custom insertion support when the DAG scheduler is inserting it into a 302 /// machine basic block. 303 bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const { 304 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 305 } 306 307 bool hasVariableOperands(MachineOpCode Opcode) const { 308 return get(Opcode).Flags & M_VARIABLE_OPS; 309 } 310 311 bool isPredicable(MachineOpCode Opcode) const { 312 return get(Opcode).Flags & M_PREDICABLE; 313 } 314 315 bool isNotDuplicable(MachineOpCode Opcode) const { 316 return get(Opcode).Flags & M_NOT_DUPLICABLE; 317 } 318 319 bool hasOptionalDef(MachineOpCode Opcode) const { 320 return get(Opcode).Flags & M_HAS_OPTIONAL_DEF; 321 } 322 323 /// isTriviallyReMaterializable - Return true if the instruction is trivially 324 /// rematerializable, meaning it has no side effects and requires no operands 325 /// that aren't always available. 326 bool isTriviallyReMaterializable(MachineInstr *MI) const { 327 return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) && 328 isReallyTriviallyReMaterializable(MI); 329 } 330 331 /// hasUnmodelledSideEffects - Returns true if the instruction has side 332 /// effects that are not captured by any operands of the instruction or other 333 /// flags. 334 bool hasUnmodelledSideEffects(MachineInstr *MI) const { 335 const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); 336 if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false; 337 if (!(TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true; 338 return !isReallySideEffectFree(MI); // May have side effects 339 } 340protected: 341 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 342 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 343 /// instruction itself is actually trivially rematerializable, considering 344 /// its operands. This is used for targets that have instructions that are 345 /// only trivially rematerializable for specific uses. This predicate must 346 /// return false if the instruction has any side effects other than 347 /// producing a value, or if it requres any address registers that are not 348 /// always available. 349 virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 350 return true; 351 } 352 353 /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this 354 /// method is called to determine if the specific instance of this 355 /// instruction has side effects. This is useful in cases of instructions, 356 /// like loads, which generally always have side effects. A load from a 357 /// constant pool doesn't have side effects, though. So we need to 358 /// differentiate it from the general case. 359 virtual bool isReallySideEffectFree(MachineInstr *MI) const { 360 return false; 361 } 362public: 363 /// getOperandConstraint - Returns the value of the specific constraint if 364 /// it is set. Returns -1 if it is not set. 365 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 366 TOI::OperandConstraint Constraint) const { 367 return get(Opcode).getOperandConstraint(OpNum, Constraint); 368 } 369 370 /// Return true if the instruction is a register to register move 371 /// and leave the source and dest operands in the passed parameters. 372 virtual bool isMoveInstr(const MachineInstr& MI, 373 unsigned& sourceReg, 374 unsigned& destReg) const { 375 return false; 376 } 377 378 /// isLoadFromStackSlot - If the specified machine instruction is a direct 379 /// load from a stack slot, return the virtual or physical register number of 380 /// the destination along with the FrameIndex of the loaded stack slot. If 381 /// not, return 0. This predicate must return 0 if the instruction has 382 /// any side effects other than loading from the stack slot. 383 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 384 return 0; 385 } 386 387 /// isStoreToStackSlot - If the specified machine instruction is a direct 388 /// store to a stack slot, return the virtual or physical register number of 389 /// the source reg along with the FrameIndex of the loaded stack slot. If 390 /// not, return 0. This predicate must return 0 if the instruction has 391 /// any side effects other than storing to the stack slot. 392 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 393 return 0; 394 } 395 396 /// convertToThreeAddress - This method must be implemented by targets that 397 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 398 /// may be able to convert a two-address instruction into one or more true 399 /// three-address instructions on demand. This allows the X86 target (for 400 /// example) to convert ADD and SHL instructions into LEA instructions if they 401 /// would require register copies due to two-addressness. 402 /// 403 /// This method returns a null pointer if the transformation cannot be 404 /// performed, otherwise it returns the last new instruction. 405 /// 406 virtual MachineInstr * 407 convertToThreeAddress(MachineFunction::iterator &MFI, 408 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 409 return 0; 410 } 411 412 /// commuteInstruction - If a target has any instructions that are commutable, 413 /// but require converting to a different instruction or making non-trivial 414 /// changes to commute them, this method can overloaded to do this. The 415 /// default implementation of this method simply swaps the first two operands 416 /// of MI and returns it. 417 /// 418 /// If a target wants to make more aggressive changes, they can construct and 419 /// return a new machine instruction. If an instruction cannot commute, it 420 /// can also return null. 421 /// 422 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0; 423 424 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 425 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 426 /// implemented for a target). Upon success, this returns false and returns 427 /// with the following information in various cases: 428 /// 429 /// 1. If this block ends with no branches (it just falls through to its succ) 430 /// just return false, leaving TBB/FBB null. 431 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 432 /// the destination block. 433 /// 3. If this block ends with an conditional branch and it falls through to 434 /// an successor block, it sets TBB to be the branch destination block and a 435 /// list of operands that evaluate the condition. These 436 /// operands can be passed to other TargetInstrInfo methods to create new 437 /// branches. 438 /// 4. If this block ends with an conditional branch and an unconditional 439 /// block, it returns the 'true' destination in TBB, the 'false' destination 440 /// in FBB, and a list of operands that evaluate the condition. These 441 /// operands can be passed to other TargetInstrInfo methods to create new 442 /// branches. 443 /// 444 /// Note that RemoveBranch and InsertBranch must be implemented to support 445 /// cases where this method returns success. 446 /// 447 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 448 MachineBasicBlock *&FBB, 449 std::vector<MachineOperand> &Cond) const { 450 return true; 451 } 452 453 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 454 /// this is only invoked in cases where AnalyzeBranch returns success. It 455 /// returns the number of instructions that were removed. 456 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 457 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 458 return 0; 459 } 460 461 /// InsertBranch - Insert a branch into the end of the specified 462 /// MachineBasicBlock. This operands to this method are the same as those 463 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 464 /// returns success and when an unconditional branch (TBB is non-null, FBB is 465 /// null, Cond is empty) needs to be inserted. It returns the number of 466 /// instructions inserted. 467 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 468 MachineBasicBlock *FBB, 469 const std::vector<MachineOperand> &Cond) const { 470 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 471 return 0; 472 } 473 474 /// copyRegToReg - Add a copy between a pair of registers 475 virtual void copyRegToReg(MachineBasicBlock &MBB, 476 MachineBasicBlock::iterator MI, 477 unsigned DestReg, unsigned SrcReg, 478 const TargetRegisterClass *DestRC, 479 const TargetRegisterClass *SrcRC) const { 480 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 481 } 482 483 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 484 MachineBasicBlock::iterator MI, 485 unsigned SrcReg, bool isKill, int FrameIndex, 486 const TargetRegisterClass *RC) const { 487 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 488 } 489 490 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 491 SmallVectorImpl<MachineOperand> &Addr, 492 const TargetRegisterClass *RC, 493 SmallVectorImpl<MachineInstr*> &NewMIs) const { 494 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 495 } 496 497 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 498 MachineBasicBlock::iterator MI, 499 unsigned DestReg, int FrameIndex, 500 const TargetRegisterClass *RC) const { 501 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 502 } 503 504 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 505 SmallVectorImpl<MachineOperand> &Addr, 506 const TargetRegisterClass *RC, 507 SmallVectorImpl<MachineInstr*> &NewMIs) const { 508 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 509 } 510 511 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 512 /// saved registers and returns true if it isn't possible / profitable to do 513 /// so by issuing a series of store instructions via 514 /// storeRegToStackSlot(). Returns false otherwise. 515 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 516 MachineBasicBlock::iterator MI, 517 const std::vector<CalleeSavedInfo> &CSI) const { 518 return false; 519 } 520 521 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 522 /// saved registers and returns true if it isn't possible / profitable to do 523 /// so by issuing a series of load instructions via loadRegToStackSlot(). 524 /// Returns false otherwise. 525 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 526 MachineBasicBlock::iterator MI, 527 const std::vector<CalleeSavedInfo> &CSI) const { 528 return false; 529 } 530 531 /// BlockHasNoFallThrough - Return true if the specified block does not 532 /// fall-through into its successor block. This is primarily used when a 533 /// branch is unanalyzable. It is useful for things like unconditional 534 /// indirect branches (jump tables). 535 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 536 return false; 537 } 538 539 /// ReverseBranchCondition - Reverses the branch condition of the specified 540 /// condition list, returning false on success and true if it cannot be 541 /// reversed. 542 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 543 return true; 544 } 545 546 /// insertNoop - Insert a noop into the instruction stream at the specified 547 /// point. 548 virtual void insertNoop(MachineBasicBlock &MBB, 549 MachineBasicBlock::iterator MI) const { 550 assert(0 && "Target didn't implement insertNoop!"); 551 abort(); 552 } 553 554 /// isPredicated - Returns true if the instruction is already predicated. 555 /// 556 virtual bool isPredicated(const MachineInstr *MI) const { 557 return false; 558 } 559 560 /// isUnpredicatedTerminator - Returns true if the instruction is a 561 /// terminator instruction that has not been predicated. 562 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 563 564 /// PredicateInstruction - Convert the instruction into a predicated 565 /// instruction. It returns true if the operation was successful. 566 virtual 567 bool PredicateInstruction(MachineInstr *MI, 568 const std::vector<MachineOperand> &Pred) const = 0; 569 570 /// SubsumesPredicate - Returns true if the first specified predicate 571 /// subsumes the second, e.g. GE subsumes GT. 572 virtual 573 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 574 const std::vector<MachineOperand> &Pred2) const { 575 return false; 576 } 577 578 /// DefinesPredicate - If the specified instruction defines any predicate 579 /// or condition code register(s) used for predication, returns true as well 580 /// as the definition predicate(s) by reference. 581 virtual bool DefinesPredicate(MachineInstr *MI, 582 std::vector<MachineOperand> &Pred) const { 583 return false; 584 } 585 586 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 587 /// values. 588 virtual const TargetRegisterClass *getPointerRegClass() const { 589 assert(0 && "Target didn't implement getPointerRegClass!"); 590 abort(); 591 return 0; // Must return a value in order to compile with VS 2005 592 } 593}; 594 595/// TargetInstrInfoImpl - This is the default implementation of 596/// TargetInstrInfo, which just provides a couple of default implementations 597/// for various methods. This separated out because it is implemented in 598/// libcodegen, not in libtarget. 599class TargetInstrInfoImpl : public TargetInstrInfo { 600protected: 601 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes) 602 : TargetInstrInfo(desc, NumOpcodes) {} 603public: 604 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 605 virtual bool PredicateInstruction(MachineInstr *MI, 606 const std::vector<MachineOperand> &Pred) const; 607 608}; 609 610} // End llvm namespace 611 612#endif 613