TargetInstrInfo.h revision 91c5346d91973a1d3458a20f8c6b0e899b732e38
12a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 22a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 32a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// The LLVM Compiler Infrastructure 42a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 52a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 62a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// License. See LICENSE.TXT for details. 72a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 8868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)//===----------------------------------------------------------------------===// 92a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 102a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// This file describes the target machine instruction set to the code generator. 115d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// 125d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)//===----------------------------------------------------------------------===// 134e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) 1490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#ifndef LLVM_TARGET_TARGETINSTRINFO_H 152a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#define LLVM_TARGET_TARGETINSTRINFO_H 165d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles)#include "llvm/MC/MCInstrInfo.h" 187d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)#include "llvm/CodeGen/DFAPacketizer.h" 192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#include "llvm/CodeGen/MachineFunction.h" 200f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) 212a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)namespace llvm { 221e9bf3e0803691d0a228da41fc608347b6db4340Torne (Richard Coles) 2358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles)class InstrItineraryData; 24c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)class LiveVariables; 252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)class MCAsmInfo; 26868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)class MachineMemOperand; 27eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdochclass MachineRegisterInfo; 282a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)class MDNode; 295d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)class MCInst; 302a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)class SDNode; 312a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)class ScheduleHazardRecognizer; 32ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdochclass SelectionDAG; 335d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)class ScheduleDAG; 342a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)class TargetRegisterClass; 352a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)class TargetRegisterInfo; 36ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdochclass BranchProbability; 37ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch 382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)template<class T> class SmallVectorImpl; 392a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 40c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//--------------------------------------------------------------------------- 42a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)/// 432a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// TargetInstrInfo - Interface to description of machine instruction set 442a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// 45ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdochclass TargetInstrInfo : public MCInstrInfo { 46c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 47868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 48868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)public: 497d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) 50868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) : CallFrameSetupOpcode(CFSetupOpcode), 51a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) CallFrameDestroyOpcode(CFDestroyOpcode) { 52868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) } 53868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 54868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) virtual ~TargetInstrInfo(); 55868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 56868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// getRegClass - Givem a machine instruction descriptor, returns the register 57cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// class constraint for OpNum, or NULL. 58eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, 59eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch unsigned OpNum, 60eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch const TargetRegisterInfo *TRI, 61eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch const MachineFunction &MF) const; 62eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch 63eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// isTriviallyReMaterializable - Return true if the instruction is trivially 64eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// rematerializable, meaning it has no side effects and requires no operands 65a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// that aren't always available. 667d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) bool isTriviallyReMaterializable(const MachineInstr *MI, 67116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch AliasAnalysis *AA = 0) const { 68cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 6990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) (MI->getDesc().isRematerializable() && 7090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) (isReallyTriviallyReMaterializable(MI, AA) || 712a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) isReallyTriviallyReMaterializableGeneric(MI, AA))); 722a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 732a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 742a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)protected: 752a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// isReallyTriviallyReMaterializable - For instructions with opcodes for 76ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 772a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// specify whether the instruction is actually trivially rematerializable, 782a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// taking into consideration its operands. This predicate must return false 792a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// if the instruction has any side effects other than producing a value, or 80a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// if it requres any address registers that are not always available. 81cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 822a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) AliasAnalysis *AA) const { 83d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) return false; 842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 85c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 865d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)private: 875d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 88116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// for which the M_REMATERIALIZABLE flag is set and the target hook 89116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// isReallyTriviallyReMaterializable returns false, this function does 90116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// target-independent tests to determine if the instruction is really 91116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// trivially rematerializable. 92116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 9390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) AliasAnalysis *AA) const; 942a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 95eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdochpublic: 962a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 972a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// frame setup/destroy instructions if they exist (-1 otherwise). Some 9858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// targets use pseudo instructions in order to abstract away the difference 9958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// between operating with a frame pointer and operating without, through the 1002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// use of these two instructions. 1015d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 1025d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 1035d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 104116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 105116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 106116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// extension instruction. That is, it's like a copy where it's legal for the 107116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 108116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// true, then it's expected the pre-extension value is available as a subreg 109116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// of the result register. This also returns the sub-register index in 1105d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// SubIdx. 1112a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual bool isCoalescableExtInstr(const MachineInstr &MI, 1122a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) unsigned &SrcReg, unsigned &DstReg, 1132a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) unsigned &SubIdx) const { 1142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return false; 115c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 116c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 117c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// isLoadFromStackSlot - If the specified machine instruction is a direct 118c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// load from a stack slot, return the virtual or physical register number of 11958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// the destination along with the FrameIndex of the loaded stack slot. If 12058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// not, return 0. This predicate must return 0 if the instruction has 12158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// any side effects other than loading from the stack slot. 12258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 12358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) int &FrameIndex) const { 12490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return 0; 12590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 12690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 12790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 12890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// stack locations as well. This uses a heuristic so it isn't 12990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// reliable for correctness. 13090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 13190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) int &FrameIndex) const { 13290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return 0; 13390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 13490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 13590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// hasLoadFromStackSlot - If the specified machine instruction has 13658e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch /// a load from a stack slot, return true along with the FrameIndex 13768043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// of the loaded stack slot and the machine mem operand containing 13858e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch /// the reference. If not, return false. Unlike 13958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// isLoadFromStackSlot, this returns true for any instructions that 14058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// loads from the stack. This is just a hint, as some cases may be 14158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// missed. 14258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 14358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) const MachineMemOperand *&MMO, 1443551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) int &FrameIndex) const { 1453551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) return 0; 1463551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) } 1473551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) 1483551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// isStoreToStackSlot - If the specified machine instruction is a direct 1493551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// store to a stack slot, return the virtual or physical register number of 1503551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// the source reg along with the FrameIndex of the loaded stack slot. If 1513551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// not, return 0. This predicate must return 0 if the instruction has 1523551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// any side effects other than storing to the stack slot. 1533551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 1543551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) int &FrameIndex) const { 1553551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) return 0; 1563551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) } 1573551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) 1583551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 1593551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// stack locations as well. This uses a heuristic so it isn't 1603551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// reliable for correctness. 1613551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 1623551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) int &FrameIndex) const { 1633551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) return 0; 1645d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 1655d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1665d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// hasStoreToStackSlot - If the specified machine instruction has a 1675d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// store to a stack slot, return true along with the FrameIndex of 1685d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// the loaded stack slot and the machine mem operand containing the 1695d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// reference. If not, return false. Unlike isStoreToStackSlot, 1705d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// this returns true for any instructions that stores to the 1715d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// stack. This is just a hint, as some cases may be missed. 1725d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual bool hasStoreToStackSlot(const MachineInstr *MI, 1735d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) const MachineMemOperand *&MMO, 1745d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) int &FrameIndex) const { 1755d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return 0; 1765d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 1775d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1785d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// reMaterialize - Re-issue the specified 'original' instruction at the 1795d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// specific location targeting a new destination register. 1805d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// The register in Orig->getOperand(0).getReg() will be substituted by 1815d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 1825d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// SubIdx. 1835d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual void reMaterialize(MachineBasicBlock &MBB, 1845d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) MachineBasicBlock::iterator MI, 1855d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) unsigned DestReg, unsigned SubIdx, 1865d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) const MachineInstr *Orig, 1875d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) const TargetRegisterInfo &TRI) const = 0; 1885d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1895d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 1902a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// two-addrss instruction inserted by two-address pass. 1912a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 1922a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineInstr *UseMI, 1935d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) const TargetRegisterInfo &TRI) const { 1945d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // Do nothing. 195b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) } 196b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) 197effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 1985d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// MachineFunction::CloneMachineInstr(), but the target may update operands 1995d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// that are required to be unique. 2005d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 2012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// The instruction must be duplicable as indicated by isNotDuplicable(). 2022a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual MachineInstr *duplicate(MachineInstr *Orig, 2032a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineFunction &MF) const = 0; 204f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) 2052a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// convertToThreeAddress - This method must be implemented by targets that 206f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 2072a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// may be able to convert a two-address instruction into one or more true 208f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// three-address instructions on demand. This allows the X86 target (for 209c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// example) to convert ADD and SHL instructions into LEA instructions if they 210116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// would require register copies due to two-addressness. 211116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// 212116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// This method returns a null pointer if the transformation cannot be 213c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// performed, otherwise it returns the last new instruction. 2142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 2152a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual MachineInstr * 2162a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) convertToThreeAddress(MachineFunction::iterator &MFI, 2172a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 2182a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return 0; 2192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 220f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) 2212a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// commuteInstruction - If a target has any instructions that are 222f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// commutable but require converting to different instructions or making 2232a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// non-trivial changes to commute them, this method can overloaded to do 224f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// that. The default implementation simply swaps the commutable operands. 2252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// If NewMI is false, MI is modified in place and returned; otherwise, a 226f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// new machine instruction is created and returned. Do not call this 227f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// method for a non-commutable instruction, but there may be some cases 228a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// where this method fails and returns null. 2292a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual MachineInstr *commuteInstruction(MachineInstr *MI, 2302a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) bool NewMI = false) const = 0; 231f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) 232c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// findCommutedOpIndices - If specified MI is commutable, return the two 233c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// operand indices that would swap value. Return false if the instruction 234116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// is not in a form which this routine understands. 235116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 2362a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) unsigned &SrcOpIdx2) const = 0; 2372a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 2382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// produceSameValue - Return true if two machine instructions would produce 239f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// identical values. By default, this is only true when the two instructions 2407dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch /// are deemed identical except for defs. If this function is called when the 2412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 242116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// aggressive checks. 243116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch virtual bool produceSameValue(const MachineInstr *MI0, 244116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const MachineInstr *MI1, 245116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const MachineRegisterInfo *MRI = 0) const = 0; 246c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 2472a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 2482a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 2492a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// implemented for a target). Upon success, this returns false and returns 2502a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// with the following information in various cases: 251c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// 2525d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 1. If this block ends with no branches (it just falls through to its succ) 2532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// just return false, leaving TBB/FBB null. 25490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// 2. If this block ends with only an unconditional branch, it sets TBB to be 255010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// the destination block. 2562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 3. If this block ends with a conditional branch and it falls through to a 2572a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// successor block, it sets TBB to be the branch destination block and a 2582a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// list of operands that evaluate the condition. These operands can be 2592a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// passed to other TargetInstrInfo methods to create new branches. 260010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// 4. If this block ends with a conditional branch followed by an 2615d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// unconditional branch, it returns the 'true' destination in TBB, the 2625d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 'false' destination in FBB, and a list of operands that evaluate the 2635d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// condition. These operands can be passed to other TargetInstrInfo 2645d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// methods to create new branches. 2652a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 2662a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// Note that RemoveBranch and InsertBranch must be implemented to support 26790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// cases where this method returns success. 26890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// 26990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// If AllowModify is true, then this routine is allowed to modify the basic 27090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// block (e.g. delete instructions after the unconditional branch). 27190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// 27290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 27390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MachineBasicBlock *&FBB, 27490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) SmallVectorImpl<MachineOperand> &Cond, 27590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) bool AllowModify = false) const { 27690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return true; 27790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 27890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 27990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// RemoveBranch - Remove the branching code at the end of the specific MBB. 28090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// This is only invoked in cases where AnalyzeBranch returns success. It 28190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// returns the number of instructions that were removed. 28290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 28390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!"); 28490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 28590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 28690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// InsertBranch - Insert branch code into the end of the specified 28790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// MachineBasicBlock. The operands to this method are the same as those 28890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// returned by AnalyzeBranch. This is only invoked in cases where 28990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// AnalyzeBranch returns success. It returns the number of instructions 29090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// inserted. 29190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// 29290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// It is also invoked by tail merging to add unconditional branches in 293868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// cases where AnalyzeBranch doesn't apply because there was no original 294868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// branch to analyze. At least this much must be implemented, else tail 295868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// merging needs to be disabled. 296868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 297868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) MachineBasicBlock *FBB, 298868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) const SmallVectorImpl<MachineOperand> &Cond, 299868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) DebugLoc DL) const { 300868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); 301868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) } 30290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 30390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 30490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// after it, replacing it with an unconditional branch to NewDest. This is 30590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// used by the tail merging pass. 30690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 30790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MachineBasicBlock *NewDest) const = 0; 30890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 30990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 31090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// block at the specified instruction (i.e. instruction would be the start 31190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// of a new basic block). 31290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 31390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) MachineBasicBlock::iterator MBBI) const { 31490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return true; 31590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 316a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 317a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// isProfitableToIfCvt - Return true if it's profitable to predicate 318a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// instructions with accumulated instruction latency of "NumCycles" 31990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// of the specified basic block, where the probability of the instructions 32090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// being executed is given by Probability, and Confidence is a measure 32190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// of our confidence that it will be properly predicted. 32290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual 32390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 3247d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) unsigned ExtraPredCycles, 3257d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) const BranchProbability &Probability) const { 3267d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) return false; 3277d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) } 3287d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 3297d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 3307d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// checks for the case where two basic blocks from true and false path 3317d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// of a if-then-else (diamond) are predicated on mutally exclusive 3327d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// predicates, where the probability of the true path being taken is given 3337d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// by Probability, and Confidence is a measure of our confidence that it 3347d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// will be properly predicted. 3357d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) virtual bool 3367d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) isProfitableToIfCvt(MachineBasicBlock &TMBB, 3377d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) unsigned NumTCycles, unsigned ExtraTCycles, 3387d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) MachineBasicBlock &FMBB, 3397d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) unsigned NumFCycles, unsigned ExtraFCycles, 3407d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) const BranchProbability &Probability) const { 3417d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) return false; 34258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 34358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 34458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// isProfitableToDupForIfCvt - Return true if it's profitable for 34558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// if-converter to duplicate instructions of specified accumulated 34658537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// instruction latencies in the specified MBB to enable if-conversion. 3477d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// The probability of the instructions being executed is given by 34858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// Probability, and Confidence is a measure of our confidence that it 34958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// will be properly predicted. 35058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual bool 35158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 35258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) const BranchProbability &Probability) const { 3537d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) return false; 354ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch } 35558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 356ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate 35758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 35858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// exclusive predicates. 359ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// e.g. 36058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// subeq r0, r1, #1 36158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// addne r0, r1, #1 36258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// => 36358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// sub r0, r1, #1 36458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// addne r0, r1, #1 36558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// 36658537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// This may be profitable is conditional instructions are always executed. 36758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 36858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) MachineBasicBlock &FMBB) const { 36958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) return false; 37058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 37158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 37258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// copyPhysReg - Emit instructions to copy a pair of physical registers. 37358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual void copyPhysReg(MachineBasicBlock &MBB, 3744e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) MachineBasicBlock::iterator MI, DebugLoc DL, 3754e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) unsigned DestReg, unsigned SrcReg, 3764e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) bool KillSrc) const { 37758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 378ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch } 3794e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) 38058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// storeRegToStackSlot - Store the specified register of the given register 381ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// class to the specified stack frame index. The store instruction is to be 3827d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// added to the given machine basic block before the specified machine 3834e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// instruction. If isKill is true, the register operand is the last use and 3844e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// must be marked kill. 38558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 386ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch MachineBasicBlock::iterator MI, 3877d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) unsigned SrcReg, bool isKill, int FrameIndex, 388116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const TargetRegisterClass *RC, 389116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const TargetRegisterInfo *TRI) const { 39058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) llvm_unreachable("Target didn't implement " 391ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch "TargetInstrInfo::storeRegToStackSlot!"); 39258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 3934e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) 3944e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// loadRegFromStackSlot - Load the specified register of the given register 39558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// class from the specified stack frame index. The load instruction is to be 396ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// added to the given machine basic block before the specified machine 3977d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// instruction. 3984e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 3994e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) MachineBasicBlock::iterator MI, 40058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) unsigned DestReg, int FrameIndex, 4017d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) const TargetRegisterClass *RC, 4027d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) const TargetRegisterInfo *TRI) const { 4034e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) llvm_unreachable("Target didn't implement " 4044e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) "TargetInstrInfo::loadRegFromStackSlot!"); 40558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 4067d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 4077d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// expandPostRAPseudo - This function is called for all pseudo instructions 408116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// that remain after register allocation. Many pseudo instructions are 4094e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// created to help register allocation. This is the place to convert them 41058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// into real instructions. The target can edit MI in place, or it can insert 411ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch /// new instructions and erase MI. The function should return true if 4127d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// anything was changed. 4134e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 4144e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) return false; 41558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 416ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch 4177d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// emitFrameIndexDebugValue - Emit a target-dependent form of 4184e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// DBG_VALUE encoding the address of a frame index. Addresses would 4194e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// normally be lowered the same way as other addresses on the target, 42058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// e.g. in load instructions. For targets that do not support this 421ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch /// the debug info is simply lost. 4227d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// If you add this for a target you should handle this DBG_VALUE in the 4234e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// target-specific AsmPrinter code as well; you will probably get invalid 4244e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// assembly output if you don't. 42558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 42658537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) int FrameIx, 427a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) uint64_t Offset, 428a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) const MDNode *MDPtr, 429a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) DebugLoc dl) const { 430a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return 0; 431a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } 432116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 433116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 434116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// slot into the specified machine instruction for the specified operand(s). 435116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// If this is possible, a new instruction is returned with the specified 436116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// operand folded, otherwise NULL is returned. 437116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// The new instruction is inserted before MI, and the client is responsible 438116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// for removing the old instruction. 439116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 44058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) const SmallVectorImpl<unsigned> &Ops, 4417d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) int FrameIndex) const; 4427d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 4434e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// foldMemoryOperand - Same as the previous version except it allows folding 44458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// of any load and store from / to any address, not just from a specific 44558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// stack slot. 44658537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 4474e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) const SmallVectorImpl<unsigned> &Ops, 44858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) MachineInstr* LoadMI) const; 44958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 4504e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)protected: 4514e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// foldMemoryOperandImpl - Target-dependent implementation for 4524e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 4534e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) /// take care of adding a MachineMemOperand to the newly created instruction. 4544e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 4554e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) MachineInstr* MI, 4564e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) const SmallVectorImpl<unsigned> &Ops, 4574e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) int FrameIndex) const { 4584e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) return 0; 4597d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) } 4607d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 46158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// foldMemoryOperandImpl - Target-dependent implementation for 46258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 46358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// take care of adding a MachineMemOperand to the newly created instruction. 46458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 46558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) MachineInstr* MI, 46658537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) const SmallVectorImpl<unsigned> &Ops, 46758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) MachineInstr* LoadMI) const { 46858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) return 0; 46958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 47058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 47158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles)public: 47258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// canFoldMemoryOperand - Returns true for the specified load / store if 47358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// folding is possible. 47458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual 47558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) bool canFoldMemoryOperand(const MachineInstr *MI, 47658537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) const SmallVectorImpl<unsigned> &Ops) const =0; 47758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 47858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// unfoldMemoryOperand - Separate a single instruction which folded a load or 47958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// a store or a load and a store into two or more instruction. If this is 48058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// possible, returns true as well as the new instructions by reference. 48158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 48258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 48358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) SmallVectorImpl<MachineInstr*> &NewMIs) const{ 48458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) return false; 48558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 4865d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 48758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 48858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) SmallVectorImpl<SDNode*> &NewNodes) const { 489d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) return false; 490d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) } 491d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 492d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 493d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// instruction after load / store are unfolded from an instruction of the 494d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// specified opcode. It returns zero if the specified unfolding is not 495d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// possible. If LoadRegIndex is non-null, it is filled in with the operand 4965d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// index of the operand which will hold the register holding the loaded 4975d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// value. 498d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 4995d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) bool UnfoldLoad, bool UnfoldStore, 500d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned *LoadRegIndex = 0) const { 501d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) return 0; 502d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) } 503d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 504d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 505d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// to determine if two loads are loading from the same base address. It 506d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// should only return true if the base pointers are the same and the 507d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// only differences between the two addresses are the offset. It also returns 508d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// the offsets by reference. 509d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 510d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) int64_t &Offset1, int64_t &Offset2) const { 511d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) return false; 5125d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 5135d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 5145d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 5155d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 5165d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// be scheduled togther. On some targets if two loads are loading from 5175d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// addresses in the same cache line, it's better if they are scheduled 5185d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// together. This function takes two integers that represent the load offsets 5195d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// from the common base address. It returns true if it decides it's desirable 5205d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// to schedule the two loads together. "NumLoads" is the number of loads that 5215d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// have already been scheduled after Load1. 522cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 523cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) int64_t Offset1, int64_t Offset2, 524cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned NumLoads) const { 525a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return false; 526cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 527cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 5285d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// ReverseBranchCondition - Reverses the branch condition of the specified 5295d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// condition list, returning false on success and true if it cannot be 5305d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// reversed. 5315d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual 5325d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 5335d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return true; 53423730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) } 53523730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) 53623730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) /// insertNoop - Insert a noop into the instruction stream at the specified 53723730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) /// point. 53823730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) virtual void insertNoop(MachineBasicBlock &MBB, 53923730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) MachineBasicBlock::iterator MI) const; 54023730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) 54123730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) 54223730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 54323730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) virtual void getNoopForMachoTarget(MCInst &NopInst) const { 54423730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) // Default to just using 'nop' string. 54523730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) } 54623730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) 54723730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) 54823730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) /// isPredicated - Returns true if the instruction is already predicated. 54923730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) /// 55023730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) virtual bool isPredicated(const MachineInstr *MI) const { 55123730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) return false; 55223730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) } 55323730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) 55423730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) /// isUnpredicatedTerminator - Returns true if the instruction is a 555010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// terminator instruction that has not been predicated. 556010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const = 0; 557010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 558010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// PredicateInstruction - Convert the instruction into a predicated 559010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// instruction. It returns true if the operation was successful. 560010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual 561010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) bool PredicateInstruction(MachineInstr *MI, 562010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const SmallVectorImpl<MachineOperand> &Pred) const = 0; 563010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 564010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// SubsumesPredicate - Returns true if the first specified predicate 565010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// subsumes the second, e.g. GE subsumes GT. 566010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual 567010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 568010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const SmallVectorImpl<MachineOperand> &Pred2) const { 569010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return false; 570010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) } 571010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 572010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// DefinesPredicate - If the specified instruction defines any predicate 573010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// or condition code register(s) used for predication, returns true as well 574010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// as the definition predicate(s) by reference. 575010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual bool DefinesPredicate(MachineInstr *MI, 576010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) std::vector<MachineOperand> &Pred) const { 577010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return false; 578010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) } 579010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 580010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// isPredicable - Return true if the specified instruction can be predicated. 581010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// By default, this returns true for every instruction with a 582010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// PredicateOperand. 583010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual bool isPredicable(MachineInstr *MI) const { 584010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return MI->getDesc().isPredicable(); 585010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) } 586010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 587010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 588010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// instruction that defines the specified register class. 589010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 590010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return true; 591010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) } 592010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 593010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// isSchedulingBoundary - Test if the given instruction should be 594010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// considered a scheduling boundary. This primarily includes labels and 595010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// terminators. 596010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual bool isSchedulingBoundary(const MachineInstr *MI, 597010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const MachineBasicBlock *MBB, 598010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const MachineFunction &MF) const = 0; 599010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 600010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// Measure the specified inline asm to determine an approximation of its 601010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// length. 602010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual unsigned getInlineAsmLength(const char *Str, 603010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const MCAsmInfo &MAI) const; 604010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 605010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 606010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// use for this target when scheduling the machine instructions before 607010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// register allocation. 608010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual ScheduleHazardRecognizer* 609010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) CreateTargetHazardRecognizer(const TargetMachine *TM, 610010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const ScheduleDAG *DAG) const = 0; 611010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 612010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer 613010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// to use for this target when scheduling the machine instructions before 614010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// register allocation. 615010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual ScheduleHazardRecognizer* 616010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) CreateTargetMIHazardRecognizer(const InstrItineraryData*, 617010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const ScheduleDAG *DAG) const = 0; 618010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 619010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 620010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// recognizer to use for this target when scheduling the machine instructions 621010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// after register allocation. 622010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual ScheduleHazardRecognizer* 623010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 624010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const ScheduleDAG *DAG) const = 0; 625010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 626010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// AnalyzeCompare - For a comparison instruction, return the source register 627010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// in SrcReg and the value it compares against in CmpValue. Return true if 628010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// the comparison instruction can be analyzed. 629010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual bool AnalyzeCompare(const MachineInstr *MI, 630010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) unsigned &SrcReg, int &Mask, int &Value) const { 631010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return false; 632010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) } 633010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 634010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// OptimizeCompareInstr - See if the comparison instruction can be converted 635010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// into something more efficient. E.g., on ARM most instructions can set the 636010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// flags register, obviating the need for a separate CMP. 637010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, 638010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) unsigned SrcReg, int Mask, int Value, 639010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const MachineRegisterInfo *MRI) const { 640010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return false; 641010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) } 642010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 643010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// OptimizeSubInstr - See if the SUB instruction can be converted into 644010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// something more efficient E.g., on X86, we can replace SUB with CMP 645010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// if the actual result of SUB is not used. 6462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual bool OptimizeSubInstr(MachineInstr *SubInstr, 6472a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) const MachineRegisterInfo *MRI) const { 6483240926e260ce088908e02ac07a6cf7b0c0cbf44Ben Murdoch return false; 6492a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 6502a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 6517dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch /// FoldImmediate - 'Reg' is known to be defined by a move immediate 6522a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// instruction, try to fold the immediate into the use instruction. 6532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 65458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) unsigned Reg, MachineRegisterInfo *MRI) const { 655c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return false; 656c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 657116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 658116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// getNumMicroOps - Return the number of u-operations the given machine 659116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// instruction will be decoded to on the target cpu. 660116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 661116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const MachineInstr *MI) const; 662116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 663116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// isZeroCost - Return true for pseudo instructions that don't consume any 664116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// machine resources in their current form. These are common cases that the 665116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// scheduler should consider free, rather than conservatively handling them 666116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// as instructions with no itinerary. 667116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch bool isZeroCost(unsigned Opcode) const { 668116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch return Opcode <= TargetOpcode::COPY; 669116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch } 670116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 671116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// getOperandLatency - Compute and return the use operand latency of a given 672116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// pair of def and use. 673116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// In most cases, the static scheduling itinerary was enough to determine the 674116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// operand latency. But it may not be possible for instructions with variable 675116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// number of defs / uses. 676116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch virtual int getOperandLatency(const InstrItineraryData *ItinData, 677116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const MachineInstr *DefMI, unsigned DefIdx, 678116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const MachineInstr *UseMI, unsigned UseIdx) const; 679a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 680a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) virtual int getOperandLatency(const InstrItineraryData *ItinData, 681a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) SDNode *DefNode, unsigned DefIdx, 682a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) SDNode *UseNode, unsigned UseIdx) const = 0; 683a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 684a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// getOutputLatency - Compute and return the output dependency latency of a 685c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// a given pair of defs which both target the same register. This is usually 686c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// one. 687f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) virtual unsigned getOutputLatency(const InstrItineraryData *ItinData, 688c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) const MachineInstr *DefMI, unsigned DefIdx, 689c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) const MachineInstr *DepMI) const { 690c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return 1; 691f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) } 692c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 693c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// getInstrLatency - Compute the instruction latency of a given instruction. 694c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// If the instruction has higher cost when predicated, it's returned via 695c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// PredCost. 696c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) virtual int getInstrLatency(const InstrItineraryData *ItinData, 697c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) const MachineInstr *MI, 698c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) unsigned *PredCost = 0) const; 6992a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 7002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual int getInstrLatency(const InstrItineraryData *ItinData, 7012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) SDNode *Node) const = 0; 7020f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) 7030f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) /// isHighLatencyDef - Return true if this opcode has high latency to its 7040f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) /// result. 7050f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) virtual bool isHighLatencyDef(int opc) const { return false; } 7060f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) 7070f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 708c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// and an use in the current loop, return true if the target considered 709868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// it 'high'. This is used by optimization passes such as machine LICM to 710c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// determine whether it makes sense to hoist an instruction out even in 711868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// high register pressure situation. 712c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) virtual 71390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) bool hasHighOperandLatency(const InstrItineraryData *ItinData, 71490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const MachineRegisterInfo *MRI, 71590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const MachineInstr *DefMI, unsigned DefIdx, 71658537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) const MachineInstr *UseMI, unsigned UseIdx) const { 71758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) return false; 71858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 71958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 7205d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 7215d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// if the target considered it 'low'. 7225d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual 7235d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) bool hasLowDefLatency(const InstrItineraryData *ItinData, 7242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) const MachineInstr *DefMI, unsigned DefIdx) const; 7252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 726ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// verifyInstruction - Perform target specific instruction verification. 727ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch virtual 728ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { 729ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch return true; 730ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch } 731f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 732ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// getExecutionDomain - Return the current execution domain and bit mask of 733ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// possible domains for instruction. 734ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// 735ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// Some micro-architectures have multiple execution domains, and multiple 736ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// opcodes that perform the same operation in different domains. For 737ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// example, the x86 architecture provides the por, orps, and orpd 7382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// instructions that all do the same thing. There is a latency penalty if a 7392a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// register is written in one domain and read in another. 7402a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 7415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// This function returns a pair (domain, mask) containing the execution 7425d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 7435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// function can be used to change the opcode to one of the domains in the 7445d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// bit mask. Instructions whose execution domain can't be changed should 7455d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// return a 0 mask. 7465d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 7475d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// The execution domain numbers don't have any special meaning except domain 7485d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 0 is used for instructions that are not associated with any interesting 749a02191e04bc25c4935f804f2c080ae28663d096dBen Murdoch /// execution domain. 750f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// 751a02191e04bc25c4935f804f2c080ae28663d096dBen Murdoch virtual std::pair<uint16_t, uint16_t> 752a02191e04bc25c4935f804f2c080ae28663d096dBen Murdoch getExecutionDomain(const MachineInstr *MI) const { 7535d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return std::make_pair(0, 0); 7545d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 7555d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 7565d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// setExecutionDomain - Change the opcode of MI to execute in Domain. 7570529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// 7580529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// The bit (1 << Domain) must be set in the mask returned from 7590529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// getExecutionDomain(MI). 7600529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// 7610529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {} 7620529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch 7630529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch 7640529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// getPartialRegUpdateClearance - Returns the preferred minimum clearance 7650529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// before an instruction with an unwanted partial register update. 7660529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// 7670529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// Some instructions only write part of a register, and implicitly need to 7680529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// read the other parts of the register. This may cause unwanted stalls 769f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// preventing otherwise unrelated instructions from executing in parallel in 770f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// an out-of-order CPU. 771f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// 772f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// For example, the x86 instruction cvtsi2ss writes its result to bits 773f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 7740529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// the instruction needs to wait for the old value of the register to become 7750529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// available: 7760529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// 7770529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch /// addps %xmm1, %xmm0 778116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// movaps %xmm0, (%rax) 779116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// cvtsi2ss %rbx, %xmm0 780a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// 781116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// In the code above, the cvtsi2ss instruction needs to wait for the addps 782116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// instruction before it can issue, even though the high bits of %xmm0 783116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// probably aren't needed. 784116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// 785116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// This hook returns the preferred clearance before MI, measured in 786116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// instructions. Other defs of MI's operand OpNum are avoided in the last N 787a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// instructions before MI. It should only return a positive value for 788116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// unwanted dependencies. If the old bits of the defined register have 789116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// useful values, or if MI is determined to otherwise read the dependency, 790116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// the hook should return 0. 791116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// 792116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// The unwanted dependency may be handled by: 793116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// 794116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// 1. Allocating the same register for an MI def and use. That makes the 795116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// unwanted dependency identical to a required dependency. 796116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// 797116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// 2. Allocating a register for the def that has no defs in the previous N 798116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// instructions. 799116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// 800116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// 3. Calling breakPartialRegDependency() with the same arguments. This 801a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// allows the target to insert a dependency breaking instruction. 8025d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 8035d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual unsigned 8045d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 8055d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) const TargetRegisterInfo *TRI) const { 8065d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // The default implementation returns 0 for no partial register dependency. 8075d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return 0; 808f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) } 809f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) 810f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// breakPartialRegDependency - Insert a dependency-breaking instruction 811f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// before MI to eliminate an unwanted dependency on OpNum. 812f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// 813f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// If it wasn't possible to avoid a def in the last N instructions before MI 814f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// (see getPartialRegUpdateClearance), this hook will be called to break the 815f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) /// unwanted dependency. 8162a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 8172a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// On x86, an xorps instruction can be used as a dependency breaker: 818c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// 8192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// addps %xmm1, %xmm0 8202a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// movaps %xmm0, (%rax) 8212a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// xorps %xmm0, %xmm0 8225d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// cvtsi2ss %rbx, %xmm0 8235d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 8242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// An <imp-kill> operand should be added to MI if an instruction was 8255d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// inserted. This ties the instructions together in the post-ra scheduler. 8265d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 8275d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual void 8285d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 8295d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) const TargetRegisterInfo *TRI) const {} 8305d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 831010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// Create machine specific model for scheduling. 832a02191e04bc25c4935f804f2c080ae28663d096dBen Murdoch virtual DFAPacketizer* 833a02191e04bc25c4935f804f2c080ae28663d096dBen Murdoch CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const { 8345d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return NULL; 8352a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 836868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 837868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)private: 8385d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) int CallFrameSetupOpcode, CallFrameDestroyOpcode; 8395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)}; 8405d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 8415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// TargetInstrInfoImpl - This is the default implementation of 8425f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// TargetInstrInfo, which just provides a couple of default implementations 8435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)/// for various methods. This separated out because it is implemented in 844868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)/// libcodegen, not in libtarget. 845116680a4aac90f2aa7413d9095a592090648e557Ben Murdochclass TargetInstrInfoImpl : public TargetInstrInfo { 846116680a4aac90f2aa7413d9095a592090648e557Ben Murdochprotected: 847116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch TargetInstrInfoImpl(int CallFrameSetupOpcode = -1, 848116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch int CallFrameDestroyOpcode = -1) 849116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch : TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 850a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)public: 851a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 852a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) MachineBasicBlock *NewDest) const; 853a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) virtual MachineInstr *commuteInstruction(MachineInstr *MI, 854a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) bool NewMI = false) const; 85558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 856cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned &SrcOpIdx2) const; 857cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) virtual bool canFoldMemoryOperand(const MachineInstr *MI, 858cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const SmallVectorImpl<unsigned> &Ops) const; 859cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 860cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const MachineMemOperand *&MMO, 861cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) int &FrameIndex) const; 862a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) virtual bool hasStoreToStackSlot(const MachineInstr *MI, 863f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) const MachineMemOperand *&MMO, 864f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) int &FrameIndex) const; 865116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 866116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch virtual bool PredicateInstruction(MachineInstr *MI, 867116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const SmallVectorImpl<MachineOperand> &Pred) const; 868116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch virtual void reMaterialize(MachineBasicBlock &MBB, 869a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) MachineBasicBlock::iterator MI, 870116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch unsigned DestReg, unsigned SubReg, 8715d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) const MachineInstr *Orig, 872a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) const TargetRegisterInfo &TRI) const; 873a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) virtual MachineInstr *duplicate(MachineInstr *Orig, 8742a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineFunction &MF) const; 8752a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual bool produceSameValue(const MachineInstr *MI0, 8762a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) const MachineInstr *MI1, 8772a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) const MachineRegisterInfo *MRI) const; 878a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) virtual bool isSchedulingBoundary(const MachineInstr *MI, 8797d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) const MachineBasicBlock *MBB, 8802a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) const MachineFunction &MF) const; 8812a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) using TargetInstrInfo::getOperandLatency; 8822a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual int getOperandLatency(const InstrItineraryData *ItinData, 8832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) SDNode *DefNode, unsigned DefIdx, 8842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) SDNode *UseNode, unsigned UseIdx) const; 8852a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) using TargetInstrInfo::getInstrLatency; 8862a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual int getInstrLatency(const InstrItineraryData *ItinData, 88758e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch SDNode *Node) const; 88858e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch 88958e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch bool usePreRAHazardRecognizer() const; 89068043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 89158e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch virtual ScheduleHazardRecognizer * 89258e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const; 89358e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch 89458e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch virtual ScheduleHazardRecognizer * 89558e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch CreateTargetMIHazardRecognizer(const InstrItineraryData*, 89658e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch const ScheduleDAG*) const; 89758e6fbe4ee35d65e14b626c557d37565bf8ad179Ben Murdoch 89858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual ScheduleHazardRecognizer * 89958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 900eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch const ScheduleDAG*) const; 901a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)}; 90258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 903a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)} // End llvm namespace 9043551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) 90558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles)#endif 906eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch