TargetInstrInfo.h revision 93ad2cf91092c4ff45ace5b87b97179202e3de06
15c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 25c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// 35c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// The LLVM Compiler Infrastructure 45c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// 55c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// This file was developed by the LLVM research group and is distributed under 65c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// the University of Illinois Open Source License. See LICENSE.TXT for details. 75c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// 85c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu//===----------------------------------------------------------------------===// 95c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// 105c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// This file describes the target machine instructions to the code generator. 115c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// 125c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu//===----------------------------------------------------------------------===// 135c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 146e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)#ifndef LLVM_TARGET_TARGETINSTRINFO_H 156e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)#define LLVM_TARGET_TARGETINSTRINFO_H 165c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 175c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu#include "llvm/CodeGen/MachineBasicBlock.h" 185c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu#include "Support/DataTypes.h" 196e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)#include <vector> 205c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu#include <cassert> 21010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 225c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liunamespace llvm { 235c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 245c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuclass MachineInstr; 255c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuclass TargetMachine; 266e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)class Value; 275c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuclass Type; 285c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuclass Instruction; 295c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuclass Constant; 30010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)class Function; 315c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuclass MachineCodeForInstruction; 325c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 335c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu//--------------------------------------------------------------------------- 345c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// Data types used to define information about a single machine instruction 356e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)//--------------------------------------------------------------------------- 365c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 375c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liutypedef short MachineOpCode; 385c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liutypedef unsigned InstrSchedClass; 39010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 405c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu//--------------------------------------------------------------------------- 415c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// struct TargetInstrDescriptor: 425c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// Predefined information about each machine instruction. 435c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// Designed to initialized statically. 446e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)// 455c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 465c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_NOP_FLAG = 1 << 0; 475c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_BRANCH_FLAG = 1 << 1; 485c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_CALL_FLAG = 1 << 2; 495c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_RET_FLAG = 1 << 3; 505c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_BARRIER_FLAG = 1 << 4; 515c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_CC_FLAG = 1 << 6; 525c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_LOAD_FLAG = 1 << 10; 535c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_STORE_FLAG = 1 << 12; 545c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_DUMMY_PHI_FLAG = 1 << 13; 555c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction 565c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub 575c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_2_ADDR_FLAG = 1 << 15; 585c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 595c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 605c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// block? Typically this is things like return and branch instructions. 615c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// Various passes use this to insert code into the bottom of a basic block, but 625c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu// before control flow occurs. 635c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuconst unsigned M_TERMINATOR_FLAG = 1 << 16; 645c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 655c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liustruct TargetInstrDescriptor { 665c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu const char * Name; // Assembly language mnemonic for the opcode. 675c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu int numOperands; // Number of args; -1 if variable #args 685c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu int resultPos; // Position of the result; -1 if no result 695c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0. 705c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 715c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // smallest -ve value is -(maxImmedConst+1). 725c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned numDelaySlots; // Number of delay slots after instruction 735c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned latency; // Latency in machine cycles 745c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu InstrSchedClass schedClass; // enum identifying instr sched class 755c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned Flags; // flags identifying machine instr class 765c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned TSFlags; // Target Specific Flag values 775c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu const unsigned *ImplicitUses; // Registers implicitly read by this instr 785c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 795c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu}; 805c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 815c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 825c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu//--------------------------------------------------------------------------- 835c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu/// 845c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu/// TargetInstrInfo - Interface to description of machine instructions 855c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu/// 865c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liuclass TargetInstrInfo { 875c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu const TargetInstrDescriptor* desc; // raw array to allow static init'n 885c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned NumOpcodes; // number of entries in the desc array 895c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned numRealOpCodes; // number of non-dummy op codes 905c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 911320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 925c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 935c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liupublic: 945c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 955c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu virtual ~TargetInstrInfo(); 965c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 975c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // Invariant: All instruction sets use opcode #0 as the PHI instruction 985c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu enum { PHI = 0 }; 995c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1005c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned getNumOpcodes() const { return NumOpcodes; } 1015c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1025c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu /// get - Return the machine instruction descriptor that corresponds to the 1035c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu /// specified instruction opcode. 1045c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu /// 105f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 1065c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu assert((unsigned)Opcode < NumOpcodes); 1075c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return desc[Opcode]; 1085c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1095c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1105c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu const char *getName(MachineOpCode Opcode) const { 1115c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Name; 1125c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 113cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 1141320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci int getNumOperands(MachineOpCode Opcode) const { 1151320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return get(Opcode).numOperands; 116cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 117cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 1186d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) 1190de6073388f4e2780db8536178b129cd8f6ab386Torne (Richard Coles) InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 1201320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return get(Opcode).schedClass; 1215c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1225c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1235c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu const unsigned *getImplicitUses(MachineOpCode Opcode) const { 1245c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).ImplicitUses; 1255c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1265c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1275c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 1285c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).ImplicitDefs; 1295c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1305c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1315c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1325c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 1335c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // Query instruction class flags according to the machine-independent 1345c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // flags listed above. 1355c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 1365c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool isReturn(MachineOpCode Opcode) const { 137f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) return get(Opcode).Flags & M_RET_FLAG; 1385c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1395c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1405c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool isPseudoInstr(MachineOpCode Opcode) const { 1415c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Flags & M_PSEUDO_FLAG; 1425c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1435c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool isTwoAddrInstr(MachineOpCode Opcode) const { 1445c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Flags & M_2_ADDR_FLAG; 1451320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci } 1465c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool isTerminatorInstr(unsigned Opcode) const { 1475c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Flags & M_TERMINATOR_FLAG; 1485c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1495c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 150116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// Return true if the instruction is a register to register move 151116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// and leave the source and dest operands in the passed parameters. 152116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch virtual bool isMoveInstr(const MachineInstr& MI, 1535c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned& sourceReg, 1545c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned& destReg) const { 1555c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return false; 1565c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1575c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1585c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu /// Insert a goto (unconditional branch) sequence to TMBB, at the 1595c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu /// end of MBB 1605c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu virtual void insertGoto(MachineBasicBlock& MBB, 1615c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu MachineBasicBlock& TMBB) const { 1625c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu assert(0 && "Target didn't implement insertGoto!"); 1635c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1645c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1655c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu /// Reverses the branch condition of the MachineInstr pointed by 1665c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu /// MI. The instruction is replaced and the new MI is returned. 1675c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu virtual MachineBasicBlock::iterator 1685c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu reverseBranchCondition(MachineBasicBlock::iterator MI) const { 1695c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu assert(0 && "Target didn't implement reverseBranchCondition!"); 1705c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu abort(); 1715c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return MI; 1725c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1735c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1745c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu //------------------------------------------------------------------------- 1755c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // Code generation support for creating individual machine instructions 1765c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 1775c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // WARNING: These methods are Sparc specific 1785c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 1795c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED! 1805c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 1815c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu //------------------------------------------------------------------------- 1825c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 1835c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu unsigned getNumDelaySlots(MachineOpCode Opcode) const { 1845c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).numDelaySlots; 1855c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1865c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool isCCInstr(MachineOpCode Opcode) const { 1875c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Flags & M_CC_FLAG; 1885c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1895c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool isNop(MachineOpCode Opcode) const { 1905c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Flags & M_NOP_FLAG; 1915c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 1925c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool isBranch(MachineOpCode Opcode) const { 1935c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Flags & M_BRANCH_FLAG; 1945c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 195f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// isBarrier - Returns true if the specified instruction stops control flow 1965c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu /// from executing the instruction immediately following it. Examples include 1975c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu /// unconditional branches and return instructions. 1985c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool isBarrier(MachineOpCode Opcode) const { 1995c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Flags & M_BARRIER_FLAG; 2005c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 2015c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool isCall(MachineOpCode Opcode) const { 2025c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Flags & M_CALL_FLAG; 203cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 2041320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci bool isLoad(MachineOpCode Opcode) const { 2051320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return get(Opcode).Flags & M_LOAD_FLAG; 206cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 207cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) bool isStore(MachineOpCode Opcode) const { 2086d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) return get(Opcode).Flags & M_STORE_FLAG; 2090de6073388f4e2780db8536178b129cd8f6ab386Torne (Richard Coles) } 2101320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci bool isDummyPhiInstr(MachineOpCode Opcode) const { 2115c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).Flags & M_DUMMY_PHI_FLAG; 2125c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 2135c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 2145c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu virtual bool hasResultInterlock(MachineOpCode Opcode) const { 2155c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return true; 2165c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 2175c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 2185c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 2195c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // Latencies for individual instructions and instruction pairs 2205c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 2215c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu virtual int minLatency(MachineOpCode Opcode) const { 2225c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).latency; 2235c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 2245c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 2255c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu virtual int maxLatency(MachineOpCode Opcode) const { 2265c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).latency; 2275c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 228f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 2295c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 2305c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // Which operand holds an immediate constant? Returns -1 if none 2315c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 2325c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu virtual int getImmedConstantPos(MachineOpCode Opcode) const { 2335c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return -1; // immediate position is machine specific, so say -1 == "none" 2345c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 2355c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 2361320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // Check if the specified constant fits in the immediate field 2375c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // of this machine instruction 2385c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 2395c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu virtual bool constantFitsInImmedField(MachineOpCode Opcode, 2405c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu int64_t intValue) const; 241116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 242116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // Return the largest positive constant that can be held in the IMMED field 243116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // of this machine instruction. 2445c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // isSignExtended is set to true if the value is sign-extended before use 2455c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // (this is true for all immediate fields in SPARC instructions). 2465c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // Return 0 if the instruction has no IMMED field. 2475c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // 2485c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu virtual uint64_t maxImmedConstant(MachineOpCode Opcode, 2495c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu bool &isSignExtended) const { 2505c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu isSignExtended = get(Opcode).immedIsSignExtended; 2515c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return get(Opcode).maxImmedConst; 2525c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu } 2535c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu}; 2545c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 2555c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu} // End llvm namespace 2565c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 2575c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu#endif 2585c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu