TargetInstrInfo.h revision 962021bc7f6721c20c7dfe8ca809e2d98b1c554a
14a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 23484964a86451e86dcf04be9bd8c0d76ee04f081rossberg@chromium.org// 33484964a86451e86dcf04be9bd8c0d76ee04f081rossberg@chromium.org// The LLVM Compiler Infrastructure 44a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com// 5196eb601290dc49c3754da728dc58700dff2de1bmachenbach@chromium.org// This file is distributed under the University of Illinois Open Source 65de0074a922429f5e0ec2cf140c2d2989bf88140yangguo@chromium.org// License. See LICENSE.TXT for details. 75de0074a922429f5e0ec2cf140c2d2989bf88140yangguo@chromium.org// 84a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com//===----------------------------------------------------------------------===// 94a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com// 104a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com// This file describes the target machine instruction set to the code generator. 114a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com// 124a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com//===----------------------------------------------------------------------===// 139f18d9111f676f2899d9aa2444130c985eb75395machenbach@chromium.org 149f18d9111f676f2899d9aa2444130c985eb75395machenbach@chromium.org#ifndef LLVM_TARGET_TARGETINSTRINFO_H 154a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com#define LLVM_TARGET_TARGETINSTRINFO_H 164f99be9ff2091451687891a05d99cc31990de709hpayer@chromium.org 174a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com#include "llvm/Target/TargetInstrDesc.h" 184a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com#include "llvm/CodeGen/MachineFunction.h" 194a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.com 20d4be0f0c0edfc0a0b46e745055c3dc497c0ffcb5verwaest@chromium.orgnamespace llvm { 21c8cbc43a1fd5fda5d6a1e172f720cbd1215157c8machenbach@chromium.org 22c8cbc43a1fd5fda5d6a1e172f720cbd1215157c8machenbach@chromium.orgclass CalleeSavedInfo; 23c8cbc43a1fd5fda5d6a1e172f720cbd1215157c8machenbach@chromium.orgclass LiveVariables; 244a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.comclass MCAsmInfo; 254a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.comclass MachineMemOperand; 264a6c3279070e8f133607a74c08d8c08ac394ab98erik.corry@gmail.comclass MDNode; 27class SDNode; 28class SelectionDAG; 29class TargetRegisterClass; 30class TargetRegisterInfo; 31 32template<class T> class SmallVectorImpl; 33 34 35//--------------------------------------------------------------------------- 36/// 37/// TargetInstrInfo - Interface to description of machine instruction set 38/// 39class TargetInstrInfo { 40 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 41 unsigned NumOpcodes; // Number of entries in the desc array 42 43 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 44 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 45public: 46 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 47 virtual ~TargetInstrInfo(); 48 49 unsigned getNumOpcodes() const { return NumOpcodes; } 50 51 /// get - Return the machine instruction descriptor that corresponds to the 52 /// specified instruction opcode. 53 /// 54 const TargetInstrDesc &get(unsigned Opcode) const { 55 assert(Opcode < NumOpcodes && "Invalid opcode!"); 56 return Descriptors[Opcode]; 57 } 58 59 /// isTriviallyReMaterializable - Return true if the instruction is trivially 60 /// rematerializable, meaning it has no side effects and requires no operands 61 /// that aren't always available. 62 bool isTriviallyReMaterializable(const MachineInstr *MI, 63 AliasAnalysis *AA = 0) const { 64 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 65 (MI->getDesc().isRematerializable() && 66 (isReallyTriviallyReMaterializable(MI, AA) || 67 isReallyTriviallyReMaterializableGeneric(MI, AA))); 68 } 69 70protected: 71 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 72 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 73 /// specify whether the instruction is actually trivially rematerializable, 74 /// taking into consideration its operands. This predicate must return false 75 /// if the instruction has any side effects other than producing a value, or 76 /// if it requres any address registers that are not always available. 77 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 78 AliasAnalysis *AA) const { 79 return false; 80 } 81 82private: 83 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 84 /// for which the M_REMATERIALIZABLE flag is set and the target hook 85 /// isReallyTriviallyReMaterializable returns false, this function does 86 /// target-independent tests to determine if the instruction is really 87 /// trivially rematerializable. 88 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 89 AliasAnalysis *AA) const; 90 91public: 92 /// isMoveInstr - Return true if the instruction is a register to register 93 /// move and return the source and dest operands and their sub-register 94 /// indices by reference. 95 virtual bool isMoveInstr(const MachineInstr& MI, 96 unsigned& SrcReg, unsigned& DstReg, 97 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 98 return false; 99 } 100 101 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 102 /// extension instruction. That is, it's like a copy where it's legal for the 103 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 104 /// true, then it's expected the pre-extension value is available as a subreg 105 /// of the result register. This also returns the sub-register index in 106 /// SubIdx. 107 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 108 unsigned &SrcReg, unsigned &DstReg, 109 unsigned &SubIdx) const { 110 return false; 111 } 112 113 /// isIdentityCopy - Return true if the instruction is a copy (or 114 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 115 /// destination registers are the same. 116 bool isIdentityCopy(const MachineInstr &MI) const { 117 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 118 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 119 SrcReg == DstReg) 120 return true; 121 122 if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG && 123 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 124 return true; 125 126 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG || 127 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) && 128 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 129 return true; 130 return false; 131 } 132 133 /// isLoadFromStackSlot - If the specified machine instruction is a direct 134 /// load from a stack slot, return the virtual or physical register number of 135 /// the destination along with the FrameIndex of the loaded stack slot. If 136 /// not, return 0. This predicate must return 0 if the instruction has 137 /// any side effects other than loading from the stack slot. 138 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 139 int &FrameIndex) const { 140 return 0; 141 } 142 143 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 144 /// stack locations as well. This uses a heuristic so it isn't 145 /// reliable for correctness. 146 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 147 int &FrameIndex) const { 148 return 0; 149 } 150 151 /// hasLoadFromStackSlot - If the specified machine instruction has 152 /// a load from a stack slot, return true along with the FrameIndex 153 /// of the loaded stack slot and the machine mem operand containing 154 /// the reference. If not, return false. Unlike 155 /// isLoadFromStackSlot, this returns true for any instructions that 156 /// loads from the stack. This is just a hint, as some cases may be 157 /// missed. 158 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 159 const MachineMemOperand *&MMO, 160 int &FrameIndex) const { 161 return 0; 162 } 163 164 /// isStoreToStackSlot - If the specified machine instruction is a direct 165 /// store to a stack slot, return the virtual or physical register number of 166 /// the source reg along with the FrameIndex of the loaded stack slot. If 167 /// not, return 0. This predicate must return 0 if the instruction has 168 /// any side effects other than storing to the stack slot. 169 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 170 int &FrameIndex) const { 171 return 0; 172 } 173 174 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 175 /// stack locations as well. This uses a heuristic so it isn't 176 /// reliable for correctness. 177 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 178 int &FrameIndex) const { 179 return 0; 180 } 181 182 /// hasStoreToStackSlot - If the specified machine instruction has a 183 /// store to a stack slot, return true along with the FrameIndex of 184 /// the loaded stack slot and the machine mem operand containing the 185 /// reference. If not, return false. Unlike isStoreToStackSlot, 186 /// this returns true for any instructions that stores to the 187 /// stack. This is just a hint, as some cases may be missed. 188 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 189 const MachineMemOperand *&MMO, 190 int &FrameIndex) const { 191 return 0; 192 } 193 194 /// reMaterialize - Re-issue the specified 'original' instruction at the 195 /// specific location targeting a new destination register. 196 virtual void reMaterialize(MachineBasicBlock &MBB, 197 MachineBasicBlock::iterator MI, 198 unsigned DestReg, unsigned SubIdx, 199 const MachineInstr *Orig, 200 const TargetRegisterInfo *TRI) const = 0; 201 202 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 203 /// MachineFunction::CloneMachineInstr(), but the target may update operands 204 /// that are required to be unique. 205 /// 206 /// The instruction must be duplicable as indicated by isNotDuplicable(). 207 virtual MachineInstr *duplicate(MachineInstr *Orig, 208 MachineFunction &MF) const = 0; 209 210 /// convertToThreeAddress - This method must be implemented by targets that 211 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 212 /// may be able to convert a two-address instruction into one or more true 213 /// three-address instructions on demand. This allows the X86 target (for 214 /// example) to convert ADD and SHL instructions into LEA instructions if they 215 /// would require register copies due to two-addressness. 216 /// 217 /// This method returns a null pointer if the transformation cannot be 218 /// performed, otherwise it returns the last new instruction. 219 /// 220 virtual MachineInstr * 221 convertToThreeAddress(MachineFunction::iterator &MFI, 222 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 223 return 0; 224 } 225 226 /// commuteInstruction - If a target has any instructions that are commutable, 227 /// but require converting to a different instruction or making non-trivial 228 /// changes to commute them, this method can overloaded to do this. The 229 /// default implementation of this method simply swaps the first two operands 230 /// of MI and returns it. 231 /// 232 /// If a target wants to make more aggressive changes, they can construct and 233 /// return a new machine instruction. If an instruction cannot commute, it 234 /// can also return null. 235 /// 236 /// If NewMI is true, then a new machine instruction must be created. 237 /// 238 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 239 bool NewMI = false) const = 0; 240 241 /// findCommutedOpIndices - If specified MI is commutable, return the two 242 /// operand indices that would swap value. Return true if the instruction 243 /// is not in a form which this routine understands. 244 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 245 unsigned &SrcOpIdx2) const = 0; 246 247 /// produceSameValue - Return true if two machine instructions would produce 248 /// identical values. By default, this is only true when the two instructions 249 /// are deemed identical except for defs. 250 virtual bool produceSameValue(const MachineInstr *MI0, 251 const MachineInstr *MI1) const = 0; 252 253 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 254 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 255 /// implemented for a target). Upon success, this returns false and returns 256 /// with the following information in various cases: 257 /// 258 /// 1. If this block ends with no branches (it just falls through to its succ) 259 /// just return false, leaving TBB/FBB null. 260 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 261 /// the destination block. 262 /// 3. If this block ends with a conditional branch and it falls through to a 263 /// successor block, it sets TBB to be the branch destination block and a 264 /// list of operands that evaluate the condition. These operands can be 265 /// passed to other TargetInstrInfo methods to create new branches. 266 /// 4. If this block ends with a conditional branch followed by an 267 /// unconditional branch, it returns the 'true' destination in TBB, the 268 /// 'false' destination in FBB, and a list of operands that evaluate the 269 /// condition. These operands can be passed to other TargetInstrInfo 270 /// methods to create new branches. 271 /// 272 /// Note that RemoveBranch and InsertBranch must be implemented to support 273 /// cases where this method returns success. 274 /// 275 /// If AllowModify is true, then this routine is allowed to modify the basic 276 /// block (e.g. delete instructions after the unconditional branch). 277 /// 278 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 279 MachineBasicBlock *&FBB, 280 SmallVectorImpl<MachineOperand> &Cond, 281 bool AllowModify = false) const { 282 return true; 283 } 284 285 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 286 /// This is only invoked in cases where AnalyzeBranch returns success. It 287 /// returns the number of instructions that were removed. 288 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 289 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 290 return 0; 291 } 292 293 /// InsertBranch - Insert branch code into the end of the specified 294 /// MachineBasicBlock. The operands to this method are the same as those 295 /// returned by AnalyzeBranch. This is only invoked in cases where 296 /// AnalyzeBranch returns success. It returns the number of instructions 297 /// inserted. 298 /// 299 /// It is also invoked by tail merging to add unconditional branches in 300 /// cases where AnalyzeBranch doesn't apply because there was no original 301 /// branch to analyze. At least this much must be implemented, else tail 302 /// merging needs to be disabled. 303 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 304 MachineBasicBlock *FBB, 305 const SmallVectorImpl<MachineOperand> &Cond) const { 306 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 307 return 0; 308 } 309 310 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 311 /// returns false if the target does not how to copy between the specified 312 /// registers. 313 virtual bool copyRegToReg(MachineBasicBlock &MBB, 314 MachineBasicBlock::iterator MI, 315 unsigned DestReg, unsigned SrcReg, 316 const TargetRegisterClass *DestRC, 317 const TargetRegisterClass *SrcRC) const { 318 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 319 return false; 320 } 321 322 /// storeRegToStackSlot - Store the specified register of the given register 323 /// class to the specified stack frame index. The store instruction is to be 324 /// added to the given machine basic block before the specified machine 325 /// instruction. If isKill is true, the register operand is the last use and 326 /// must be marked kill. 327 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 328 MachineBasicBlock::iterator MI, 329 unsigned SrcReg, bool isKill, int FrameIndex, 330 const TargetRegisterClass *RC) const { 331 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 332 } 333 334 /// loadRegFromStackSlot - Load the specified register of the given register 335 /// class from the specified stack frame index. The load instruction is to be 336 /// added to the given machine basic block before the specified machine 337 /// instruction. 338 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 339 MachineBasicBlock::iterator MI, 340 unsigned DestReg, int FrameIndex, 341 const TargetRegisterClass *RC) const { 342 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 343 } 344 345 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 346 /// saved registers and returns true if it isn't possible / profitable to do 347 /// so by issuing a series of store instructions via 348 /// storeRegToStackSlot(). Returns false otherwise. 349 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 350 MachineBasicBlock::iterator MI, 351 const std::vector<CalleeSavedInfo> &CSI) const { 352 return false; 353 } 354 355 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 356 /// saved registers and returns true if it isn't possible / profitable to do 357 /// so by issuing a series of load instructions via loadRegToStackSlot(). 358 /// Returns false otherwise. 359 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 360 MachineBasicBlock::iterator MI, 361 const std::vector<CalleeSavedInfo> &CSI) const { 362 return false; 363 } 364 365 /// emitFrameIndexDebugValue - Emit a target-dependent form of 366 /// DBG_VALUE encoding the address of a frame index. Addresses would 367 /// normally be lowered the same way as other addresses on the target, 368 /// e.g. in load instructions. For targets that do not support this 369 /// the debug info is simply lost. 370 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 371 unsigned FrameIx, 372 uint64_t Offset, 373 const MDNode *MDPtr, 374 DebugLoc dl) const { 375 return 0; 376 } 377 378 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 379 /// slot into the specified machine instruction for the specified operand(s). 380 /// If this is possible, a new instruction is returned with the specified 381 /// operand folded, otherwise NULL is returned. The client is responsible for 382 /// removing the old instruction and adding the new one in the instruction 383 /// stream. 384 MachineInstr* foldMemoryOperand(MachineFunction &MF, 385 MachineInstr* MI, 386 const SmallVectorImpl<unsigned> &Ops, 387 int FrameIndex) const; 388 389 /// foldMemoryOperand - Same as the previous version except it allows folding 390 /// of any load and store from / to any address, not just from a specific 391 /// stack slot. 392 MachineInstr* foldMemoryOperand(MachineFunction &MF, 393 MachineInstr* MI, 394 const SmallVectorImpl<unsigned> &Ops, 395 MachineInstr* LoadMI) const; 396 397protected: 398 /// foldMemoryOperandImpl - Target-dependent implementation for 399 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 400 /// take care of adding a MachineMemOperand to the newly created instruction. 401 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 402 MachineInstr* MI, 403 const SmallVectorImpl<unsigned> &Ops, 404 int FrameIndex) const { 405 return 0; 406 } 407 408 /// foldMemoryOperandImpl - Target-dependent implementation for 409 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 410 /// take care of adding a MachineMemOperand to the newly created instruction. 411 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 412 MachineInstr* MI, 413 const SmallVectorImpl<unsigned> &Ops, 414 MachineInstr* LoadMI) const { 415 return 0; 416 } 417 418public: 419 /// canFoldMemoryOperand - Returns true for the specified load / store if 420 /// folding is possible. 421 virtual 422 bool canFoldMemoryOperand(const MachineInstr *MI, 423 const SmallVectorImpl<unsigned> &Ops) const { 424 return false; 425 } 426 427 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 428 /// a store or a load and a store into two or more instruction. If this is 429 /// possible, returns true as well as the new instructions by reference. 430 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 431 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 432 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 433 return false; 434 } 435 436 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 437 SmallVectorImpl<SDNode*> &NewNodes) const { 438 return false; 439 } 440 441 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 442 /// instruction after load / store are unfolded from an instruction of the 443 /// specified opcode. It returns zero if the specified unfolding is not 444 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 445 /// index of the operand which will hold the register holding the loaded 446 /// value. 447 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 448 bool UnfoldLoad, bool UnfoldStore, 449 unsigned *LoadRegIndex = 0) const { 450 return 0; 451 } 452 453 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 454 /// to determine if two loads are loading from the same base address. It 455 /// should only return true if the base pointers are the same and the 456 /// only differences between the two addresses are the offset. It also returns 457 /// the offsets by reference. 458 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 459 int64_t &Offset1, int64_t &Offset2) const { 460 return false; 461 } 462 463 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 464 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 465 /// be scheduled togther. On some targets if two loads are loading from 466 /// addresses in the same cache line, it's better if they are scheduled 467 /// together. This function takes two integers that represent the load offsets 468 /// from the common base address. It returns true if it decides it's desirable 469 /// to schedule the two loads together. "NumLoads" is the number of loads that 470 /// have already been scheduled after Load1. 471 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 472 int64_t Offset1, int64_t Offset2, 473 unsigned NumLoads) const { 474 return false; 475 } 476 477 /// ReverseBranchCondition - Reverses the branch condition of the specified 478 /// condition list, returning false on success and true if it cannot be 479 /// reversed. 480 virtual 481 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 482 return true; 483 } 484 485 /// insertNoop - Insert a noop into the instruction stream at the specified 486 /// point. 487 virtual void insertNoop(MachineBasicBlock &MBB, 488 MachineBasicBlock::iterator MI) const; 489 490 /// isPredicated - Returns true if the instruction is already predicated. 491 /// 492 virtual bool isPredicated(const MachineInstr *MI) const { 493 return false; 494 } 495 496 /// isUnpredicatedTerminator - Returns true if the instruction is a 497 /// terminator instruction that has not been predicated. 498 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 499 500 /// PredicateInstruction - Convert the instruction into a predicated 501 /// instruction. It returns true if the operation was successful. 502 virtual 503 bool PredicateInstruction(MachineInstr *MI, 504 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 505 506 /// SubsumesPredicate - Returns true if the first specified predicate 507 /// subsumes the second, e.g. GE subsumes GT. 508 virtual 509 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 510 const SmallVectorImpl<MachineOperand> &Pred2) const { 511 return false; 512 } 513 514 /// DefinesPredicate - If the specified instruction defines any predicate 515 /// or condition code register(s) used for predication, returns true as well 516 /// as the definition predicate(s) by reference. 517 virtual bool DefinesPredicate(MachineInstr *MI, 518 std::vector<MachineOperand> &Pred) const { 519 return false; 520 } 521 522 /// isPredicable - Return true if the specified instruction can be predicated. 523 /// By default, this returns true for every instruction with a 524 /// PredicateOperand. 525 virtual bool isPredicable(MachineInstr *MI) const { 526 return MI->getDesc().isPredicable(); 527 } 528 529 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 530 /// instruction that defines the specified register class. 531 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 532 return true; 533 } 534 535 /// GetInstSize - Returns the size of the specified Instruction. 536 /// 537 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 538 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 539 return 0; 540 } 541 542 /// GetFunctionSizeInBytes - Returns the size of the specified 543 /// MachineFunction. 544 /// 545 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 546 547 /// Measure the specified inline asm to determine an approximation of its 548 /// length. 549 virtual unsigned getInlineAsmLength(const char *Str, 550 const MCAsmInfo &MAI) const; 551}; 552 553/// TargetInstrInfoImpl - This is the default implementation of 554/// TargetInstrInfo, which just provides a couple of default implementations 555/// for various methods. This separated out because it is implemented in 556/// libcodegen, not in libtarget. 557class TargetInstrInfoImpl : public TargetInstrInfo { 558protected: 559 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 560 : TargetInstrInfo(desc, NumOpcodes) {} 561public: 562 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 563 bool NewMI = false) const; 564 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 565 unsigned &SrcOpIdx2) const; 566 virtual bool PredicateInstruction(MachineInstr *MI, 567 const SmallVectorImpl<MachineOperand> &Pred) const; 568 virtual void reMaterialize(MachineBasicBlock &MBB, 569 MachineBasicBlock::iterator MI, 570 unsigned DestReg, unsigned SubReg, 571 const MachineInstr *Orig, 572 const TargetRegisterInfo *TRI) const; 573 virtual MachineInstr *duplicate(MachineInstr *Orig, 574 MachineFunction &MF) const; 575 virtual bool produceSameValue(const MachineInstr *MI0, 576 const MachineInstr *MI1) const; 577 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 578}; 579 580} // End llvm namespace 581 582#endif 583