TargetInstrInfo.h revision 9ada014ec09579a7dd3833f779a1de82bd71bce1
1//===-- llvm/Target/MachineInstrInstrInfo.h - Instruction Infor ---*-C++-*-===// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===----------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "Support/DataTypes.h" 11#include <vector> 12 13class MachineInstrDescriptor; 14class MachineInstr; 15class TargetMachine; 16class Value; 17class Instruction; 18class Constant; 19class Function; 20class MachineCodeForInstruction; 21 22//--------------------------------------------------------------------------- 23// Data types used to define information about a single machine instruction 24//--------------------------------------------------------------------------- 25 26typedef int MachineOpCode; 27typedef unsigned InstrSchedClass; 28 29const MachineOpCode INVALID_MACHINE_OPCODE = -1; 30 31 32//--------------------------------------------------------------------------- 33// struct MachineInstrDescriptor: 34// Predefined information about each machine instruction. 35// Designed to initialized statically. 36// 37// class MachineInstructionInfo 38// Interface to description of machine instructions 39// 40//--------------------------------------------------------------------------- 41 42const unsigned M_NOP_FLAG = 1 << 0; 43const unsigned M_BRANCH_FLAG = 1 << 1; 44const unsigned M_CALL_FLAG = 1 << 2; 45const unsigned M_RET_FLAG = 1 << 3; 46const unsigned M_ARITH_FLAG = 1 << 4; 47const unsigned M_CC_FLAG = 1 << 6; 48const unsigned M_LOGICAL_FLAG = 1 << 6; 49const unsigned M_INT_FLAG = 1 << 7; 50const unsigned M_FLOAT_FLAG = 1 << 8; 51const unsigned M_CONDL_FLAG = 1 << 9; 52const unsigned M_LOAD_FLAG = 1 << 10; 53const unsigned M_PREFETCH_FLAG = 1 << 11; 54const unsigned M_STORE_FLAG = 1 << 12; 55const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 56const unsigned M_PSEUDO_FLAG = 1 << 14; 57// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub 58const unsigned M_2_ADDR_FLAG = 1 << 15; 59 60struct MachineInstrDescriptor { 61 const char * Name; // Assembly language mnemonic for the opcode. 62 int numOperands; // Number of args; -1 if variable #args 63 int resultPos; // Position of the result; -1 if no result 64 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 65 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 66 // smallest -ve value is -(maxImmedConst+1). 67 unsigned numDelaySlots; // Number of delay slots after instruction 68 unsigned latency; // Latency in machine cycles 69 InstrSchedClass schedClass; // enum identifying instr sched class 70 unsigned Flags; // flags identifying machine instr class 71 unsigned TSFlags; // Target Specific Flag values 72 const unsigned *ImplicitUses; // Registers implicitly read by this instr 73 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 74}; 75 76 77class MachineInstrInfo { 78 const MachineInstrDescriptor* desc; // raw array to allow static init'n 79 unsigned descSize; // number of entries in the desc array 80 unsigned numRealOpCodes; // number of non-dummy op codes 81 82 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT 83 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT 84public: 85 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize, 86 unsigned numRealOpCodes); 87 virtual ~MachineInstrInfo(); 88 89 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 90 unsigned getNumTotalOpCodes() const { return descSize; } 91 92 /// get - Return the machine instruction descriptor that corresponds to the 93 /// specified instruction opcode. 94 /// 95 const MachineInstrDescriptor& get(MachineOpCode opCode) const { 96 assert(opCode >= 0 && opCode < (int)descSize); 97 return desc[opCode]; 98 } 99 100 /// print - Print out the specified machine instruction in the appropriate 101 /// target specific assembly language. If this method is not overridden, the 102 /// default implementation uses the crummy machine independant printer. 103 /// 104 virtual void print(const MachineInstr *MI, std::ostream &O, 105 const TargetMachine &TM) const; 106 107 const char *getName(MachineOpCode opCode) const { 108 return get(opCode).Name; 109 } 110 111 int getNumOperands(MachineOpCode opCode) const { 112 return get(opCode).numOperands; 113 } 114 115 int getResultPos(MachineOpCode opCode) const { 116 return get(opCode).resultPos; 117 } 118 119 unsigned getNumDelaySlots(MachineOpCode opCode) const { 120 return get(opCode).numDelaySlots; 121 } 122 123 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 124 return get(opCode).schedClass; 125 } 126 127 // 128 // Query instruction class flags according to the machine-independent 129 // flags listed above. 130 // 131 bool isNop(MachineOpCode opCode) const { 132 return get(opCode).Flags & M_NOP_FLAG; 133 } 134 bool isBranch(MachineOpCode opCode) const { 135 return get(opCode).Flags & M_BRANCH_FLAG; 136 } 137 bool isCall(MachineOpCode opCode) const { 138 return get(opCode).Flags & M_CALL_FLAG; 139 } 140 bool isReturn(MachineOpCode opCode) const { 141 return get(opCode).Flags & M_RET_FLAG; 142 } 143 bool isControlFlow(MachineOpCode opCode) const { 144 return get(opCode).Flags & M_BRANCH_FLAG 145 || get(opCode).Flags & M_CALL_FLAG 146 || get(opCode).Flags & M_RET_FLAG; 147 } 148 bool isArith(MachineOpCode opCode) const { 149 return get(opCode).Flags & M_ARITH_FLAG; 150 } 151 bool isCCInstr(MachineOpCode opCode) const { 152 return get(opCode).Flags & M_CC_FLAG; 153 } 154 bool isLogical(MachineOpCode opCode) const { 155 return get(opCode).Flags & M_LOGICAL_FLAG; 156 } 157 bool isIntInstr(MachineOpCode opCode) const { 158 return get(opCode).Flags & M_INT_FLAG; 159 } 160 bool isFloatInstr(MachineOpCode opCode) const { 161 return get(opCode).Flags & M_FLOAT_FLAG; 162 } 163 bool isConditional(MachineOpCode opCode) const { 164 return get(opCode).Flags & M_CONDL_FLAG; 165 } 166 bool isLoad(MachineOpCode opCode) const { 167 return get(opCode).Flags & M_LOAD_FLAG; 168 } 169 bool isPrefetch(MachineOpCode opCode) const { 170 return get(opCode).Flags & M_PREFETCH_FLAG; 171 } 172 bool isLoadOrPrefetch(MachineOpCode opCode) const { 173 return get(opCode).Flags & M_LOAD_FLAG 174 || get(opCode).Flags & M_PREFETCH_FLAG; 175 } 176 bool isStore(MachineOpCode opCode) const { 177 return get(opCode).Flags & M_STORE_FLAG; 178 } 179 bool isMemoryAccess(MachineOpCode opCode) const { 180 return get(opCode).Flags & M_LOAD_FLAG 181 || get(opCode).Flags & M_PREFETCH_FLAG 182 || get(opCode).Flags & M_STORE_FLAG; 183 } 184 bool isDummyPhiInstr(const MachineOpCode opCode) const { 185 return get(opCode).Flags & M_DUMMY_PHI_FLAG; 186 } 187 bool isPseudoInstr(const MachineOpCode opCode) const { 188 return get(opCode).Flags & M_PSEUDO_FLAG; 189 } 190 bool isTwoAddrInstr(const MachineOpCode opCode) const { 191 return get(opCode).Flags & M_2_ADDR_FLAG; 192 } 193 194 // Check if an instruction can be issued before its operands are ready, 195 // or if a subsequent instruction that uses its result can be issued 196 // before the results are ready. 197 // Default to true since most instructions on many architectures allow this. 198 // 199 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 200 return true; 201 } 202 203 virtual bool hasResultInterlock(MachineOpCode opCode) const { 204 return true; 205 } 206 207 // 208 // Latencies for individual instructions and instruction pairs 209 // 210 virtual int minLatency(MachineOpCode opCode) const { 211 return get(opCode).latency; 212 } 213 214 virtual int maxLatency(MachineOpCode opCode) const { 215 return get(opCode).latency; 216 } 217 218 // 219 // Which operand holds an immediate constant? Returns -1 if none 220 // 221 virtual int getImmedConstantPos(MachineOpCode opCode) const { 222 return -1; // immediate position is machine specific, so say -1 == "none" 223 } 224 225 // Check if the specified constant fits in the immediate field 226 // of this machine instruction 227 // 228 virtual bool constantFitsInImmedField(MachineOpCode opCode, 229 int64_t intValue) const; 230 231 // Return the largest +ve constant that can be held in the IMMMED field 232 // of this machine instruction. 233 // isSignExtended is set to true if the value is sign-extended before use 234 // (this is true for all immediate fields in SPARC instructions). 235 // Return 0 if the instruction has no IMMED field. 236 // 237 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 238 bool &isSignExtended) const { 239 isSignExtended = get(opCode).immedIsSignExtended; 240 return get(opCode).maxImmedConst; 241 } 242 243 //------------------------------------------------------------------------- 244 // Queries about representation of LLVM quantities (e.g., constants) 245 //------------------------------------------------------------------------- 246 247 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 248 /// from memory into a register, i.e., cannot be set bitwise in register and 249 /// cannot use immediate fields of instructions. Note that this only makes 250 /// sense for primitive types. 251 /// 252 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 253 254 // Test if this constant may not fit in the immediate field of the 255 // machine instructions (probably) generated for this instruction. 256 // 257 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 258 const Instruction* I) const { 259 return true; // safe but very conservative 260 } 261 262 //------------------------------------------------------------------------- 263 // Code generation support for creating individual machine instructions 264 //------------------------------------------------------------------------- 265 266 // Get certain common op codes for the current target. this and all the 267 // Create* methods below should be moved to a machine code generation class 268 // 269 virtual MachineOpCode getNOPOpCode() const = 0; 270 271 // Create an instruction sequence to put the constant `val' into 272 // the virtual register `dest'. `val' may be a Constant or a 273 // GlobalValue, viz., the constant address of a global variable or function. 274 // The generated instructions are returned in `mvec'. 275 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 276 // Symbolic constants or constants that must be accessed from memory 277 // are added to the constant pool via MachineFunction::get(F). 278 // 279 virtual void CreateCodeToLoadConst(const TargetMachine& target, 280 Function* F, 281 Value* val, 282 Instruction* dest, 283 std::vector<MachineInstr*>& mvec, 284 MachineCodeForInstruction& mcfi) const=0; 285 286 // Create an instruction sequence to copy an integer value `val' 287 // to a floating point value `dest' by copying to memory and back. 288 // val must be an integral type. dest must be a Float or Double. 289 // The generated instructions are returned in `mvec'. 290 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 291 // Any stack space required is allocated via mcff. 292 // 293 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 294 Function* F, 295 Value* val, 296 Instruction* dest, 297 std::vector<MachineInstr*>& mvec, 298 MachineCodeForInstruction& mcfi)const=0; 299 300 // Similarly, create an instruction sequence to copy an FP value 301 // `val' to an integer value `dest' by copying to memory and back. 302 // The generated instructions are returned in `mvec'. 303 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 304 // Any stack space required is allocated via mcff. 305 // 306 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 307 Function* F, 308 Value* val, 309 Instruction* dest, 310 std::vector<MachineInstr*>& mvec, 311 MachineCodeForInstruction& mcfi)const=0; 312 313 // Create instruction(s) to copy src to dest, for arbitrary types 314 // The generated instructions are returned in `mvec'. 315 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 316 // Any stack space required is allocated via mcff. 317 // 318 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 319 Function* F, 320 Value* src, 321 Instruction* dest, 322 std::vector<MachineInstr*>& mvec, 323 MachineCodeForInstruction& mcfi)const=0; 324 325 // Create instruction sequence to produce a sign-extended register value 326 // from an arbitrary sized value (sized in bits, not bytes). 327 // The generated instructions are appended to `mvec'. 328 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 329 // Any stack space required is allocated via mcff. 330 // 331 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 332 Function* F, 333 Value* srcVal, 334 Value* destVal, 335 unsigned numLowBits, 336 std::vector<MachineInstr*>& mvec, 337 MachineCodeForInstruction& mcfi) const=0; 338 339 // Create instruction sequence to produce a zero-extended register value 340 // from an arbitrary sized value (sized in bits, not bytes). 341 // The generated instructions are appended to `mvec'. 342 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 343 // Any stack space required is allocated via mcff. 344 // 345 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 346 Function* F, 347 Value* srcVal, 348 Value* destVal, 349 unsigned srcSizeInBits, 350 std::vector<MachineInstr*>& mvec, 351 MachineCodeForInstruction& mcfi) const=0; 352}; 353 354#endif 355