TargetInstrInfo.h revision a70dca156fa76d452f54829b5c5f962ddfd94ef2
1c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)// 3c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)// The LLVM Compiler Infrastructure 4c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)// 5c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 6c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)// License. See LICENSE.TXT for details. 790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// 890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)//===----------------------------------------------------------------------===// 990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// 1090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)// This file describes the target machine instruction set to the code generator. 114e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)// 1290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)//===----------------------------------------------------------------------===// 1390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 1490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles)#define LLVM_TARGET_TARGETINSTRINFO_H 1690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 1790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/Target/TargetInstrDesc.h" 1890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/CodeGen/MachineFunction.h" 19c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 2090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)namespace llvm { 2190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 2290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)class MCAsmInfo; 2390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)class TargetRegisterClass; 2490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)class TargetRegisterInfo; 2590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)class LiveVariables; 2690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)class CalleeSavedInfo; 2790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)class SDNode; 2890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)class SelectionDAG; 2990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 3090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)template<class T> class SmallVectorImpl; 3190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 3290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 3390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)//--------------------------------------------------------------------------- 3490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)/// 354e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)/// TargetInstrInfo - Interface to description of machine instruction set 367d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles)/// 37c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)class TargetInstrInfo { 38c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 39c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) unsigned NumOpcodes; // Number of entries in the desc array 40c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 414e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 42c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 43c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)public: 44c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 45c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) virtual ~TargetInstrInfo(); 46c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 47c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) // Invariant opcodes: All instruction sets have these as their low opcodes. 48c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) enum { 49c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) PHI = 0, 50c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) INLINEASM = 1, 51c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DBG_LABEL = 2, 52c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) EH_LABEL = 3, 5390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) GC_LABEL = 4, 5490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 5590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// KILL - This instruction is a noop that is used only to adjust the liveness 5690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// of registers. This can be useful when dealing with sub-registers. 5790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) KILL = 5, 5890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 5990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// EXTRACT_SUBREG - This instruction takes two operands: a register 6090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// that has subregisters, and a subregister index. It returns the 6190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// extracted subregister value. This is commonly used to implement 6290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// truncation operations on target architectures which support it. 6390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) EXTRACT_SUBREG = 6, 645d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 655d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// INSERT_SUBREG - This instruction takes three operands: a register 6690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// that has subregisters, a register providing an insert value, and a 6790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// subregister index. It returns the value of the first register with 685d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// the value of the second register inserted. The first register is 695d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// often defined by an IMPLICIT_DEF, as is commonly used to implement 7090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// anyext operations on target architectures which support it. 7190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) INSERT_SUBREG = 7, 7290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 7390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 7490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) IMPLICIT_DEF = 8, 7590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 7690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 7790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// that the first operand is an immediate integer constant. This constant 7890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// is often zero, as is commonly used to implement zext operations on 7990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// target architectures which support it, such as with x86-64 (with 80ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch /// zext from i32 to i64 via implicit zero-extension). 81ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch SUBREG_TO_REG = 9, 8290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 83868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 84ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch /// register-to-register copy into a specific register class. This is only 8590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// used between instruction selection and MachineInstr creation, before 8690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// virtual registers have been created for all the instructions, and it's 8790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// only needed in cases where the register classes implied by the 8890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// instructions are insufficient. The actual MachineInstrs to perform 8990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 9090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) COPY_TO_REGCLASS = 10 9190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) }; 9290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 9390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) unsigned getNumOpcodes() const { return NumOpcodes; } 9490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 9590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// get - Return the machine instruction descriptor that corresponds to the 9690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// specified instruction opcode. 9790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// 9890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const TargetInstrDesc &get(unsigned Opcode) const { 9990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) assert(Opcode < NumOpcodes && "Invalid opcode!"); 1005d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return Descriptors[Opcode]; 1015d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 1025d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1035d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// isTriviallyReMaterializable - Return true if the instruction is trivially 1045d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// rematerializable, meaning it has no side effects and requires no operands 10590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// that aren't always available. 10690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) bool isTriviallyReMaterializable(const MachineInstr *MI, 10790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) AliasAnalysis *AA = 0) const { 10890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return MI->getOpcode() == IMPLICIT_DEF || 10990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) (MI->getDesc().isRematerializable() && 11090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) (isReallyTriviallyReMaterializable(MI) || 11190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) isReallyTriviallyReMaterializableGeneric(MI, AA))); 11290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 11390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 11490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)protected: 11590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// isReallyTriviallyReMaterializable - For instructions with opcodes for 11690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 11790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// specify whether the instruction is actually trivially rematerializable, 11890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// taking into consideration its operands. This predicate must return false 11990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// if the instruction has any side effects other than producing a value, or 12090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// if it requres any address registers that are not always available. 12190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 122a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) return false; 12390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 12490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 12590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)private: 126ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 127ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch /// for which the M_REMATERIALIZABLE flag is set and the target hook 12890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// isReallyTriviallyReMaterializable returns false, this function does 129868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// target-independent tests to determine if the instruction is really 130ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch /// trivially rematerializable. 13190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 13290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) AliasAnalysis *AA) const; 13390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 13490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)public: 13590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// Return true if the instruction is a register to register move and return 13690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// the source and dest operands and their sub-register indices by reference. 13790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual bool isMoveInstr(const MachineInstr& MI, 13890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) unsigned& SrcReg, unsigned& DstReg, 13990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 14090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return false; 1415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 14290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 14390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// isLoadFromStackSlot - If the specified machine instruction is a direct 14490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// load from a stack slot, return the virtual or physical register number of 1455d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// the destination along with the FrameIndex of the loaded stack slot. If 1465d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// not, return 0. This predicate must return 0 if the instruction has 1475d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// any side effects other than loading from the stack slot. 14890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 14990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) int &FrameIndex) const { 15090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return 0; 15190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 15290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 153a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// isStoreToStackSlot - If the specified machine instruction is a direct 15490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// store to a stack slot, return the virtual or physical register number of 15590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// the source reg along with the FrameIndex of the loaded stack slot. If 15690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// not, return 0. This predicate must return 0 if the instruction has 157ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch /// any side effects other than storing to the stack slot. 158ca12bfac764ba476d6cd062bf1dde12cc64c3f40Ben Murdoch virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 15990dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) int &FrameIndex) const { 160c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return 0; 16190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 162c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 1637d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) /// reMaterialize - Re-issue the specified 'original' instruction at the 1645d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// specific location targeting a new destination register. 1655d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual void reMaterialize(MachineBasicBlock &MBB, 1665d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) MachineBasicBlock::iterator MI, 1675d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) unsigned DestReg, unsigned SubIdx, 1685d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) const MachineInstr *Orig) const = 0; 1695d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1705d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// convertToThreeAddress - This method must be implemented by targets that 1715d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1725d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// may be able to convert a two-address instruction into one or more true 1735d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// three-address instructions on demand. This allows the X86 target (for 1745d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// example) to convert ADD and SHL instructions into LEA instructions if they 1755d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// would require register copies due to two-addressness. 1765d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 1775d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// This method returns a null pointer if the transformation cannot be 1785d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// performed, otherwise it returns the last new instruction. 1795d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 1805d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual MachineInstr * 1815d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) convertToThreeAddress(MachineFunction::iterator &MFI, 1825d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 1835d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return 0; 1845d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 1855d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1865d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// commuteInstruction - If a target has any instructions that are commutable, 1875d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// but require converting to a different instruction or making non-trivial 1885d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// changes to commute them, this method can overloaded to do this. The 1895d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// default implementation of this method simply swaps the first two operands 1905d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// of MI and returns it. 1915d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 1925d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// If a target wants to make more aggressive changes, they can construct and 1935d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// return a new machine instruction. If an instruction cannot commute, it 1945d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// can also return null. 1955d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 1965d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// If NewMI is true, then a new machine instruction must be created. 1975d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 1985d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual MachineInstr *commuteInstruction(MachineInstr *MI, 1995d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) bool NewMI = false) const = 0; 2005d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 2015d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// findCommutedOpIndices - If specified MI is commutable, return the two 2025d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// operand indices that would swap value. Return true if the instruction 2035d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// is not in a form which this routine understands. 2045d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 2055d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) unsigned &SrcOpIdx2) const = 0; 2065d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 2075d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 2085d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 2095d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// implemented for a target). Upon success, this returns false and returns 2105d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// with the following information in various cases: 211 /// 212 /// 1. If this block ends with no branches (it just falls through to its succ) 213 /// just return false, leaving TBB/FBB null. 214 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 215 /// the destination block. 216 /// 3. If this block ends with an conditional branch and it falls through to 217 /// a successor block, it sets TBB to be the branch destination block and 218 /// a list of operands that evaluate the condition. These 219 /// operands can be passed to other TargetInstrInfo methods to create new 220 /// branches. 221 /// 4. If this block ends with a conditional branch followed by an 222 /// unconditional branch, it returns the 'true' destination in TBB, the 223 /// 'false' destination in FBB, and a list of operands that evaluate the 224 /// condition. These operands can be passed to other TargetInstrInfo 225 /// methods to create new branches. 226 /// 227 /// Note that RemoveBranch and InsertBranch must be implemented to support 228 /// cases where this method returns success. 229 /// 230 /// If AllowModify is true, then this routine is allowed to modify the basic 231 /// block (e.g. delete instructions after the unconditional branch). 232 /// 233 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 234 MachineBasicBlock *&FBB, 235 SmallVectorImpl<MachineOperand> &Cond, 236 bool AllowModify = false) const { 237 return true; 238 } 239 240 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 241 /// This is only invoked in cases where AnalyzeBranch returns success. It 242 /// returns the number of instructions that were removed. 243 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 244 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 245 return 0; 246 } 247 248 /// InsertBranch - Insert branch code into the end of the specified 249 /// MachineBasicBlock. The operands to this method are the same as those 250 /// returned by AnalyzeBranch. This is only invoked in cases where 251 /// AnalyzeBranch returns success. It returns the number of instructions 252 /// inserted. 253 /// 254 /// It is also invoked by tail merging to add unconditional branches in 255 /// cases where AnalyzeBranch doesn't apply because there was no original 256 /// branch to analyze. At least this much must be implemented, else tail 257 /// merging needs to be disabled. 258 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 259 MachineBasicBlock *FBB, 260 const SmallVectorImpl<MachineOperand> &Cond) const { 261 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 262 return 0; 263 } 264 265 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 266 /// returns false if the target does not how to copy between the specified 267 /// registers. 268 virtual bool copyRegToReg(MachineBasicBlock &MBB, 269 MachineBasicBlock::iterator MI, 270 unsigned DestReg, unsigned SrcReg, 271 const TargetRegisterClass *DestRC, 272 const TargetRegisterClass *SrcRC) const { 273 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 274 return false; 275 } 276 277 /// storeRegToStackSlot - Store the specified register of the given register 278 /// class to the specified stack frame index. The store instruction is to be 279 /// added to the given machine basic block before the specified machine 280 /// instruction. If isKill is true, the register operand is the last use and 281 /// must be marked kill. 282 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 283 MachineBasicBlock::iterator MI, 284 unsigned SrcReg, bool isKill, int FrameIndex, 285 const TargetRegisterClass *RC) const { 286 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 287 } 288 289 /// loadRegFromStackSlot - Load the specified register of the given register 290 /// class from the specified stack frame index. The load instruction is to be 291 /// added to the given machine basic block before the specified machine 292 /// instruction. 293 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 294 MachineBasicBlock::iterator MI, 295 unsigned DestReg, int FrameIndex, 296 const TargetRegisterClass *RC) const { 297 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 298 } 299 300 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 301 /// saved registers and returns true if it isn't possible / profitable to do 302 /// so by issuing a series of store instructions via 303 /// storeRegToStackSlot(). Returns false otherwise. 304 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 305 MachineBasicBlock::iterator MI, 306 const std::vector<CalleeSavedInfo> &CSI) const { 307 return false; 308 } 309 310 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 311 /// saved registers and returns true if it isn't possible / profitable to do 312 /// so by issuing a series of load instructions via loadRegToStackSlot(). 313 /// Returns false otherwise. 314 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 315 MachineBasicBlock::iterator MI, 316 const std::vector<CalleeSavedInfo> &CSI) const { 317 return false; 318 } 319 320 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 321 /// slot into the specified machine instruction for the specified operand(s). 322 /// If this is possible, a new instruction is returned with the specified 323 /// operand folded, otherwise NULL is returned. The client is responsible for 324 /// removing the old instruction and adding the new one in the instruction 325 /// stream. 326 MachineInstr* foldMemoryOperand(MachineFunction &MF, 327 MachineInstr* MI, 328 const SmallVectorImpl<unsigned> &Ops, 329 int FrameIndex) const; 330 331 /// foldMemoryOperand - Same as the previous version except it allows folding 332 /// of any load and store from / to any address, not just from a specific 333 /// stack slot. 334 MachineInstr* foldMemoryOperand(MachineFunction &MF, 335 MachineInstr* MI, 336 const SmallVectorImpl<unsigned> &Ops, 337 MachineInstr* LoadMI) const; 338 339protected: 340 /// foldMemoryOperandImpl - Target-dependent implementation for 341 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 342 /// take care of adding a MachineMemOperand to the newly created instruction. 343 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 344 MachineInstr* MI, 345 const SmallVectorImpl<unsigned> &Ops, 346 int FrameIndex) const { 347 return 0; 348 } 349 350 /// foldMemoryOperandImpl - Target-dependent implementation for 351 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 352 /// take care of adding a MachineMemOperand to the newly created instruction. 353 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 354 MachineInstr* MI, 355 const SmallVectorImpl<unsigned> &Ops, 356 MachineInstr* LoadMI) const { 357 return 0; 358 } 359 360public: 361 /// canFoldMemoryOperand - Returns true for the specified load / store if 362 /// folding is possible. 363 virtual 364 bool canFoldMemoryOperand(const MachineInstr *MI, 365 const SmallVectorImpl<unsigned> &Ops) const { 366 return false; 367 } 368 369 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 370 /// a store or a load and a store into two or more instruction. If this is 371 /// possible, returns true as well as the new instructions by reference. 372 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 373 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 374 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 375 return false; 376 } 377 378 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 379 SmallVectorImpl<SDNode*> &NewNodes) const { 380 return false; 381 } 382 383 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 384 /// instruction after load / store are unfolded from an instruction of the 385 /// specified opcode. It returns zero if the specified unfolding is not 386 /// possible. 387 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 388 bool UnfoldLoad, bool UnfoldStore) const { 389 return 0; 390 } 391 392 /// BlockHasNoFallThrough - Return true if the specified block does not 393 /// fall-through into its successor block. This is primarily used when a 394 /// branch is unanalyzable. It is useful for things like unconditional 395 /// indirect branches (jump tables). 396 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 397 return false; 398 } 399 400 /// ReverseBranchCondition - Reverses the branch condition of the specified 401 /// condition list, returning false on success and true if it cannot be 402 /// reversed. 403 virtual 404 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 405 return true; 406 } 407 408 /// insertNoop - Insert a noop into the instruction stream at the specified 409 /// point. 410 virtual void insertNoop(MachineBasicBlock &MBB, 411 MachineBasicBlock::iterator MI) const; 412 413 /// isPredicated - Returns true if the instruction is already predicated. 414 /// 415 virtual bool isPredicated(const MachineInstr *MI) const { 416 return false; 417 } 418 419 /// isUnpredicatedTerminator - Returns true if the instruction is a 420 /// terminator instruction that has not been predicated. 421 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 422 423 /// PredicateInstruction - Convert the instruction into a predicated 424 /// instruction. It returns true if the operation was successful. 425 virtual 426 bool PredicateInstruction(MachineInstr *MI, 427 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 428 429 /// SubsumesPredicate - Returns true if the first specified predicate 430 /// subsumes the second, e.g. GE subsumes GT. 431 virtual 432 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 433 const SmallVectorImpl<MachineOperand> &Pred2) const { 434 return false; 435 } 436 437 /// DefinesPredicate - If the specified instruction defines any predicate 438 /// or condition code register(s) used for predication, returns true as well 439 /// as the definition predicate(s) by reference. 440 virtual bool DefinesPredicate(MachineInstr *MI, 441 std::vector<MachineOperand> &Pred) const { 442 return false; 443 } 444 445 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 446 /// instruction that defines the specified register class. 447 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 448 return true; 449 } 450 451 /// isDeadInstruction - Return true if the instruction is considered dead. 452 /// This allows some late codegen passes to delete them. 453 virtual bool isDeadInstruction(const MachineInstr *MI) const = 0; 454 455 /// GetInstSize - Returns the size of the specified Instruction. 456 /// 457 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 458 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 459 return 0; 460 } 461 462 /// GetFunctionSizeInBytes - Returns the size of the specified 463 /// MachineFunction. 464 /// 465 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 466 467 /// Measure the specified inline asm to determine an approximation of its 468 /// length. 469 virtual unsigned getInlineAsmLength(const char *Str, 470 const MCAsmInfo &MAI) const; 471}; 472 473/// TargetInstrInfoImpl - This is the default implementation of 474/// TargetInstrInfo, which just provides a couple of default implementations 475/// for various methods. This separated out because it is implemented in 476/// libcodegen, not in libtarget. 477class TargetInstrInfoImpl : public TargetInstrInfo { 478protected: 479 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 480 : TargetInstrInfo(desc, NumOpcodes) {} 481public: 482 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 483 bool NewMI = false) const; 484 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 485 unsigned &SrcOpIdx2) const; 486 virtual bool PredicateInstruction(MachineInstr *MI, 487 const SmallVectorImpl<MachineOperand> &Pred) const; 488 virtual void reMaterialize(MachineBasicBlock &MBB, 489 MachineBasicBlock::iterator MI, 490 unsigned DestReg, unsigned SubReg, 491 const MachineInstr *Orig) const; 492 virtual bool isDeadInstruction(const MachineInstr *MI) const; 493 494 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 495}; 496 497} // End llvm namespace 498 499#endif 500