TargetInstrInfo.h revision c188b733babbcdb0ff51613d0bb133e0496963b6
1//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===---------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "Support/NonCopyable.h" 11#include "Support/DataTypes.h" 12#include "llvm/Constant.h" 13#include "llvm/DerivedTypes.h" 14 15class MachineInstrDescriptor; 16class MachineInstr; 17class TargetMachine; 18class Value; 19class Instruction; 20class Function; 21class MachineCodeForInstruction; 22 23//--------------------------------------------------------------------------- 24// Data types used to define information about a single machine instruction 25//--------------------------------------------------------------------------- 26 27typedef int MachineOpCode; 28typedef int OpCodeMask; 29typedef unsigned InstrSchedClass; 30 31const MachineOpCode INVALID_MACHINE_OPCODE = -1; 32 33 34// Global variable holding an array of descriptors for machine instructions. 35// The actual object needs to be created separately for each target machine. 36// This variable is initialized and reset by class MachineInstrInfo. 37// 38// FIXME: This should be a property of the target so that more than one target 39// at a time can be active... 40// 41extern const MachineInstrDescriptor *TargetInstrDescriptors; 42 43 44//--------------------------------------------------------------------------- 45// struct MachineInstrDescriptor: 46// Predefined information about each machine instruction. 47// Designed to initialized statically. 48// 49// class MachineInstructionInfo 50// Interface to description of machine instructions 51// 52//--------------------------------------------------------------------------- 53 54 55const unsigned int M_NOP_FLAG = 1 << 0; 56const unsigned int M_BRANCH_FLAG = 1 << 1; 57const unsigned int M_CALL_FLAG = 1 << 2; 58const unsigned int M_RET_FLAG = 1 << 3; 59const unsigned int M_ARITH_FLAG = 1 << 4; 60const unsigned int M_CC_FLAG = 1 << 6; 61const unsigned int M_LOGICAL_FLAG = 1 << 6; 62const unsigned int M_INT_FLAG = 1 << 7; 63const unsigned int M_FLOAT_FLAG = 1 << 8; 64const unsigned int M_CONDL_FLAG = 1 << 9; 65const unsigned int M_LOAD_FLAG = 1 << 10; 66const unsigned int M_PREFETCH_FLAG = 1 << 11; 67const unsigned int M_STORE_FLAG = 1 << 12; 68const unsigned int M_DUMMY_PHI_FLAG = 1 << 13; 69const unsigned int M_PSEUDO_FLAG = 1 << 14; 70 71 72struct MachineInstrDescriptor { 73 std::string opCodeString; // Assembly language mnemonic for the opcode. 74 int numOperands; // Number of args; -1 if variable #args 75 int resultPos; // Position of the result; -1 if no result 76 unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0. 77 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 78 // smallest -ve value is -(maxImmedConst+1). 79 unsigned int numDelaySlots; // Number of delay slots after instruction 80 unsigned int latency; // Latency in machine cycles 81 InstrSchedClass schedClass; // enum identifying instr sched class 82 unsigned int iclass; // flags identifying machine instr class 83}; 84 85 86class MachineInstrInfo : public NonCopyableV { 87public: 88 const TargetMachine& target; 89 90protected: 91 const MachineInstrDescriptor* desc; // raw array to allow static init'n 92 unsigned int descSize; // number of entries in the desc array 93 unsigned int numRealOpCodes; // number of non-dummy op codes 94 95public: 96 MachineInstrInfo(const TargetMachine& tgt, 97 const MachineInstrDescriptor *desc, unsigned descSize, 98 unsigned numRealOpCodes); 99 virtual ~MachineInstrInfo(); 100 101 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 102 unsigned getNumTotalOpCodes() const { return descSize; } 103 104 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const { 105 assert(opCode >= 0 && opCode < (int)descSize); 106 return desc[opCode]; 107 } 108 109 int getNumOperands(MachineOpCode opCode) const { 110 return getDescriptor(opCode).numOperands; 111 } 112 113 int getResultPos(MachineOpCode opCode) const { 114 return getDescriptor(opCode).resultPos; 115 } 116 117 unsigned getNumDelaySlots(MachineOpCode opCode) const { 118 return getDescriptor(opCode).numDelaySlots; 119 } 120 121 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 122 return getDescriptor(opCode).schedClass; 123 } 124 125 // 126 // Query instruction class flags according to the machine-independent 127 // flags listed above. 128 // 129 unsigned int getIClass(MachineOpCode opCode) const { 130 return getDescriptor(opCode).iclass; 131 } 132 bool isNop(MachineOpCode opCode) const { 133 return getDescriptor(opCode).iclass & M_NOP_FLAG; 134 } 135 bool isBranch(MachineOpCode opCode) const { 136 return getDescriptor(opCode).iclass & M_BRANCH_FLAG; 137 } 138 bool isCall(MachineOpCode opCode) const { 139 return getDescriptor(opCode).iclass & M_CALL_FLAG; 140 } 141 bool isReturn(MachineOpCode opCode) const { 142 return getDescriptor(opCode).iclass & M_RET_FLAG; 143 } 144 bool isControlFlow(MachineOpCode opCode) const { 145 return getDescriptor(opCode).iclass & M_BRANCH_FLAG 146 || getDescriptor(opCode).iclass & M_CALL_FLAG 147 || getDescriptor(opCode).iclass & M_RET_FLAG; 148 } 149 bool isArith(MachineOpCode opCode) const { 150 return getDescriptor(opCode).iclass & M_ARITH_FLAG; 151 } 152 bool isCCInstr(MachineOpCode opCode) const { 153 return getDescriptor(opCode).iclass & M_CC_FLAG; 154 } 155 bool isLogical(MachineOpCode opCode) const { 156 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG; 157 } 158 bool isIntInstr(MachineOpCode opCode) const { 159 return getDescriptor(opCode).iclass & M_INT_FLAG; 160 } 161 bool isFloatInstr(MachineOpCode opCode) const { 162 return getDescriptor(opCode).iclass & M_FLOAT_FLAG; 163 } 164 bool isConditional(MachineOpCode opCode) const { 165 return getDescriptor(opCode).iclass & M_CONDL_FLAG; 166 } 167 bool isLoad(MachineOpCode opCode) const { 168 return getDescriptor(opCode).iclass & M_LOAD_FLAG; 169 } 170 bool isPrefetch(MachineOpCode opCode) const { 171 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 172 } 173 bool isLoadOrPrefetch(MachineOpCode opCode) const { 174 return getDescriptor(opCode).iclass & M_LOAD_FLAG 175 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 176 } 177 bool isStore(MachineOpCode opCode) const { 178 return getDescriptor(opCode).iclass & M_STORE_FLAG; 179 } 180 bool isMemoryAccess(MachineOpCode opCode) const { 181 return getDescriptor(opCode).iclass & M_LOAD_FLAG 182 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG 183 || getDescriptor(opCode).iclass & M_STORE_FLAG; 184 } 185 bool isDummyPhiInstr(const MachineOpCode opCode) const { 186 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG; 187 } 188 bool isPseudoInstr(const MachineOpCode opCode) const { 189 return getDescriptor(opCode).iclass & M_PSEUDO_FLAG; 190 } 191 192 // Check if an instruction can be issued before its operands are ready, 193 // or if a subsequent instruction that uses its result can be issued 194 // before the results are ready. 195 // Default to true since most instructions on many architectures allow this. 196 // 197 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 198 return true; 199 } 200 201 virtual bool hasResultInterlock(MachineOpCode opCode) const { 202 return true; 203 } 204 205 // 206 // Latencies for individual instructions and instruction pairs 207 // 208 virtual int minLatency(MachineOpCode opCode) const { 209 return getDescriptor(opCode).latency; 210 } 211 212 virtual int maxLatency(MachineOpCode opCode) const { 213 return getDescriptor(opCode).latency; 214 } 215 216 // 217 // Which operand holds an immediate constant? Returns -1 if none 218 // 219 virtual int getImmedConstantPos(MachineOpCode opCode) const { 220 return -1; // immediate position is machine specific, so say -1 == "none" 221 } 222 223 // Check if the specified constant fits in the immediate field 224 // of this machine instruction 225 // 226 virtual bool constantFitsInImmedField(MachineOpCode opCode, 227 int64_t intValue) const; 228 229 // Return the largest +ve constant that can be held in the IMMMED field 230 // of this machine instruction. 231 // isSignExtended is set to true if the value is sign-extended before use 232 // (this is true for all immediate fields in SPARC instructions). 233 // Return 0 if the instruction has no IMMED field. 234 // 235 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 236 bool &isSignExtended) const { 237 isSignExtended = getDescriptor(opCode).immedIsSignExtended; 238 return getDescriptor(opCode).maxImmedConst; 239 } 240 241 //------------------------------------------------------------------------- 242 // Queries about representation of LLVM quantities (e.g., constants) 243 //------------------------------------------------------------------------- 244 245 // Test if this type of constant must be loaded from memory into 246 // a register, i.e., cannot be set bitwise in register and cannot 247 // use immediate fields of instructions. Note that this only makes 248 // sense for primitive types. 249 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const { 250 assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType())); 251 return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType())); 252 } 253 254 // Test if this constant may not fit in the immediate field of the 255 // machine instructions (probably) generated for this instruction. 256 // 257 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 258 const Instruction* I) const { 259 return true; // safe but very conservative 260 } 261 262 //------------------------------------------------------------------------- 263 // Code generation support for creating individual machine instructions 264 //------------------------------------------------------------------------- 265 266 // Get certain common op codes for the current target. this and all the 267 // Create* methods below should be moved to a machine code generation class 268 // 269 virtual MachineOpCode getNOPOpCode() const = 0; 270 271 // Create an instruction sequence to put the constant `val' into 272 // the virtual register `dest'. `val' may be a Constant or a 273 // GlobalValue, viz., the constant address of a global variable or function. 274 // The generated instructions are returned in `mvec'. 275 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 276 // Symbolic constants or constants that must be accessed from memory 277 // are added to the constant pool via MachineFunction::get(F). 278 // 279 virtual void CreateCodeToLoadConst(const TargetMachine& target, 280 Function* F, 281 Value* val, 282 Instruction* dest, 283 std::vector<MachineInstr*>& mvec, 284 MachineCodeForInstruction& mcfi) const=0; 285 286 // Create an instruction sequence to copy an integer value `val' 287 // to a floating point value `dest' by copying to memory and back. 288 // val must be an integral type. dest must be a Float or Double. 289 // The generated instructions are returned in `mvec'. 290 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 291 // Any stack space required is allocated via mcff. 292 // 293 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 294 Function* F, 295 Value* val, 296 Instruction* dest, 297 std::vector<MachineInstr*>& mvec, 298 MachineCodeForInstruction& mcfi)const=0; 299 300 // Similarly, create an instruction sequence to copy an FP value 301 // `val' to an integer value `dest' by copying to memory and back. 302 // The generated instructions are returned in `mvec'. 303 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 304 // Any stack space required is allocated via mcff. 305 // 306 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 307 Function* F, 308 Value* val, 309 Instruction* dest, 310 std::vector<MachineInstr*>& mvec, 311 MachineCodeForInstruction& mcfi)const=0; 312 313 // Create instruction(s) to copy src to dest, for arbitrary types 314 // The generated instructions are returned in `mvec'. 315 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 316 // Any stack space required is allocated via mcff. 317 // 318 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 319 Function* F, 320 Value* src, 321 Instruction* dest, 322 std::vector<MachineInstr*>& mvec, 323 MachineCodeForInstruction& mcfi)const=0; 324 325 // Create instruction sequence to produce a sign-extended register value 326 // from an arbitrary sized value (sized in bits, not bytes). 327 // The generated instructions are appended to `mvec'. 328 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 329 // Any stack space required is allocated via mcff. 330 // 331 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 332 Function* F, 333 Value* srcVal, 334 Value* destVal, 335 unsigned int numLowBits, 336 std::vector<MachineInstr*>& mvec, 337 MachineCodeForInstruction& mcfi) const=0; 338 339 // Create instruction sequence to produce a zero-extended register value 340 // from an arbitrary sized value (sized in bits, not bytes). 341 // The generated instructions are appended to `mvec'. 342 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 343 // Any stack space required is allocated via mcff. 344 // 345 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 346 Function* F, 347 Value* srcVal, 348 Value* destVal, 349 unsigned int srcSizeInBits, 350 std::vector<MachineInstr*>& mvec, 351 MachineCodeForInstruction& mcfi) const=0; 352}; 353 354#endif 355