TargetInstrInfo.h revision d2035203a0359eedbc1cf4ae77d43176e8455cd4
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class MCAsmInfo; 23class TargetRegisterClass; 24class TargetRegisterInfo; 25class LiveVariables; 26class CalleeSavedInfo; 27class SDNode; 28class SelectionDAG; 29class MachineMemOperand; 30 31template<class T> class SmallVectorImpl; 32 33 34//--------------------------------------------------------------------------- 35/// 36/// TargetInstrInfo - Interface to description of machine instruction set 37/// 38class TargetInstrInfo { 39 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 40 unsigned NumOpcodes; // Number of entries in the desc array 41 42 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 43 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 44public: 45 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 46 virtual ~TargetInstrInfo(); 47 48 // Invariant opcodes: All instruction sets have these as their low opcodes. 49 enum { 50 PHI = 0, 51 INLINEASM = 1, 52 DBG_LABEL = 2, 53 EH_LABEL = 3, 54 GC_LABEL = 4, 55 56 /// KILL - This instruction is a noop that is used only to adjust the liveness 57 /// of registers. This can be useful when dealing with sub-registers. 58 KILL = 5, 59 60 /// EXTRACT_SUBREG - This instruction takes two operands: a register 61 /// that has subregisters, and a subregister index. It returns the 62 /// extracted subregister value. This is commonly used to implement 63 /// truncation operations on target architectures which support it. 64 EXTRACT_SUBREG = 6, 65 66 /// INSERT_SUBREG - This instruction takes three operands: a register 67 /// that has subregisters, a register providing an insert value, and a 68 /// subregister index. It returns the value of the first register with 69 /// the value of the second register inserted. The first register is 70 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 71 /// anyext operations on target architectures which support it. 72 INSERT_SUBREG = 7, 73 74 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 75 IMPLICIT_DEF = 8, 76 77 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 78 /// that the first operand is an immediate integer constant. This constant 79 /// is often zero, as is commonly used to implement zext operations on 80 /// target architectures which support it, such as with x86-64 (with 81 /// zext from i32 to i64 via implicit zero-extension). 82 SUBREG_TO_REG = 9, 83 84 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 85 /// register-to-register copy into a specific register class. This is only 86 /// used between instruction selection and MachineInstr creation, before 87 /// virtual registers have been created for all the instructions, and it's 88 /// only needed in cases where the register classes implied by the 89 /// instructions are insufficient. The actual MachineInstrs to perform 90 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 91 COPY_TO_REGCLASS = 10, 92 93 // DEBUG_VALUE - a mapping of the llvm.dbg.value intrinsic 94 DEBUG_VALUE = 11, 95 96 // DEBUG_DECLARE - a mapping of the llvm.dbg.declare intrinsic 97 DEBUG_DECLARE = 12 98 }; 99 100 unsigned getNumOpcodes() const { return NumOpcodes; } 101 102 /// get - Return the machine instruction descriptor that corresponds to the 103 /// specified instruction opcode. 104 /// 105 const TargetInstrDesc &get(unsigned Opcode) const { 106 assert(Opcode < NumOpcodes && "Invalid opcode!"); 107 return Descriptors[Opcode]; 108 } 109 110 /// isTriviallyReMaterializable - Return true if the instruction is trivially 111 /// rematerializable, meaning it has no side effects and requires no operands 112 /// that aren't always available. 113 bool isTriviallyReMaterializable(const MachineInstr *MI, 114 AliasAnalysis *AA = 0) const { 115 return MI->getOpcode() == IMPLICIT_DEF || 116 (MI->getDesc().isRematerializable() && 117 (isReallyTriviallyReMaterializable(MI, AA) || 118 isReallyTriviallyReMaterializableGeneric(MI, AA))); 119 } 120 121protected: 122 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 123 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 124 /// specify whether the instruction is actually trivially rematerializable, 125 /// taking into consideration its operands. This predicate must return false 126 /// if the instruction has any side effects other than producing a value, or 127 /// if it requres any address registers that are not always available. 128 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 129 AliasAnalysis *AA) const { 130 return false; 131 } 132 133private: 134 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 135 /// for which the M_REMATERIALIZABLE flag is set and the target hook 136 /// isReallyTriviallyReMaterializable returns false, this function does 137 /// target-independent tests to determine if the instruction is really 138 /// trivially rematerializable. 139 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 140 AliasAnalysis *AA) const; 141 142public: 143 /// isMoveInstr - Return true if the instruction is a register to register 144 /// move and return the source and dest operands and their sub-register 145 /// indices by reference. 146 virtual bool isMoveInstr(const MachineInstr& MI, 147 unsigned& SrcReg, unsigned& DstReg, 148 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 149 return false; 150 } 151 152 /// isIdentityCopy - Return true if the instruction is a copy (or 153 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 154 /// destination registers are the same. 155 bool isIdentityCopy(const MachineInstr &MI) const { 156 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 157 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 158 SrcReg == DstReg) 159 return true; 160 161 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && 162 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 163 return true; 164 165 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || 166 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && 167 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 168 return true; 169 return false; 170 } 171 172 /// isLoadFromStackSlot - If the specified machine instruction is a direct 173 /// load from a stack slot, return the virtual or physical register number of 174 /// the destination along with the FrameIndex of the loaded stack slot. If 175 /// not, return 0. This predicate must return 0 if the instruction has 176 /// any side effects other than loading from the stack slot. 177 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 178 int &FrameIndex) const { 179 return 0; 180 } 181 182 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 183 /// stack locations as well. This uses a heuristic so it isn't 184 /// reliable for correctness. 185 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 186 int &FrameIndex) const { 187 return 0; 188 } 189 190 /// hasLoadFromStackSlot - If the specified machine instruction has 191 /// a load from a stack slot, return true along with the FrameIndex 192 /// of the loaded stack slot and the machine mem operand containing 193 /// the reference. If not, return false. Unlike 194 /// isLoadFromStackSlot, this returns true for any instructions that 195 /// loads from the stack. This is just a hint, as some cases may be 196 /// missed. 197 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 198 const MachineMemOperand *&MMO, 199 int &FrameIndex) const { 200 return 0; 201 } 202 203 /// isStoreToStackSlot - If the specified machine instruction is a direct 204 /// store to a stack slot, return the virtual or physical register number of 205 /// the source reg along with the FrameIndex of the loaded stack slot. If 206 /// not, return 0. This predicate must return 0 if the instruction has 207 /// any side effects other than storing to the stack slot. 208 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 209 int &FrameIndex) const { 210 return 0; 211 } 212 213 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 214 /// stack locations as well. This uses a heuristic so it isn't 215 /// reliable for correctness. 216 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 217 int &FrameIndex) const { 218 return 0; 219 } 220 221 /// hasStoreToStackSlot - If the specified machine instruction has a 222 /// store to a stack slot, return true along with the FrameIndex of 223 /// the loaded stack slot and the machine mem operand containing the 224 /// reference. If not, return false. Unlike isStoreToStackSlot, 225 /// this returns true for any instructions that loads from the 226 /// stack. This is just a hint, as some cases may be missed. 227 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 228 const MachineMemOperand *&MMO, 229 int &FrameIndex) const { 230 return 0; 231 } 232 233 /// reMaterialize - Re-issue the specified 'original' instruction at the 234 /// specific location targeting a new destination register. 235 virtual void reMaterialize(MachineBasicBlock &MBB, 236 MachineBasicBlock::iterator MI, 237 unsigned DestReg, unsigned SubIdx, 238 const MachineInstr *Orig, 239 const TargetRegisterInfo *TRI) const = 0; 240 241 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 242 /// MachineFunction::CloneMachineInstr(), but the target may update operands 243 /// that are required to be unique. 244 /// 245 /// The instruction must be duplicable as indicated by isNotDuplicable(). 246 virtual MachineInstr *duplicate(MachineInstr *Orig, 247 MachineFunction &MF) const = 0; 248 249 /// convertToThreeAddress - This method must be implemented by targets that 250 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 251 /// may be able to convert a two-address instruction into one or more true 252 /// three-address instructions on demand. This allows the X86 target (for 253 /// example) to convert ADD and SHL instructions into LEA instructions if they 254 /// would require register copies due to two-addressness. 255 /// 256 /// This method returns a null pointer if the transformation cannot be 257 /// performed, otherwise it returns the last new instruction. 258 /// 259 virtual MachineInstr * 260 convertToThreeAddress(MachineFunction::iterator &MFI, 261 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 262 return 0; 263 } 264 265 /// commuteInstruction - If a target has any instructions that are commutable, 266 /// but require converting to a different instruction or making non-trivial 267 /// changes to commute them, this method can overloaded to do this. The 268 /// default implementation of this method simply swaps the first two operands 269 /// of MI and returns it. 270 /// 271 /// If a target wants to make more aggressive changes, they can construct and 272 /// return a new machine instruction. If an instruction cannot commute, it 273 /// can also return null. 274 /// 275 /// If NewMI is true, then a new machine instruction must be created. 276 /// 277 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 278 bool NewMI = false) const = 0; 279 280 /// findCommutedOpIndices - If specified MI is commutable, return the two 281 /// operand indices that would swap value. Return true if the instruction 282 /// is not in a form which this routine understands. 283 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 284 unsigned &SrcOpIdx2) const = 0; 285 286 /// isIdentical - Return true if two instructions are identical. This differs 287 /// from MachineInstr::isIdenticalTo() in that it does not require the 288 /// virtual destination registers to be the same. This is used by MachineLICM 289 /// and other MI passes to perform CSE. 290 virtual bool isIdentical(const MachineInstr *MI, 291 const MachineInstr *Other, 292 const MachineRegisterInfo *MRI) const = 0; 293 294 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 295 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 296 /// implemented for a target). Upon success, this returns false and returns 297 /// with the following information in various cases: 298 /// 299 /// 1. If this block ends with no branches (it just falls through to its succ) 300 /// just return false, leaving TBB/FBB null. 301 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 302 /// the destination block. 303 /// 3. If this block ends with a conditional branch and it falls through to a 304 /// successor block, it sets TBB to be the branch destination block and a 305 /// list of operands that evaluate the condition. These operands can be 306 /// passed to other TargetInstrInfo methods to create new branches. 307 /// 4. If this block ends with a conditional branch followed by an 308 /// unconditional branch, it returns the 'true' destination in TBB, the 309 /// 'false' destination in FBB, and a list of operands that evaluate the 310 /// condition. These operands can be passed to other TargetInstrInfo 311 /// methods to create new branches. 312 /// 313 /// Note that RemoveBranch and InsertBranch must be implemented to support 314 /// cases where this method returns success. 315 /// 316 /// If AllowModify is true, then this routine is allowed to modify the basic 317 /// block (e.g. delete instructions after the unconditional branch). 318 /// 319 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 320 MachineBasicBlock *&FBB, 321 SmallVectorImpl<MachineOperand> &Cond, 322 bool AllowModify = false) const { 323 return true; 324 } 325 326 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 327 /// This is only invoked in cases where AnalyzeBranch returns success. It 328 /// returns the number of instructions that were removed. 329 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 330 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 331 return 0; 332 } 333 334 /// InsertBranch - Insert branch code into the end of the specified 335 /// MachineBasicBlock. The operands to this method are the same as those 336 /// returned by AnalyzeBranch. This is only invoked in cases where 337 /// AnalyzeBranch returns success. It returns the number of instructions 338 /// inserted. 339 /// 340 /// It is also invoked by tail merging to add unconditional branches in 341 /// cases where AnalyzeBranch doesn't apply because there was no original 342 /// branch to analyze. At least this much must be implemented, else tail 343 /// merging needs to be disabled. 344 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 345 MachineBasicBlock *FBB, 346 const SmallVectorImpl<MachineOperand> &Cond) const { 347 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 348 return 0; 349 } 350 351 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 352 /// returns false if the target does not how to copy between the specified 353 /// registers. 354 virtual bool copyRegToReg(MachineBasicBlock &MBB, 355 MachineBasicBlock::iterator MI, 356 unsigned DestReg, unsigned SrcReg, 357 const TargetRegisterClass *DestRC, 358 const TargetRegisterClass *SrcRC) const { 359 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 360 return false; 361 } 362 363 /// storeRegToStackSlot - Store the specified register of the given register 364 /// class to the specified stack frame index. The store instruction is to be 365 /// added to the given machine basic block before the specified machine 366 /// instruction. If isKill is true, the register operand is the last use and 367 /// must be marked kill. 368 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 369 MachineBasicBlock::iterator MI, 370 unsigned SrcReg, bool isKill, int FrameIndex, 371 const TargetRegisterClass *RC) const { 372 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 373 } 374 375 /// loadRegFromStackSlot - Load the specified register of the given register 376 /// class from the specified stack frame index. The load instruction is to be 377 /// added to the given machine basic block before the specified machine 378 /// instruction. 379 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 380 MachineBasicBlock::iterator MI, 381 unsigned DestReg, int FrameIndex, 382 const TargetRegisterClass *RC) const { 383 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 384 } 385 386 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 387 /// saved registers and returns true if it isn't possible / profitable to do 388 /// so by issuing a series of store instructions via 389 /// storeRegToStackSlot(). Returns false otherwise. 390 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 391 MachineBasicBlock::iterator MI, 392 const std::vector<CalleeSavedInfo> &CSI) const { 393 return false; 394 } 395 396 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 397 /// saved registers and returns true if it isn't possible / profitable to do 398 /// so by issuing a series of load instructions via loadRegToStackSlot(). 399 /// Returns false otherwise. 400 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 401 MachineBasicBlock::iterator MI, 402 const std::vector<CalleeSavedInfo> &CSI) const { 403 return false; 404 } 405 406 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 407 /// slot into the specified machine instruction for the specified operand(s). 408 /// If this is possible, a new instruction is returned with the specified 409 /// operand folded, otherwise NULL is returned. The client is responsible for 410 /// removing the old instruction and adding the new one in the instruction 411 /// stream. 412 MachineInstr* foldMemoryOperand(MachineFunction &MF, 413 MachineInstr* MI, 414 const SmallVectorImpl<unsigned> &Ops, 415 int FrameIndex) const; 416 417 /// foldMemoryOperand - Same as the previous version except it allows folding 418 /// of any load and store from / to any address, not just from a specific 419 /// stack slot. 420 MachineInstr* foldMemoryOperand(MachineFunction &MF, 421 MachineInstr* MI, 422 const SmallVectorImpl<unsigned> &Ops, 423 MachineInstr* LoadMI) const; 424 425protected: 426 /// foldMemoryOperandImpl - Target-dependent implementation for 427 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 428 /// take care of adding a MachineMemOperand to the newly created instruction. 429 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 430 MachineInstr* MI, 431 const SmallVectorImpl<unsigned> &Ops, 432 int FrameIndex) const { 433 return 0; 434 } 435 436 /// foldMemoryOperandImpl - Target-dependent implementation for 437 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 438 /// take care of adding a MachineMemOperand to the newly created instruction. 439 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 440 MachineInstr* MI, 441 const SmallVectorImpl<unsigned> &Ops, 442 MachineInstr* LoadMI) const { 443 return 0; 444 } 445 446public: 447 /// canFoldMemoryOperand - Returns true for the specified load / store if 448 /// folding is possible. 449 virtual 450 bool canFoldMemoryOperand(const MachineInstr *MI, 451 const SmallVectorImpl<unsigned> &Ops) const { 452 return false; 453 } 454 455 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 456 /// a store or a load and a store into two or more instruction. If this is 457 /// possible, returns true as well as the new instructions by reference. 458 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 459 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 460 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 461 return false; 462 } 463 464 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 465 SmallVectorImpl<SDNode*> &NewNodes) const { 466 return false; 467 } 468 469 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 470 /// instruction after load / store are unfolded from an instruction of the 471 /// specified opcode. It returns zero if the specified unfolding is not 472 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 473 /// index of the operand which will hold the register holding the loaded 474 /// value. 475 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 476 bool UnfoldLoad, bool UnfoldStore, 477 unsigned *LoadRegIndex = 0) const { 478 return 0; 479 } 480 481 /// ReverseBranchCondition - Reverses the branch condition of the specified 482 /// condition list, returning false on success and true if it cannot be 483 /// reversed. 484 virtual 485 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 486 return true; 487 } 488 489 /// insertNoop - Insert a noop into the instruction stream at the specified 490 /// point. 491 virtual void insertNoop(MachineBasicBlock &MBB, 492 MachineBasicBlock::iterator MI) const; 493 494 /// isPredicated - Returns true if the instruction is already predicated. 495 /// 496 virtual bool isPredicated(const MachineInstr *MI) const { 497 return false; 498 } 499 500 /// isUnpredicatedTerminator - Returns true if the instruction is a 501 /// terminator instruction that has not been predicated. 502 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 503 504 /// PredicateInstruction - Convert the instruction into a predicated 505 /// instruction. It returns true if the operation was successful. 506 virtual 507 bool PredicateInstruction(MachineInstr *MI, 508 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 509 510 /// SubsumesPredicate - Returns true if the first specified predicate 511 /// subsumes the second, e.g. GE subsumes GT. 512 virtual 513 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 514 const SmallVectorImpl<MachineOperand> &Pred2) const { 515 return false; 516 } 517 518 /// DefinesPredicate - If the specified instruction defines any predicate 519 /// or condition code register(s) used for predication, returns true as well 520 /// as the definition predicate(s) by reference. 521 virtual bool DefinesPredicate(MachineInstr *MI, 522 std::vector<MachineOperand> &Pred) const { 523 return false; 524 } 525 526 /// isPredicable - Return true if the specified instruction can be predicated. 527 /// By default, this returns true for every instruction with a 528 /// PredicateOperand. 529 virtual bool isPredicable(MachineInstr *MI) const { 530 return MI->getDesc().isPredicable(); 531 } 532 533 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 534 /// instruction that defines the specified register class. 535 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 536 return true; 537 } 538 539 /// GetInstSize - Returns the size of the specified Instruction. 540 /// 541 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 542 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 543 return 0; 544 } 545 546 /// GetFunctionSizeInBytes - Returns the size of the specified 547 /// MachineFunction. 548 /// 549 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 550 551 /// Measure the specified inline asm to determine an approximation of its 552 /// length. 553 virtual unsigned getInlineAsmLength(const char *Str, 554 const MCAsmInfo &MAI) const; 555}; 556 557/// TargetInstrInfoImpl - This is the default implementation of 558/// TargetInstrInfo, which just provides a couple of default implementations 559/// for various methods. This separated out because it is implemented in 560/// libcodegen, not in libtarget. 561class TargetInstrInfoImpl : public TargetInstrInfo { 562protected: 563 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 564 : TargetInstrInfo(desc, NumOpcodes) {} 565public: 566 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 567 bool NewMI = false) const; 568 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 569 unsigned &SrcOpIdx2) const; 570 virtual bool PredicateInstruction(MachineInstr *MI, 571 const SmallVectorImpl<MachineOperand> &Pred) const; 572 virtual void reMaterialize(MachineBasicBlock &MBB, 573 MachineBasicBlock::iterator MI, 574 unsigned DestReg, unsigned SubReg, 575 const MachineInstr *Orig, 576 const TargetRegisterInfo *TRI) const; 577 virtual MachineInstr *duplicate(MachineInstr *Orig, 578 MachineFunction &MF) const; 579 virtual bool isIdentical(const MachineInstr *MI, 580 const MachineInstr *Other, 581 const MachineRegisterInfo *MRI) const; 582 583 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 584}; 585 586} // End llvm namespace 587 588#endif 589