TargetInstrInfo.h revision dda3978d7877d2d60390833c73ed24857295e89c
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class MCAsmInfo; 23class TargetRegisterClass; 24class LiveVariables; 25class CalleeSavedInfo; 26class SDNode; 27class SelectionDAG; 28 29template<class T> class SmallVectorImpl; 30 31 32//--------------------------------------------------------------------------- 33/// 34/// TargetInstrInfo - Interface to description of machine instruction set 35/// 36class TargetInstrInfo { 37 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 38 unsigned NumOpcodes; // Number of entries in the desc array 39 40 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 41 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 42public: 43 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 44 virtual ~TargetInstrInfo(); 45 46 // Invariant opcodes: All instruction sets have these as their low opcodes. 47 enum { 48 PHI = 0, 49 INLINEASM = 1, 50 DBG_LABEL = 2, 51 EH_LABEL = 3, 52 GC_LABEL = 4, 53 54 /// KILL - This instruction is a noop that is used only to adjust the liveness 55 /// of registers. This can be useful when dealing with sub-registers. 56 KILL = 5, 57 58 /// EXTRACT_SUBREG - This instruction takes two operands: a register 59 /// that has subregisters, and a subregister index. It returns the 60 /// extracted subregister value. This is commonly used to implement 61 /// truncation operations on target architectures which support it. 62 EXTRACT_SUBREG = 6, 63 64 /// INSERT_SUBREG - This instruction takes three operands: a register 65 /// that has subregisters, a register providing an insert value, and a 66 /// subregister index. It returns the value of the first register with 67 /// the value of the second register inserted. The first register is 68 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 69 /// anyext operations on target architectures which support it. 70 INSERT_SUBREG = 7, 71 72 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 73 IMPLICIT_DEF = 8, 74 75 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 76 /// that the first operand is an immediate integer constant. This constant 77 /// is often zero, as is commonly used to implement zext operations on 78 /// target architectures which support it, such as with x86-64 (with 79 /// zext from i32 to i64 via implicit zero-extension). 80 SUBREG_TO_REG = 9, 81 82 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 83 /// register-to-register copy into a specific register class. This is only 84 /// used between instruction selection and MachineInstr creation, before 85 /// virtual registers have been created for all the instructions, and it's 86 /// only needed in cases where the register classes implied by the 87 /// instructions are insufficient. The actual MachineInstrs to perform 88 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 89 COPY_TO_REGCLASS = 10 90 }; 91 92 unsigned getNumOpcodes() const { return NumOpcodes; } 93 94 /// get - Return the machine instruction descriptor that corresponds to the 95 /// specified instruction opcode. 96 /// 97 const TargetInstrDesc &get(unsigned Opcode) const { 98 assert(Opcode < NumOpcodes && "Invalid opcode!"); 99 return Descriptors[Opcode]; 100 } 101 102 /// isTriviallyReMaterializable - Return true if the instruction is trivially 103 /// rematerializable, meaning it has no side effects and requires no operands 104 /// that aren't always available. 105 bool isTriviallyReMaterializable(const MachineInstr *MI, 106 AliasAnalysis *AA = 0) const { 107 return MI->getOpcode() == IMPLICIT_DEF || 108 (MI->getDesc().isRematerializable() && 109 (isReallyTriviallyReMaterializable(MI, AA) || 110 isReallyTriviallyReMaterializableGeneric(MI, AA))); 111 } 112 113protected: 114 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 115 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 116 /// specify whether the instruction is actually trivially rematerializable, 117 /// taking into consideration its operands. This predicate must return false 118 /// if the instruction has any side effects other than producing a value, or 119 /// if it requres any address registers that are not always available. 120 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 121 AliasAnalysis *AA) const { 122 return false; 123 } 124 125private: 126 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 127 /// for which the M_REMATERIALIZABLE flag is set and the target hook 128 /// isReallyTriviallyReMaterializable returns false, this function does 129 /// target-independent tests to determine if the instruction is really 130 /// trivially rematerializable. 131 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 132 AliasAnalysis *AA) const; 133 134public: 135 /// isMoveInstr - Return true if the instruction is a register to register 136 /// move and return the source and dest operands and their sub-register 137 /// indices by reference. 138 virtual bool isMoveInstr(const MachineInstr& MI, 139 unsigned& SrcReg, unsigned& DstReg, 140 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 141 return false; 142 } 143 144 /// isIdentityCopy - Return true if the instruction is a copy (or 145 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 146 /// destination registers are the same. 147 bool isIdentityCopy(const MachineInstr &MI) const { 148 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 149 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 150 SrcReg == DstReg) 151 return true; 152 153 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG && 154 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 155 return true; 156 157 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG || 158 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) && 159 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 160 return true; 161 return false; 162 } 163 164 /// isLoadFromStackSlot - If the specified machine instruction is a direct 165 /// load from a stack slot, return the virtual or physical register number of 166 /// the destination along with the FrameIndex of the loaded stack slot. If 167 /// not, return 0. This predicate must return 0 if the instruction has 168 /// any side effects other than loading from the stack slot. 169 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 170 int &FrameIndex) const { 171 return 0; 172 } 173 174 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 175 /// stack locations as well. This uses a heuristic so it isn't 176 /// reliable for correctness. 177 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 178 int &FrameIndex) const { 179 return 0; 180 } 181 182 /// hasLoadFromStackSlot - If the specified machine instruction has 183 /// a load from a stack slot, return true along with the FrameIndex 184 /// of the loaded stack slot. If not, return false. Unlike 185 /// isLoadFromStackSlot, this returns true for any instructions that 186 /// loads from the stack. This is just a hint, as some cases may be 187 /// missed. 188 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 189 int &FrameIndex) const { 190 return 0; 191 } 192 193 /// isStoreToStackSlot - If the specified machine instruction is a direct 194 /// store to a stack slot, return the virtual or physical register number of 195 /// the source reg along with the FrameIndex of the loaded stack slot. If 196 /// not, return 0. This predicate must return 0 if the instruction has 197 /// any side effects other than storing to the stack slot. 198 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 199 int &FrameIndex) const { 200 return 0; 201 } 202 203 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 204 /// stack locations as well. This uses a heuristic so it isn't 205 /// reliable for correctness. 206 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 207 int &FrameIndex) const { 208 return 0; 209 } 210 211 /// hasStoreToStackSlot - If the specified machine instruction has a 212 /// store to a stack slot, return true along with the FrameIndex of 213 /// the loaded stack slot. If not, return false. Unlike 214 /// isStoreToStackSlot, this returns true for any instructions that 215 /// loads from the stack. This is just a hint, as some cases may be 216 /// missed. 217 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 218 int &FrameIndex) const { 219 return 0; 220 } 221 222 /// reMaterialize - Re-issue the specified 'original' instruction at the 223 /// specific location targeting a new destination register. 224 virtual void reMaterialize(MachineBasicBlock &MBB, 225 MachineBasicBlock::iterator MI, 226 unsigned DestReg, unsigned SubIdx, 227 const MachineInstr *Orig) const = 0; 228 229 /// convertToThreeAddress - This method must be implemented by targets that 230 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 231 /// may be able to convert a two-address instruction into one or more true 232 /// three-address instructions on demand. This allows the X86 target (for 233 /// example) to convert ADD and SHL instructions into LEA instructions if they 234 /// would require register copies due to two-addressness. 235 /// 236 /// This method returns a null pointer if the transformation cannot be 237 /// performed, otherwise it returns the last new instruction. 238 /// 239 virtual MachineInstr * 240 convertToThreeAddress(MachineFunction::iterator &MFI, 241 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 242 return 0; 243 } 244 245 /// commuteInstruction - If a target has any instructions that are commutable, 246 /// but require converting to a different instruction or making non-trivial 247 /// changes to commute them, this method can overloaded to do this. The 248 /// default implementation of this method simply swaps the first two operands 249 /// of MI and returns it. 250 /// 251 /// If a target wants to make more aggressive changes, they can construct and 252 /// return a new machine instruction. If an instruction cannot commute, it 253 /// can also return null. 254 /// 255 /// If NewMI is true, then a new machine instruction must be created. 256 /// 257 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 258 bool NewMI = false) const = 0; 259 260 /// findCommutedOpIndices - If specified MI is commutable, return the two 261 /// operand indices that would swap value. Return true if the instruction 262 /// is not in a form which this routine understands. 263 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 264 unsigned &SrcOpIdx2) const = 0; 265 266 /// isIdentical - Return true if two instructions are identical. This differs 267 /// from MachineInstr::isIdenticalTo() in that it does not require the 268 /// virtual destination registers to be the same. This is used by MachineLICM 269 /// and other MI passes to perform CSE. 270 virtual bool isIdentical(const MachineInstr *MI, 271 const MachineInstr *Other, 272 const MachineRegisterInfo *MRI) const = 0; 273 274 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 275 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 276 /// implemented for a target). Upon success, this returns false and returns 277 /// with the following information in various cases: 278 /// 279 /// 1. If this block ends with no branches (it just falls through to its succ) 280 /// just return false, leaving TBB/FBB null. 281 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 282 /// the destination block. 283 /// 3. If this block ends with an conditional branch and it falls through to 284 /// a successor block, it sets TBB to be the branch destination block and 285 /// a list of operands that evaluate the condition. These 286 /// operands can be passed to other TargetInstrInfo methods to create new 287 /// branches. 288 /// 4. If this block ends with a conditional branch followed by an 289 /// unconditional branch, it returns the 'true' destination in TBB, the 290 /// 'false' destination in FBB, and a list of operands that evaluate the 291 /// condition. These operands can be passed to other TargetInstrInfo 292 /// methods to create new branches. 293 /// 294 /// Note that RemoveBranch and InsertBranch must be implemented to support 295 /// cases where this method returns success. 296 /// 297 /// If AllowModify is true, then this routine is allowed to modify the basic 298 /// block (e.g. delete instructions after the unconditional branch). 299 /// 300 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 301 MachineBasicBlock *&FBB, 302 SmallVectorImpl<MachineOperand> &Cond, 303 bool AllowModify = false) const { 304 return true; 305 } 306 307 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 308 /// This is only invoked in cases where AnalyzeBranch returns success. It 309 /// returns the number of instructions that were removed. 310 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 311 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 312 return 0; 313 } 314 315 /// InsertBranch - Insert branch code into the end of the specified 316 /// MachineBasicBlock. The operands to this method are the same as those 317 /// returned by AnalyzeBranch. This is only invoked in cases where 318 /// AnalyzeBranch returns success. It returns the number of instructions 319 /// inserted. 320 /// 321 /// It is also invoked by tail merging to add unconditional branches in 322 /// cases where AnalyzeBranch doesn't apply because there was no original 323 /// branch to analyze. At least this much must be implemented, else tail 324 /// merging needs to be disabled. 325 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 326 MachineBasicBlock *FBB, 327 const SmallVectorImpl<MachineOperand> &Cond) const { 328 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 329 return 0; 330 } 331 332 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 333 /// returns false if the target does not how to copy between the specified 334 /// registers. 335 virtual bool copyRegToReg(MachineBasicBlock &MBB, 336 MachineBasicBlock::iterator MI, 337 unsigned DestReg, unsigned SrcReg, 338 const TargetRegisterClass *DestRC, 339 const TargetRegisterClass *SrcRC) const { 340 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 341 return false; 342 } 343 344 /// storeRegToStackSlot - Store the specified register of the given register 345 /// class to the specified stack frame index. The store instruction is to be 346 /// added to the given machine basic block before the specified machine 347 /// instruction. If isKill is true, the register operand is the last use and 348 /// must be marked kill. 349 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 350 MachineBasicBlock::iterator MI, 351 unsigned SrcReg, bool isKill, int FrameIndex, 352 const TargetRegisterClass *RC) const { 353 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 354 } 355 356 /// loadRegFromStackSlot - Load the specified register of the given register 357 /// class from the specified stack frame index. The load instruction is to be 358 /// added to the given machine basic block before the specified machine 359 /// instruction. 360 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 361 MachineBasicBlock::iterator MI, 362 unsigned DestReg, int FrameIndex, 363 const TargetRegisterClass *RC) const { 364 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 365 } 366 367 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 368 /// saved registers and returns true if it isn't possible / profitable to do 369 /// so by issuing a series of store instructions via 370 /// storeRegToStackSlot(). Returns false otherwise. 371 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 372 MachineBasicBlock::iterator MI, 373 const std::vector<CalleeSavedInfo> &CSI) const { 374 return false; 375 } 376 377 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 378 /// saved registers and returns true if it isn't possible / profitable to do 379 /// so by issuing a series of load instructions via loadRegToStackSlot(). 380 /// Returns false otherwise. 381 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 382 MachineBasicBlock::iterator MI, 383 const std::vector<CalleeSavedInfo> &CSI) const { 384 return false; 385 } 386 387 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 388 /// slot into the specified machine instruction for the specified operand(s). 389 /// If this is possible, a new instruction is returned with the specified 390 /// operand folded, otherwise NULL is returned. The client is responsible for 391 /// removing the old instruction and adding the new one in the instruction 392 /// stream. 393 MachineInstr* foldMemoryOperand(MachineFunction &MF, 394 MachineInstr* MI, 395 const SmallVectorImpl<unsigned> &Ops, 396 int FrameIndex) const; 397 398 /// foldMemoryOperand - Same as the previous version except it allows folding 399 /// of any load and store from / to any address, not just from a specific 400 /// stack slot. 401 MachineInstr* foldMemoryOperand(MachineFunction &MF, 402 MachineInstr* MI, 403 const SmallVectorImpl<unsigned> &Ops, 404 MachineInstr* LoadMI) const; 405 406protected: 407 /// foldMemoryOperandImpl - Target-dependent implementation for 408 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 409 /// take care of adding a MachineMemOperand to the newly created instruction. 410 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 411 MachineInstr* MI, 412 const SmallVectorImpl<unsigned> &Ops, 413 int FrameIndex) const { 414 return 0; 415 } 416 417 /// foldMemoryOperandImpl - Target-dependent implementation for 418 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 419 /// take care of adding a MachineMemOperand to the newly created instruction. 420 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 421 MachineInstr* MI, 422 const SmallVectorImpl<unsigned> &Ops, 423 MachineInstr* LoadMI) const { 424 return 0; 425 } 426 427public: 428 /// canFoldMemoryOperand - Returns true for the specified load / store if 429 /// folding is possible. 430 virtual 431 bool canFoldMemoryOperand(const MachineInstr *MI, 432 const SmallVectorImpl<unsigned> &Ops) const { 433 return false; 434 } 435 436 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 437 /// a store or a load and a store into two or more instruction. If this is 438 /// possible, returns true as well as the new instructions by reference. 439 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 440 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 441 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 442 return false; 443 } 444 445 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 446 SmallVectorImpl<SDNode*> &NewNodes) const { 447 return false; 448 } 449 450 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 451 /// instruction after load / store are unfolded from an instruction of the 452 /// specified opcode. It returns zero if the specified unfolding is not 453 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 454 /// index of the operand which will hold the register holding the loaded 455 /// value. 456 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 457 bool UnfoldLoad, bool UnfoldStore, 458 unsigned *LoadRegIndex = 0) const { 459 return 0; 460 } 461 462 /// BlockHasNoFallThrough - Return true if the specified block does not 463 /// fall-through into its successor block. This is primarily used when a 464 /// branch is unanalyzable. It is useful for things like unconditional 465 /// indirect branches (jump tables). 466 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 467 return false; 468 } 469 470 /// ReverseBranchCondition - Reverses the branch condition of the specified 471 /// condition list, returning false on success and true if it cannot be 472 /// reversed. 473 virtual 474 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 475 return true; 476 } 477 478 /// insertNoop - Insert a noop into the instruction stream at the specified 479 /// point. 480 virtual void insertNoop(MachineBasicBlock &MBB, 481 MachineBasicBlock::iterator MI) const; 482 483 /// isPredicated - Returns true if the instruction is already predicated. 484 /// 485 virtual bool isPredicated(const MachineInstr *MI) const { 486 return false; 487 } 488 489 /// isUnpredicatedTerminator - Returns true if the instruction is a 490 /// terminator instruction that has not been predicated. 491 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 492 493 /// PredicateInstruction - Convert the instruction into a predicated 494 /// instruction. It returns true if the operation was successful. 495 virtual 496 bool PredicateInstruction(MachineInstr *MI, 497 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 498 499 /// SubsumesPredicate - Returns true if the first specified predicate 500 /// subsumes the second, e.g. GE subsumes GT. 501 virtual 502 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 503 const SmallVectorImpl<MachineOperand> &Pred2) const { 504 return false; 505 } 506 507 /// DefinesPredicate - If the specified instruction defines any predicate 508 /// or condition code register(s) used for predication, returns true as well 509 /// as the definition predicate(s) by reference. 510 virtual bool DefinesPredicate(MachineInstr *MI, 511 std::vector<MachineOperand> &Pred) const { 512 return false; 513 } 514 515 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 516 /// instruction that defines the specified register class. 517 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 518 return true; 519 } 520 521 /// GetInstSize - Returns the size of the specified Instruction. 522 /// 523 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 524 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 525 return 0; 526 } 527 528 /// GetFunctionSizeInBytes - Returns the size of the specified 529 /// MachineFunction. 530 /// 531 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 532 533 /// Measure the specified inline asm to determine an approximation of its 534 /// length. 535 virtual unsigned getInlineAsmLength(const char *Str, 536 const MCAsmInfo &MAI) const; 537}; 538 539/// TargetInstrInfoImpl - This is the default implementation of 540/// TargetInstrInfo, which just provides a couple of default implementations 541/// for various methods. This separated out because it is implemented in 542/// libcodegen, not in libtarget. 543class TargetInstrInfoImpl : public TargetInstrInfo { 544protected: 545 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 546 : TargetInstrInfo(desc, NumOpcodes) {} 547public: 548 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 549 bool NewMI = false) const; 550 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 551 unsigned &SrcOpIdx2) const; 552 virtual bool PredicateInstruction(MachineInstr *MI, 553 const SmallVectorImpl<MachineOperand> &Pred) const; 554 virtual void reMaterialize(MachineBasicBlock &MBB, 555 MachineBasicBlock::iterator MI, 556 unsigned DestReg, unsigned SubReg, 557 const MachineInstr *Orig) const; 558 virtual bool isIdentical(const MachineInstr *MI, 559 const MachineInstr *Other, 560 const MachineRegisterInfo *MRI) const; 561 562 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 563}; 564 565} // End llvm namespace 566 567#endif 568