TargetInstrInfo.h revision de7266c611b37ec050efb53b73166081a98cea13
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file describes the target machine instruction set to the code generator. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 139ab5563a3196760eb381d102cbb2bc0f7abc6a50Ben Murdoch 145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#ifndef LLVM_TARGET_TARGETINSTRINFO_H 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define LLVM_TARGET_TARGETINSTRINFO_H 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 17c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "llvm/MC/MCInstrInfo.h" 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CodeGen/DFAPacketizer.h" 19eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch#include "llvm/CodeGen/MachineFunction.h" 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)namespace llvm { 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class InstrItineraryData; 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class LiveVariables; 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class MCAsmInfo; 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class MachineMemOperand; 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class MachineRegisterInfo; 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class MDNode; 29c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)class MCInst; 30c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)class SDNode; 31c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)class ScheduleHazardRecognizer; 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class SelectionDAG; 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class ScheduleDAG; 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class TargetRegisterClass; 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class TargetRegisterInfo; 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class BranchProbability; 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)template<class T> class SmallVectorImpl; 39d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 40d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//--------------------------------------------------------------------------- 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// TargetInstrInfo - Interface to description of machine instruction set 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// 45f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)class TargetInstrInfo : public MCInstrInfo { 46f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)public: 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) : CallFrameSetupOpcode(CFSetupOpcode), 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CallFrameDestroyOpcode(CFDestroyOpcode) { 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 54f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) virtual ~TargetInstrInfo(); 55f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getRegClass - Givem a machine instruction descriptor, returns the register 575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// class constraint for OpNum, or NULL. 58c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, 59c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) unsigned OpNum, 60c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) const TargetRegisterInfo *TRI, 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MachineFunction &MF) const; 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isTriviallyReMaterializable - Return true if the instruction is trivially 645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// rematerializable, meaning it has no side effects and requires no operands 65f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// that aren't always available. 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isTriviallyReMaterializable(const MachineInstr *MI, 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) AliasAnalysis *AA = 0) const { 682a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 692a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) (MI->getDesc().isRematerializable() && 702a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) (isReallyTriviallyReMaterializable(MI, AA) || 712a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) isReallyTriviallyReMaterializableGeneric(MI, AA))); 7268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) } 732a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 742a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)protected: 75010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// isReallyTriviallyReMaterializable - For instructions with opcodes for 76010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 77010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// specify whether the instruction is actually trivially rematerializable, 78010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// taking into consideration its operands. This predicate must return false 79010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// if the instruction has any side effects other than producing a value, or 80010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// if it requres any address registers that are not always available. 81010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 82010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) AliasAnalysis *AA) const { 83d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) return false; 8446d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) } 85d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)private: 875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 88868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// for which the M_REMATERIALIZABLE flag is set and the target hook 89868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// isReallyTriviallyReMaterializable returns false, this function does 90868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// target-independent tests to determine if the instruction is really 91868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// trivially rematerializable. 925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) AliasAnalysis *AA) const; 94f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)public: 965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// frame setup/destroy instructions if they exist (-1 otherwise). Some 98a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// targets use pseudo instructions in order to abstract away the difference 99a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// between operating with a frame pointer and operating without, through the 100a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// use of these two instructions. 101a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// 1025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 1035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 1045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 1065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// extension instruction. That is, it's like a copy where it's legal for the 1075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 108eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// true, then it's expected the pre-extension value is available as a subreg 109eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// of the result register. This also returns the sub-register index in 110eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// SubIdx. 111eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch virtual bool isCoalescableExtInstr(const MachineInstr &MI, 1125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned &SrcReg, unsigned &DstReg, 113d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned &SubIdx) const { 11446d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) return false; 11546d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) } 11646d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) 11746d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// isLoadFromStackSlot - If the specified machine instruction is a direct 11846d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// load from a stack slot, return the virtual or physical register number of 1195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the destination along with the FrameIndex of the loaded stack slot. If 1205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// not, return 0. This predicate must return 0 if the instruction has 1215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// any side effects other than loading from the stack slot. 1225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 123f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) int &FrameIndex) const { 124eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch return 0; 125f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) } 12668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 127f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 1285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// stack locations as well. This uses a heuristic so it isn't 1295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reliable for correctness. 1305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 1315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int &FrameIndex) const { 1325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return 0; 1335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// hasLoadFromStackSlot - If the specified machine instruction has 1365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// a load from a stack slot, return true along with the FrameIndex 1375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// of the loaded stack slot and the machine mem operand containing 1385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the reference. If not, return false. Unlike 1395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isLoadFromStackSlot, this returns true for any instructions that 1405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// loads from the stack. This is just a hint, as some cases may be 1415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// missed. 1425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 1435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MachineMemOperand *&MMO, 144f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) int &FrameIndex) const { 14546d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) return 0; 1465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isStoreToStackSlot - If the specified machine instruction is a direct 1495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// store to a stack slot, return the virtual or physical register number of 150f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// the source reg along with the FrameIndex of the loaded stack slot. If 1515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// not, return 0. This predicate must return 0 if the instruction has 1525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// any side effects other than storing to the stack slot. 1535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 1545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int &FrameIndex) const { 1555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return 0; 1565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 158eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 1595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// stack locations as well. This uses a heuristic so it isn't 1605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reliable for correctness. 161d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 1625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int &FrameIndex) const { 1635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return 0; 1645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// hasStoreToStackSlot - If the specified machine instruction has a 1675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// store to a stack slot, return true along with the FrameIndex of 1685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the loaded stack slot and the machine mem operand containing the 1695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reference. If not, return false. Unlike isStoreToStackSlot, 1705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// this returns true for any instructions that stores to the 1715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// stack. This is just a hint, as some cases may be missed. 172eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch virtual bool hasStoreToStackSlot(const MachineInstr *MI, 173eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch const MachineMemOperand *&MMO, 1745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int &FrameIndex) const { 1755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return 0; 1765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reMaterialize - Re-issue the specified 'original' instruction at the 1795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specific location targeting a new destination register. 1801320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci /// The register in Orig->getOperand(0).getReg() will be substituted by 1815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 1825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// SubIdx. 1835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void reMaterialize(MachineBasicBlock &MBB, 1845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator MI, 1855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned DestReg, unsigned SubIdx, 1865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MachineInstr *Orig, 1875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterInfo &TRI) const = 0; 1885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 1905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// two-addrss instruction inserted by two-address pass. 1915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 192eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch MachineInstr *UseMI, 193eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch const TargetRegisterInfo &TRI) const { 194eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch // Do nothing. 195c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 196c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 1975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 1985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// MachineFunction::CloneMachineInstr(), but the target may update operands 1995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// that are required to be unique. 2005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// The instruction must be duplicable as indicated by isNotDuplicable(). 2025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual MachineInstr *duplicate(MachineInstr *Orig, 2035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineFunction &MF) const = 0; 2045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// convertToThreeAddress - This method must be implemented by targets that 2065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 20746d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// may be able to convert a two-address instruction into one or more true 2085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// three-address instructions on demand. This allows the X86 target (for 2095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// example) to convert ADD and SHL instructions into LEA instructions if they 2105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// would require register copies due to two-addressness. 2115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This method returns a null pointer if the transformation cannot be 2135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// performed, otherwise it returns the last new instruction. 2145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual MachineInstr * 21646d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) convertToThreeAddress(MachineFunction::iterator &MFI, 217f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 2185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return 0; 219116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch } 220116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 221116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// commuteInstruction - If a target has any instructions that are 222116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// commutable but require converting to different instructions or making 223116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// non-trivial changes to commute them, this method can overloaded to do 224116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// that. The default implementation simply swaps the commutable operands. 225c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// If NewMI is false, MI is modified in place and returned; otherwise, a 226c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// new machine instruction is created and returned. Do not call this 227c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// method for a non-commutable instruction, but there may be some cases 228c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// where this method fails and returns null. 229c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) virtual MachineInstr *commuteInstruction(MachineInstr *MI, 23046d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) bool NewMI = false) const = 0; 231c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 232cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// findCommutedOpIndices - If specified MI is commutable, return the two 233116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// operand indices that would swap value. Return false if the instruction 234cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) /// is not in a form which this routine understands. 235cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 236cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned &SrcOpIdx2) const = 0; 237eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch 23846d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// produceSameValue - Return true if two machine instructions would produce 239eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// identical values. By default, this is only true when the two instructions 240eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// are deemed identical except for defs. If this function is called when the 241eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 242eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// aggressive checks. 243eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch virtual bool produceSameValue(const MachineInstr *MI0, 244116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const MachineInstr *MI1, 245116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch const MachineRegisterInfo *MRI = 0) const = 0; 246116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 247116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 248116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 249116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// implemented for a target). Upon success, this returns false and returns 250eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// with the following information in various cases: 251eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// 252eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// 1. If this block ends with no branches (it just falls through to its succ) 253eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// just return false, leaving TBB/FBB null. 254eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// 2. If this block ends with only an unconditional branch, it sets TBB to be 2555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the destination block. 2565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 3. If this block ends with a conditional branch and it falls through to a 2575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// successor block, it sets TBB to be the branch destination block and a 2585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// list of operands that evaluate the condition. These operands can be 2595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// passed to other TargetInstrInfo methods to create new branches. 2605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 4. If this block ends with a conditional branch followed by an 2615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// unconditional branch, it returns the 'true' destination in TBB, the 2625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 'false' destination in FBB, and a list of operands that evaluate the 2632a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// condition. These operands can be passed to other TargetInstrInfo 2645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// methods to create new branches. 2655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Note that RemoveBranch and InsertBranch must be implemented to support 2675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// cases where this method returns success. 2685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// If AllowModify is true, then this routine is allowed to modify the basic 2705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// block (e.g. delete instructions after the unconditional branch). 27168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// 27258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 27368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) MachineBasicBlock *&FBB, 27468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) SmallVectorImpl<MachineOperand> &Cond, 27568043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) bool AllowModify = false) const { 27668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) return true; 27768043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) } 2785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// RemoveBranch - Remove the branching code at the end of the specific MBB. 2805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This is only invoked in cases where AnalyzeBranch returns success. It 2812a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// returns the number of instructions that were removed. 2822a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 2832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!"); 28468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) } 28568043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 2862a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// InsertBranch - Insert branch code into the end of the specified 28746d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// MachineBasicBlock. The operands to this method are the same as those 28846d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// returned by AnalyzeBranch. This is only invoked in cases where 28946d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// AnalyzeBranch returns success. It returns the number of instructions 29046d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// inserted. 2912a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 2922a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// It is also invoked by tail merging to add unconditional branches in 293868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) /// cases where AnalyzeBranch doesn't apply because there was no original 2945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// branch to analyze. At least this much must be implemented, else tail 2955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// merging needs to be disabled. 2965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock *FBB, 2985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const SmallVectorImpl<MachineOperand> &Cond, 299eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch DebugLoc DL) const { 3005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); 3015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 3045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// after it, replacing it with an unconditional branch to NewDest. This is 3055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// used by the tail merging pass. 30668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 30768043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) MachineBasicBlock *NewDest) const = 0; 3085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 31068043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// block at the specified instruction (i.e. instruction would be the start 3115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// of a new basic block). 3125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 3136d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) MachineBasicBlock::iterator MBBI) const { 3145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return true; 3155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isProfitableToIfCvt - Return true if it's profitable to predicate 3185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// instructions with accumulated instruction latency of "NumCycles" 319d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// of the specified basic block, where the probability of the instructions 320d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// being executed is given by Probability, and Confidence is a measure 3212385ea399aae016c0806a4f9ef3c9cfe3d2a39dfBen Murdoch /// of our confidence that it will be properly predicted. 322a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) virtual 32346d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 324a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) unsigned ExtraPredCycles, 3252385ea399aae016c0806a4f9ef3c9cfe3d2a39dfBen Murdoch const BranchProbability &Probability) const { 32646d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) return false; 3272385ea399aae016c0806a4f9ef3c9cfe3d2a39dfBen Murdoch } 3285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 32946d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 330a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// checks for the case where two basic blocks from true and false path 3315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// of a if-then-else (diamond) are predicated on mutally exclusive 33246d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// predicates, where the probability of the true path being taken is given 333c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// by Probability, and Confidence is a measure of our confidence that it 334a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// will be properly predicted. 335a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) virtual bool 3362a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) isProfitableToIfCvt(MachineBasicBlock &TMBB, 3375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned NumTCycles, unsigned ExtraTCycles, 33846d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) MachineBasicBlock &FMBB, 3395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned NumFCycles, unsigned ExtraFCycles, 340a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) const BranchProbability &Probability) const { 3415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return false; 3425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 34346d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) 344a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// isProfitableToDupForIfCvt - Return true if it's profitable for 3455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// if-converter to duplicate instructions of specified accumulated 3465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// instruction latencies in the specified MBB to enable if-conversion. 3475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// The probability of the instructions being executed is given by 3485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Probability, and Confidence is a measure of our confidence that it 3495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// will be properly predicted. 3505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool 3515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 35268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) const BranchProbability &Probability) const { 3535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return false; 354a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } 3555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 35668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate 3575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 358a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// exclusive predicates. 3595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// e.g. 36068043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// subeq r0, r1, #1 36146d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// addne r0, r1, #1 3625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// => 363a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// sub r0, r1, #1 3645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// addne r0, r1, #1 3655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 366a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// This may be profitable is conditional instructions are always executed. 3675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 36868043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) MachineBasicBlock &FMBB) const { 3695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return false; 3705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// copyPhysReg - Emit instructions to copy a pair of physical registers. 3735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void copyPhysReg(MachineBasicBlock &MBB, 3745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineBasicBlock::iterator MI, DebugLoc DL, 3755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned DestReg, unsigned SrcReg, 3766d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) bool KillSrc) const { 3775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 37846d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) } 379a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 3805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// storeRegToStackSlot - Store the specified register of the given register 38146d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) /// class to the specified stack frame index. The store instruction is to be 3825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// added to the given machine basic block before the specified machine 383f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// instruction. If isKill is true, the register operand is the last use and 384f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// must be marked kill. 3855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 3866d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) MachineBasicBlock::iterator MI, 387a93a17c8d99d686bd4a1511e5504e5e6cc9fcadfTorne (Richard Coles) unsigned SrcReg, bool isKill, int FrameIndex, 388eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch const TargetRegisterClass *RC, 389f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) const TargetRegisterInfo *TRI) const { 3905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) llvm_unreachable("Target didn't implement " 3915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "TargetInstrInfo::storeRegToStackSlot!"); 3925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 39468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// loadRegFromStackSlot - Load the specified register of the given register 3955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// class from the specified stack frame index. The load instruction is to be 3965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// added to the given machine basic block before the specified machine 3975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// instruction. 39846d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 399eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch MachineBasicBlock::iterator MI, 400f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) unsigned DestReg, int FrameIndex, 401f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) const TargetRegisterClass *RC, 4026d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) const TargetRegisterInfo *TRI) const { 4036d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) llvm_unreachable("Target didn't implement " 404f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) "TargetInstrInfo::loadRegFromStackSlot!"); 405f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) } 406f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 407f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// expandPostRAPseudo - This function is called for all pseudo instructions 408f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// that remain after register allocation. Many pseudo instructions are 409f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// created to help register allocation. This is the place to convert them 410f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// into real instructions. The target can edit MI in place, or it can insert 4116d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) /// new instructions and erase MI. The function should return true if 4125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// anything was changed. 413f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 414f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) return false; 415a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } 4165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 4175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// emitFrameIndexDebugValue - Emit a target-dependent form of 418f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) /// DBG_VALUE encoding the address of a frame index. Addresses would 4195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// normally be lowered the same way as other addresses on the target, 4206d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) /// e.g. in load instructions. For targets that do not support this 4215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the debug info is simply lost. 4225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// If you add this for a target you should handle this DBG_VALUE in the 4235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// target-specific AsmPrinter code as well; you will probably get invalid 4245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// assembly output if you don't. 425c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 426c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) int FrameIx, 427c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) uint64_t Offset, 4287dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch const MDNode *MDPtr, 429c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DebugLoc dl) const { 430c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return 0; 431c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 43268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 433c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 434c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// slot into the specified machine instruction for the specified operand(s). 4355f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) /// If this is possible, a new instruction is returned with the specified 4365f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) /// operand folded, otherwise NULL is returned. 437c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// The new instruction is inserted before MI, and the client is responsible 438c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// for removing the old instruction. 43968043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 4407dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch const SmallVectorImpl<unsigned> &Ops, 4417dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch int FrameIndex) const; 4427dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch 4437dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch /// foldMemoryOperand - Same as the previous version except it allows folding 44468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// of any load and store from / to any address, not just from a specific 4457dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch /// stack slot. 4467dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 4477dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch const SmallVectorImpl<unsigned> &Ops, 4487dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch MachineInstr* LoadMI) const; 44968043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 450c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)protected: 451c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// foldMemoryOperandImpl - Target-dependent implementation for 452c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 453c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// take care of adding a MachineMemOperand to the newly created instruction. 454c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 455c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) MachineInstr* MI, 45646d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) const SmallVectorImpl<unsigned> &Ops, 457c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) int FrameIndex) const { 458c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return 0; 459eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch } 460f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 461c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// foldMemoryOperandImpl - Target-dependent implementation for 462c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 463c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// take care of adding a MachineMemOperand to the newly created instruction. 464c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 465c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) MachineInstr* MI, 466c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) const SmallVectorImpl<unsigned> &Ops, 467010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) MachineInstr* LoadMI) const { 468010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return 0; 469010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) } 470c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 47146d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles)public: 472c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// canFoldMemoryOperand - Returns true for the specified load / store if 47368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// folding is possible. 47446d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) virtual 475c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) bool canFoldMemoryOperand(const MachineInstr *MI, 47646d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) const SmallVectorImpl<unsigned> &Ops) const =0; 477010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 478010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// unfoldMemoryOperand - Separate a single instruction which folded a load or 479010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) /// a store or a load and a store into two or more instruction. If this is 480eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// possible, returns true as well as the new instructions by reference. 481eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 482f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 483f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) SmallVectorImpl<MachineInstr*> &NewMIs) const{ 484a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return false; 48546d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) } 486a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 487eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 4886d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) SmallVectorImpl<SDNode*> &NewNodes) const { 4896d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) return false; 490a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } 491eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch 492eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 493a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// instruction after load / store are unfolded from an instruction of the 494eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// specified opcode. It returns zero if the specified unfolding is not 495eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// possible. If LoadRegIndex is non-null, it is filled in with the operand 4966d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles) /// index of the operand which will hold the register holding the loaded 497eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// value. 498eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 499eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch bool UnfoldLoad, bool UnfoldStore, 500f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) unsigned *LoadRegIndex = 0) const { 501a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) return 0; 502eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch } 50368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 504eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 505eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// to determine if two loads are loading from the same base address. It 506a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) /// should only return true if the base pointers are the same and the 507eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// only differences between the two addresses are the offset. It also returns 508eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// the offsets by reference. 509eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 510eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch int64_t &Offset1, int64_t &Offset2) const { 511c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return false; 5125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 5135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 514 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 515 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 516 /// be scheduled togther. On some targets if two loads are loading from 517 /// addresses in the same cache line, it's better if they are scheduled 518 /// together. This function takes two integers that represent the load offsets 519 /// from the common base address. It returns true if it decides it's desirable 520 /// to schedule the two loads together. "NumLoads" is the number of loads that 521 /// have already been scheduled after Load1. 522 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 523 int64_t Offset1, int64_t Offset2, 524 unsigned NumLoads) const { 525 return false; 526 } 527 528 /// ReverseBranchCondition - Reverses the branch condition of the specified 529 /// condition list, returning false on success and true if it cannot be 530 /// reversed. 531 virtual 532 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 533 return true; 534 } 535 536 /// insertNoop - Insert a noop into the instruction stream at the specified 537 /// point. 538 virtual void insertNoop(MachineBasicBlock &MBB, 539 MachineBasicBlock::iterator MI) const; 540 541 542 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 543 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 544 // Default to just using 'nop' string. 545 } 546 547 548 /// isPredicated - Returns true if the instruction is already predicated. 549 /// 550 virtual bool isPredicated(const MachineInstr *MI) const { 551 return false; 552 } 553 554 /// isUnpredicatedTerminator - Returns true if the instruction is a 555 /// terminator instruction that has not been predicated. 556 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const = 0; 557 558 /// PredicateInstruction - Convert the instruction into a predicated 559 /// instruction. It returns true if the operation was successful. 560 virtual 561 bool PredicateInstruction(MachineInstr *MI, 562 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 563 564 /// SubsumesPredicate - Returns true if the first specified predicate 565 /// subsumes the second, e.g. GE subsumes GT. 566 virtual 567 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 568 const SmallVectorImpl<MachineOperand> &Pred2) const { 569 return false; 570 } 571 572 /// DefinesPredicate - If the specified instruction defines any predicate 573 /// or condition code register(s) used for predication, returns true as well 574 /// as the definition predicate(s) by reference. 575 virtual bool DefinesPredicate(MachineInstr *MI, 576 std::vector<MachineOperand> &Pred) const { 577 return false; 578 } 579 580 /// isPredicable - Return true if the specified instruction can be predicated. 581 /// By default, this returns true for every instruction with a 582 /// PredicateOperand. 583 virtual bool isPredicable(MachineInstr *MI) const { 584 return MI->getDesc().isPredicable(); 585 } 586 587 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 588 /// instruction that defines the specified register class. 589 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 590 return true; 591 } 592 593 /// isSchedulingBoundary - Test if the given instruction should be 594 /// considered a scheduling boundary. This primarily includes labels and 595 /// terminators. 596 virtual bool isSchedulingBoundary(const MachineInstr *MI, 597 const MachineBasicBlock *MBB, 598 const MachineFunction &MF) const = 0; 599 600 /// Measure the specified inline asm to determine an approximation of its 601 /// length. 602 virtual unsigned getInlineAsmLength(const char *Str, 603 const MCAsmInfo &MAI) const; 604 605 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 606 /// use for this target when scheduling the machine instructions before 607 /// register allocation. 608 virtual ScheduleHazardRecognizer* 609 CreateTargetHazardRecognizer(const TargetMachine *TM, 610 const ScheduleDAG *DAG) const = 0; 611 612 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer 613 /// to use for this target when scheduling the machine instructions before 614 /// register allocation. 615 virtual ScheduleHazardRecognizer* 616 CreateTargetMIHazardRecognizer(const InstrItineraryData*, 617 const ScheduleDAG *DAG) const = 0; 618 619 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 620 /// recognizer to use for this target when scheduling the machine instructions 621 /// after register allocation. 622 virtual ScheduleHazardRecognizer* 623 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 624 const ScheduleDAG *DAG) const = 0; 625 626 /// analyzeCompare - For a comparison instruction, return the source registers 627 /// in SrcReg and SrcReg2 if having two register operands, and the value it 628 /// compares against in CmpValue. Return true if the comparison instruction 629 /// can be analyzed. 630 virtual bool analyzeCompare(const MachineInstr *MI, 631 unsigned &SrcReg, unsigned &SrcReg2, 632 int &Mask, int &Value) const { 633 return false; 634 } 635 636 /// optimizeCompareInstr - See if the comparison instruction can be converted 637 /// into something more efficient. E.g., on ARM most instructions can set the 638 /// flags register, obviating the need for a separate CMP. 639 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 640 unsigned SrcReg, unsigned SrcReg2, 641 int Mask, int Value, 642 const MachineRegisterInfo *MRI) const { 643 return false; 644 } 645 646 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 647 /// instruction, try to fold the immediate into the use instruction. 648 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 649 unsigned Reg, MachineRegisterInfo *MRI) const { 650 return false; 651 } 652 653 /// getNumMicroOps - Return the number of u-operations the given machine 654 /// instruction will be decoded to on the target cpu. 655 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 656 const MachineInstr *MI) const = 0; 657 658 /// isZeroCost - Return true for pseudo instructions that don't consume any 659 /// machine resources in their current form. These are common cases that the 660 /// scheduler should consider free, rather than conservatively handling them 661 /// as instructions with no itinerary. 662 bool isZeroCost(unsigned Opcode) const { 663 return Opcode <= TargetOpcode::COPY; 664 } 665 666 virtual int getOperandLatency(const InstrItineraryData *ItinData, 667 SDNode *DefNode, unsigned DefIdx, 668 SDNode *UseNode, unsigned UseIdx) const = 0; 669 670 /// getOperandLatency - Compute and return the use operand latency of a given 671 /// pair of def and use. 672 /// In most cases, the static scheduling itinerary was enough to determine the 673 /// operand latency. But it may not be possible for instructions with variable 674 /// number of defs / uses. 675 /// 676 /// This is a raw interface to the itinerary that may be directly overriden by 677 /// a target. Use computeOperandLatency to get the best estimate of latency. 678 virtual int getOperandLatency(const InstrItineraryData *ItinData, 679 const MachineInstr *DefMI, unsigned DefIdx, 680 const MachineInstr *UseMI, 681 unsigned UseIdx) const = 0; 682 683 /// computeOperandLatency - Compute and return the latency of the given data 684 /// dependent def and use when the operand indices are already known. 685 /// 686 /// FindMin may be set to get the minimum vs. expected latency. 687 unsigned computeOperandLatency(const InstrItineraryData *ItinData, 688 const MachineInstr *DefMI, unsigned DefIdx, 689 const MachineInstr *UseMI, unsigned UseIdx, 690 bool FindMin = false) const; 691 692 /// computeOperandLatency - Compute and return the latency of the given data 693 /// dependent def and use. DefMI must be a valid def. UseMI may be NULL for 694 /// an unknown use. If the subtarget allows, this may or may not need to call 695 /// getOperandLatency(). 696 /// 697 /// FindMin may be set to get the minimum vs. expected latency. Minimum 698 /// latency is used for scheduling groups, while expected latency is for 699 /// instruction cost and critical path. 700 unsigned computeOperandLatency(const InstrItineraryData *ItinData, 701 const TargetRegisterInfo *TRI, 702 const MachineInstr *DefMI, 703 const MachineInstr *UseMI, 704 unsigned Reg, bool FindMin) const; 705 706 /// getOutputLatency - Compute and return the output dependency latency of a 707 /// a given pair of defs which both target the same register. This is usually 708 /// one. 709 virtual unsigned getOutputLatency(const InstrItineraryData *ItinData, 710 const MachineInstr *DefMI, unsigned DefIdx, 711 const MachineInstr *DepMI) const { 712 return 1; 713 } 714 715 /// getInstrLatency - Compute the instruction latency of a given instruction. 716 /// If the instruction has higher cost when predicated, it's returned via 717 /// PredCost. 718 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 719 const MachineInstr *MI, 720 unsigned *PredCost = 0) const = 0; 721 722 virtual int getInstrLatency(const InstrItineraryData *ItinData, 723 SDNode *Node) const = 0; 724 725 /// Return the default expected latency for a def based on it's opcode. 726 unsigned defaultDefLatency(const InstrItineraryData *ItinData, 727 const MachineInstr *DefMI) const; 728 729 /// isHighLatencyDef - Return true if this opcode has high latency to its 730 /// result. 731 virtual bool isHighLatencyDef(int opc) const { return false; } 732 733 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 734 /// and an use in the current loop, return true if the target considered 735 /// it 'high'. This is used by optimization passes such as machine LICM to 736 /// determine whether it makes sense to hoist an instruction out even in 737 /// high register pressure situation. 738 virtual 739 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 740 const MachineRegisterInfo *MRI, 741 const MachineInstr *DefMI, unsigned DefIdx, 742 const MachineInstr *UseMI, unsigned UseIdx) const { 743 return false; 744 } 745 746 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 747 /// if the target considered it 'low'. 748 virtual 749 bool hasLowDefLatency(const InstrItineraryData *ItinData, 750 const MachineInstr *DefMI, unsigned DefIdx) const = 0; 751 752 /// verifyInstruction - Perform target specific instruction verification. 753 virtual 754 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { 755 return true; 756 } 757 758 /// getExecutionDomain - Return the current execution domain and bit mask of 759 /// possible domains for instruction. 760 /// 761 /// Some micro-architectures have multiple execution domains, and multiple 762 /// opcodes that perform the same operation in different domains. For 763 /// example, the x86 architecture provides the por, orps, and orpd 764 /// instructions that all do the same thing. There is a latency penalty if a 765 /// register is written in one domain and read in another. 766 /// 767 /// This function returns a pair (domain, mask) containing the execution 768 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 769 /// function can be used to change the opcode to one of the domains in the 770 /// bit mask. Instructions whose execution domain can't be changed should 771 /// return a 0 mask. 772 /// 773 /// The execution domain numbers don't have any special meaning except domain 774 /// 0 is used for instructions that are not associated with any interesting 775 /// execution domain. 776 /// 777 virtual std::pair<uint16_t, uint16_t> 778 getExecutionDomain(const MachineInstr *MI) const { 779 return std::make_pair(0, 0); 780 } 781 782 /// setExecutionDomain - Change the opcode of MI to execute in Domain. 783 /// 784 /// The bit (1 << Domain) must be set in the mask returned from 785 /// getExecutionDomain(MI). 786 /// 787 virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {} 788 789 790 /// getPartialRegUpdateClearance - Returns the preferred minimum clearance 791 /// before an instruction with an unwanted partial register update. 792 /// 793 /// Some instructions only write part of a register, and implicitly need to 794 /// read the other parts of the register. This may cause unwanted stalls 795 /// preventing otherwise unrelated instructions from executing in parallel in 796 /// an out-of-order CPU. 797 /// 798 /// For example, the x86 instruction cvtsi2ss writes its result to bits 799 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 800 /// the instruction needs to wait for the old value of the register to become 801 /// available: 802 /// 803 /// addps %xmm1, %xmm0 804 /// movaps %xmm0, (%rax) 805 /// cvtsi2ss %rbx, %xmm0 806 /// 807 /// In the code above, the cvtsi2ss instruction needs to wait for the addps 808 /// instruction before it can issue, even though the high bits of %xmm0 809 /// probably aren't needed. 810 /// 811 /// This hook returns the preferred clearance before MI, measured in 812 /// instructions. Other defs of MI's operand OpNum are avoided in the last N 813 /// instructions before MI. It should only return a positive value for 814 /// unwanted dependencies. If the old bits of the defined register have 815 /// useful values, or if MI is determined to otherwise read the dependency, 816 /// the hook should return 0. 817 /// 818 /// The unwanted dependency may be handled by: 819 /// 820 /// 1. Allocating the same register for an MI def and use. That makes the 821 /// unwanted dependency identical to a required dependency. 822 /// 823 /// 2. Allocating a register for the def that has no defs in the previous N 824 /// instructions. 825 /// 826 /// 3. Calling breakPartialRegDependency() with the same arguments. This 827 /// allows the target to insert a dependency breaking instruction. 828 /// 829 virtual unsigned 830 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 831 const TargetRegisterInfo *TRI) const { 832 // The default implementation returns 0 for no partial register dependency. 833 return 0; 834 } 835 836 /// breakPartialRegDependency - Insert a dependency-breaking instruction 837 /// before MI to eliminate an unwanted dependency on OpNum. 838 /// 839 /// If it wasn't possible to avoid a def in the last N instructions before MI 840 /// (see getPartialRegUpdateClearance), this hook will be called to break the 841 /// unwanted dependency. 842 /// 843 /// On x86, an xorps instruction can be used as a dependency breaker: 844 /// 845 /// addps %xmm1, %xmm0 846 /// movaps %xmm0, (%rax) 847 /// xorps %xmm0, %xmm0 848 /// cvtsi2ss %rbx, %xmm0 849 /// 850 /// An <imp-kill> operand should be added to MI if an instruction was 851 /// inserted. This ties the instructions together in the post-ra scheduler. 852 /// 853 virtual void 854 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 855 const TargetRegisterInfo *TRI) const {} 856 857 /// Create machine specific model for scheduling. 858 virtual DFAPacketizer* 859 CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const { 860 return NULL; 861 } 862 863private: 864 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 865}; 866 867/// TargetInstrInfoImpl - This is the default implementation of 868/// TargetInstrInfo, which just provides a couple of default implementations 869/// for various methods. This separated out because it is implemented in 870/// libcodegen, not in libtarget. 871class TargetInstrInfoImpl : public TargetInstrInfo { 872protected: 873 TargetInstrInfoImpl(int CallFrameSetupOpcode = -1, 874 int CallFrameDestroyOpcode = -1) 875 : TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {} 876public: 877 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 878 MachineBasicBlock *NewDest) const; 879 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 880 bool NewMI = false) const; 881 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 882 unsigned &SrcOpIdx2) const; 883 virtual bool canFoldMemoryOperand(const MachineInstr *MI, 884 const SmallVectorImpl<unsigned> &Ops) const; 885 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 886 const MachineMemOperand *&MMO, 887 int &FrameIndex) const; 888 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 889 const MachineMemOperand *&MMO, 890 int &FrameIndex) const; 891 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 892 virtual bool PredicateInstruction(MachineInstr *MI, 893 const SmallVectorImpl<MachineOperand> &Pred) const; 894 virtual void reMaterialize(MachineBasicBlock &MBB, 895 MachineBasicBlock::iterator MI, 896 unsigned DestReg, unsigned SubReg, 897 const MachineInstr *Orig, 898 const TargetRegisterInfo &TRI) const; 899 virtual MachineInstr *duplicate(MachineInstr *Orig, 900 MachineFunction &MF) const; 901 virtual bool produceSameValue(const MachineInstr *MI0, 902 const MachineInstr *MI1, 903 const MachineRegisterInfo *MRI) const; 904 virtual bool isSchedulingBoundary(const MachineInstr *MI, 905 const MachineBasicBlock *MBB, 906 const MachineFunction &MF) const; 907 908 virtual int getOperandLatency(const InstrItineraryData *ItinData, 909 SDNode *DefNode, unsigned DefIdx, 910 SDNode *UseNode, unsigned UseIdx) const; 911 912 virtual int getInstrLatency(const InstrItineraryData *ItinData, 913 SDNode *Node) const; 914 915 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 916 const MachineInstr *MI) const; 917 918 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 919 const MachineInstr *MI, 920 unsigned *PredCost = 0) const; 921 922 virtual 923 bool hasLowDefLatency(const InstrItineraryData *ItinData, 924 const MachineInstr *DefMI, unsigned DefIdx) const; 925 926 virtual int getOperandLatency(const InstrItineraryData *ItinData, 927 const MachineInstr *DefMI, unsigned DefIdx, 928 const MachineInstr *UseMI, 929 unsigned UseIdx) const; 930 931 bool usePreRAHazardRecognizer() const; 932 933 virtual ScheduleHazardRecognizer * 934 CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const; 935 936 virtual ScheduleHazardRecognizer * 937 CreateTargetMIHazardRecognizer(const InstrItineraryData*, 938 const ScheduleDAG*) const; 939 940 virtual ScheduleHazardRecognizer * 941 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 942 const ScheduleDAG*) const; 943}; 944 945} // End llvm namespace 946 947#endif 948