TargetInstrInfo.h revision e33f44cfc547359bc28526e4c5e1852b600b4448
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class MCAsmInfo; 23class TargetRegisterClass; 24class TargetRegisterInfo; 25class LiveVariables; 26class CalleeSavedInfo; 27class SDNode; 28class SelectionDAG; 29 30template<class T> class SmallVectorImpl; 31 32 33//--------------------------------------------------------------------------- 34/// 35/// TargetInstrInfo - Interface to description of machine instruction set 36/// 37class TargetInstrInfo { 38 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 39 unsigned NumOpcodes; // Number of entries in the desc array 40 41 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 42 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 43public: 44 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 45 virtual ~TargetInstrInfo(); 46 47 // Invariant opcodes: All instruction sets have these as their low opcodes. 48 enum { 49 PHI = 0, 50 INLINEASM = 1, 51 DBG_LABEL = 2, 52 EH_LABEL = 3, 53 GC_LABEL = 4, 54 55 /// KILL - This instruction is a noop that is used only to adjust the liveness 56 /// of registers. This can be useful when dealing with sub-registers. 57 KILL = 5, 58 59 /// EXTRACT_SUBREG - This instruction takes two operands: a register 60 /// that has subregisters, and a subregister index. It returns the 61 /// extracted subregister value. This is commonly used to implement 62 /// truncation operations on target architectures which support it. 63 EXTRACT_SUBREG = 6, 64 65 /// INSERT_SUBREG - This instruction takes three operands: a register 66 /// that has subregisters, a register providing an insert value, and a 67 /// subregister index. It returns the value of the first register with 68 /// the value of the second register inserted. The first register is 69 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 70 /// anyext operations on target architectures which support it. 71 INSERT_SUBREG = 7, 72 73 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 74 IMPLICIT_DEF = 8, 75 76 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 77 /// that the first operand is an immediate integer constant. This constant 78 /// is often zero, as is commonly used to implement zext operations on 79 /// target architectures which support it, such as with x86-64 (with 80 /// zext from i32 to i64 via implicit zero-extension). 81 SUBREG_TO_REG = 9, 82 83 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 84 /// register-to-register copy into a specific register class. This is only 85 /// used between instruction selection and MachineInstr creation, before 86 /// virtual registers have been created for all the instructions, and it's 87 /// only needed in cases where the register classes implied by the 88 /// instructions are insufficient. The actual MachineInstrs to perform 89 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 90 COPY_TO_REGCLASS = 10 91 }; 92 93 unsigned getNumOpcodes() const { return NumOpcodes; } 94 95 /// get - Return the machine instruction descriptor that corresponds to the 96 /// specified instruction opcode. 97 /// 98 const TargetInstrDesc &get(unsigned Opcode) const { 99 assert(Opcode < NumOpcodes && "Invalid opcode!"); 100 return Descriptors[Opcode]; 101 } 102 103 /// isTriviallyReMaterializable - Return true if the instruction is trivially 104 /// rematerializable, meaning it has no side effects and requires no operands 105 /// that aren't always available. 106 bool isTriviallyReMaterializable(const MachineInstr *MI) const { 107 return MI->getDesc().isRematerializable() && 108 isReallyTriviallyReMaterializable(MI); 109 } 110 111protected: 112 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 113 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 114 /// instruction itself is actually trivially rematerializable, considering 115 /// its operands. This is used for targets that have instructions that are 116 /// only trivially rematerializable for specific uses. This predicate must 117 /// return false if the instruction has any side effects other than 118 /// producing a value, or if it requres any address registers that are not 119 /// always available. 120 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 121 return true; 122 } 123 124public: 125 /// Return true if the instruction is a register to register move and return 126 /// the source and dest operands and their sub-register indices by reference. 127 virtual bool isMoveInstr(const MachineInstr& MI, 128 unsigned& SrcReg, unsigned& DstReg, 129 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 130 return false; 131 } 132 133 /// isLoadFromStackSlot - If the specified machine instruction is a direct 134 /// load from a stack slot, return the virtual or physical register number of 135 /// the destination along with the FrameIndex of the loaded stack slot. If 136 /// not, return 0. This predicate must return 0 if the instruction has 137 /// any side effects other than loading from the stack slot. 138 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 139 int &FrameIndex) const { 140 return 0; 141 } 142 143 /// isStoreToStackSlot - If the specified machine instruction is a direct 144 /// store to a stack slot, return the virtual or physical register number of 145 /// the source reg along with the FrameIndex of the loaded stack slot. If 146 /// not, return 0. This predicate must return 0 if the instruction has 147 /// any side effects other than storing to the stack slot. 148 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 149 int &FrameIndex) const { 150 return 0; 151 } 152 153 /// reMaterialize - Re-issue the specified 'original' instruction at the 154 /// specific location targeting a new destination register. 155 virtual void reMaterialize(MachineBasicBlock &MBB, 156 MachineBasicBlock::iterator MI, 157 unsigned DestReg, unsigned SubIdx, 158 const MachineInstr *Orig) const = 0; 159 160 /// convertToThreeAddress - This method must be implemented by targets that 161 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 162 /// may be able to convert a two-address instruction into one or more true 163 /// three-address instructions on demand. This allows the X86 target (for 164 /// example) to convert ADD and SHL instructions into LEA instructions if they 165 /// would require register copies due to two-addressness. 166 /// 167 /// This method returns a null pointer if the transformation cannot be 168 /// performed, otherwise it returns the last new instruction. 169 /// 170 virtual MachineInstr * 171 convertToThreeAddress(MachineFunction::iterator &MFI, 172 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 173 return 0; 174 } 175 176 /// commuteInstruction - If a target has any instructions that are commutable, 177 /// but require converting to a different instruction or making non-trivial 178 /// changes to commute them, this method can overloaded to do this. The 179 /// default implementation of this method simply swaps the first two operands 180 /// of MI and returns it. 181 /// 182 /// If a target wants to make more aggressive changes, they can construct and 183 /// return a new machine instruction. If an instruction cannot commute, it 184 /// can also return null. 185 /// 186 /// If NewMI is true, then a new machine instruction must be created. 187 /// 188 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 189 bool NewMI = false) const = 0; 190 191 /// findCommutedOpIndices - If specified MI is commutable, return the two 192 /// operand indices that would swap value. Return true if the instruction 193 /// is not in a form which this routine understands. 194 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 195 unsigned &SrcOpIdx2) const = 0; 196 197 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 198 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 199 /// implemented for a target). Upon success, this returns false and returns 200 /// with the following information in various cases: 201 /// 202 /// 1. If this block ends with no branches (it just falls through to its succ) 203 /// just return false, leaving TBB/FBB null. 204 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 205 /// the destination block. 206 /// 3. If this block ends with an conditional branch and it falls through to 207 /// a successor block, it sets TBB to be the branch destination block and 208 /// a list of operands that evaluate the condition. These 209 /// operands can be passed to other TargetInstrInfo methods to create new 210 /// branches. 211 /// 4. If this block ends with a conditional branch followed by an 212 /// unconditional branch, it returns the 'true' destination in TBB, the 213 /// 'false' destination in FBB, and a list of operands that evaluate the 214 /// condition. These operands can be passed to other TargetInstrInfo 215 /// methods to create new branches. 216 /// 217 /// Note that RemoveBranch and InsertBranch must be implemented to support 218 /// cases where this method returns success. 219 /// 220 /// If AllowModify is true, then this routine is allowed to modify the basic 221 /// block (e.g. delete instructions after the unconditional branch). 222 /// 223 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 224 MachineBasicBlock *&FBB, 225 SmallVectorImpl<MachineOperand> &Cond, 226 bool AllowModify = false) const { 227 return true; 228 } 229 230 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 231 /// This is only invoked in cases where AnalyzeBranch returns success. It 232 /// returns the number of instructions that were removed. 233 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 234 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 235 return 0; 236 } 237 238 /// InsertBranch - Insert branch code into the end of the specified 239 /// MachineBasicBlock. The operands to this method are the same as those 240 /// returned by AnalyzeBranch. This is only invoked in cases where 241 /// AnalyzeBranch returns success. It returns the number of instructions 242 /// inserted. 243 /// 244 /// It is also invoked by tail merging to add unconditional branches in 245 /// cases where AnalyzeBranch doesn't apply because there was no original 246 /// branch to analyze. At least this much must be implemented, else tail 247 /// merging needs to be disabled. 248 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 249 MachineBasicBlock *FBB, 250 const SmallVectorImpl<MachineOperand> &Cond) const { 251 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 252 return 0; 253 } 254 255 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 256 /// returns false if the target does not how to copy between the specified 257 /// registers. 258 virtual bool copyRegToReg(MachineBasicBlock &MBB, 259 MachineBasicBlock::iterator MI, 260 unsigned DestReg, unsigned SrcReg, 261 const TargetRegisterClass *DestRC, 262 const TargetRegisterClass *SrcRC) const { 263 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 264 return false; 265 } 266 267 /// storeRegToStackSlot - Store the specified register of the given register 268 /// class to the specified stack frame index. The store instruction is to be 269 /// added to the given machine basic block before the specified machine 270 /// instruction. If isKill is true, the register operand is the last use and 271 /// must be marked kill. 272 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 273 MachineBasicBlock::iterator MI, 274 unsigned SrcReg, bool isKill, int FrameIndex, 275 const TargetRegisterClass *RC) const { 276 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 277 } 278 279 /// loadRegFromStackSlot - Load the specified register of the given register 280 /// class from the specified stack frame index. The load instruction is to be 281 /// added to the given machine basic block before the specified machine 282 /// instruction. 283 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 284 MachineBasicBlock::iterator MI, 285 unsigned DestReg, int FrameIndex, 286 const TargetRegisterClass *RC) const { 287 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 288 } 289 290 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 291 /// saved registers and returns true if it isn't possible / profitable to do 292 /// so by issuing a series of store instructions via 293 /// storeRegToStackSlot(). Returns false otherwise. 294 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 295 MachineBasicBlock::iterator MI, 296 const std::vector<CalleeSavedInfo> &CSI) const { 297 return false; 298 } 299 300 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 301 /// saved registers and returns true if it isn't possible / profitable to do 302 /// so by issuing a series of load instructions via loadRegToStackSlot(). 303 /// Returns false otherwise. 304 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 305 MachineBasicBlock::iterator MI, 306 const std::vector<CalleeSavedInfo> &CSI) const { 307 return false; 308 } 309 310 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 311 /// slot into the specified machine instruction for the specified operand(s). 312 /// If this is possible, a new instruction is returned with the specified 313 /// operand folded, otherwise NULL is returned. The client is responsible for 314 /// removing the old instruction and adding the new one in the instruction 315 /// stream. 316 MachineInstr* foldMemoryOperand(MachineFunction &MF, 317 MachineInstr* MI, 318 const SmallVectorImpl<unsigned> &Ops, 319 int FrameIndex) const; 320 321 /// foldMemoryOperand - Same as the previous version except it allows folding 322 /// of any load and store from / to any address, not just from a specific 323 /// stack slot. 324 MachineInstr* foldMemoryOperand(MachineFunction &MF, 325 MachineInstr* MI, 326 const SmallVectorImpl<unsigned> &Ops, 327 MachineInstr* LoadMI) const; 328 329protected: 330 /// foldMemoryOperandImpl - Target-dependent implementation for 331 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 332 /// take care of adding a MachineMemOperand to the newly created instruction. 333 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 334 MachineInstr* MI, 335 const SmallVectorImpl<unsigned> &Ops, 336 int FrameIndex) const { 337 return 0; 338 } 339 340 /// foldMemoryOperandImpl - Target-dependent implementation for 341 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 342 /// take care of adding a MachineMemOperand to the newly created instruction. 343 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 344 MachineInstr* MI, 345 const SmallVectorImpl<unsigned> &Ops, 346 MachineInstr* LoadMI) const { 347 return 0; 348 } 349 350public: 351 /// canFoldMemoryOperand - Returns true for the specified load / store if 352 /// folding is possible. 353 virtual 354 bool canFoldMemoryOperand(const MachineInstr *MI, 355 const SmallVectorImpl<unsigned> &Ops) const { 356 return false; 357 } 358 359 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 360 /// a store or a load and a store into two or more instruction. If this is 361 /// possible, returns true as well as the new instructions by reference. 362 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 363 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 364 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 365 return false; 366 } 367 368 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 369 SmallVectorImpl<SDNode*> &NewNodes) const { 370 return false; 371 } 372 373 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 374 /// instruction after load / store are unfolded from an instruction of the 375 /// specified opcode. It returns zero if the specified unfolding is not 376 /// possible. 377 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 378 bool UnfoldLoad, bool UnfoldStore) const { 379 return 0; 380 } 381 382 /// BlockHasNoFallThrough - Return true if the specified block does not 383 /// fall-through into its successor block. This is primarily used when a 384 /// branch is unanalyzable. It is useful for things like unconditional 385 /// indirect branches (jump tables). 386 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 387 return false; 388 } 389 390 /// ReverseBranchCondition - Reverses the branch condition of the specified 391 /// condition list, returning false on success and true if it cannot be 392 /// reversed. 393 virtual 394 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 395 return true; 396 } 397 398 /// insertNoop - Insert a noop into the instruction stream at the specified 399 /// point. 400 virtual void insertNoop(MachineBasicBlock &MBB, 401 MachineBasicBlock::iterator MI) const; 402 403 /// isPredicated - Returns true if the instruction is already predicated. 404 /// 405 virtual bool isPredicated(const MachineInstr *MI) const { 406 return false; 407 } 408 409 /// isUnpredicatedTerminator - Returns true if the instruction is a 410 /// terminator instruction that has not been predicated. 411 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 412 413 /// PredicateInstruction - Convert the instruction into a predicated 414 /// instruction. It returns true if the operation was successful. 415 virtual 416 bool PredicateInstruction(MachineInstr *MI, 417 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 418 419 /// SubsumesPredicate - Returns true if the first specified predicate 420 /// subsumes the second, e.g. GE subsumes GT. 421 virtual 422 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 423 const SmallVectorImpl<MachineOperand> &Pred2) const { 424 return false; 425 } 426 427 /// DefinesPredicate - If the specified instruction defines any predicate 428 /// or condition code register(s) used for predication, returns true as well 429 /// as the definition predicate(s) by reference. 430 virtual bool DefinesPredicate(MachineInstr *MI, 431 std::vector<MachineOperand> &Pred) const { 432 return false; 433 } 434 435 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 436 /// instruction that defines the specified register class. 437 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 438 return true; 439 } 440 441 /// isDeadInstruction - Return true if the instruction is considered dead. 442 /// This allows some late codegen passes to delete them. 443 virtual bool isDeadInstruction(const MachineInstr *MI) const = 0; 444 445 /// GetInstSize - Returns the size of the specified Instruction. 446 /// 447 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 448 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 449 return 0; 450 } 451 452 /// GetFunctionSizeInBytes - Returns the size of the specified 453 /// MachineFunction. 454 /// 455 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 456 457 /// Measure the specified inline asm to determine an approximation of its 458 /// length. 459 virtual unsigned getInlineAsmLength(const char *Str, 460 const MCAsmInfo &MAI) const; 461}; 462 463/// TargetInstrInfoImpl - This is the default implementation of 464/// TargetInstrInfo, which just provides a couple of default implementations 465/// for various methods. This separated out because it is implemented in 466/// libcodegen, not in libtarget. 467class TargetInstrInfoImpl : public TargetInstrInfo { 468protected: 469 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 470 : TargetInstrInfo(desc, NumOpcodes) {} 471public: 472 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 473 bool NewMI = false) const; 474 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 475 unsigned &SrcOpIdx2) const; 476 virtual bool PredicateInstruction(MachineInstr *MI, 477 const SmallVectorImpl<MachineOperand> &Pred) const; 478 virtual void reMaterialize(MachineBasicBlock &MBB, 479 MachineBasicBlock::iterator MI, 480 unsigned DestReg, unsigned SubReg, 481 const MachineInstr *Orig) const; 482 virtual bool isDeadInstruction(const MachineInstr *MI) const; 483 484 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 485}; 486 487} // End llvm namespace 488 489#endif 490