TargetInstrInfo.h revision e3cc84a43d6a4bb6c50f58f3dd8e60e28787509e
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class CalleeSavedInfo; 23class InstrItineraryData; 24class LiveVariables; 25class MCAsmInfo; 26class MachineMemOperand; 27class MDNode; 28class MCInst; 29class SDNode; 30class ScheduleHazardRecognizer; 31class SelectionDAG; 32class TargetRegisterClass; 33class TargetRegisterInfo; 34 35template<class T> class SmallVectorImpl; 36 37 38//--------------------------------------------------------------------------- 39/// 40/// TargetInstrInfo - Interface to description of machine instruction set 41/// 42class TargetInstrInfo { 43 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 44 unsigned NumOpcodes; // Number of entries in the desc array 45 46 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 47 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 48public: 49 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 50 virtual ~TargetInstrInfo(); 51 52 unsigned getNumOpcodes() const { return NumOpcodes; } 53 54 /// get - Return the machine instruction descriptor that corresponds to the 55 /// specified instruction opcode. 56 /// 57 const TargetInstrDesc &get(unsigned Opcode) const { 58 assert(Opcode < NumOpcodes && "Invalid opcode!"); 59 return Descriptors[Opcode]; 60 } 61 62 /// isTriviallyReMaterializable - Return true if the instruction is trivially 63 /// rematerializable, meaning it has no side effects and requires no operands 64 /// that aren't always available. 65 bool isTriviallyReMaterializable(const MachineInstr *MI, 66 AliasAnalysis *AA = 0) const { 67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 68 (MI->getDesc().isRematerializable() && 69 (isReallyTriviallyReMaterializable(MI, AA) || 70 isReallyTriviallyReMaterializableGeneric(MI, AA))); 71 } 72 73protected: 74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 75 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 76 /// specify whether the instruction is actually trivially rematerializable, 77 /// taking into consideration its operands. This predicate must return false 78 /// if the instruction has any side effects other than producing a value, or 79 /// if it requres any address registers that are not always available. 80 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 81 AliasAnalysis *AA) const { 82 return false; 83 } 84 85private: 86 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 87 /// for which the M_REMATERIALIZABLE flag is set and the target hook 88 /// isReallyTriviallyReMaterializable returns false, this function does 89 /// target-independent tests to determine if the instruction is really 90 /// trivially rematerializable. 91 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 92 AliasAnalysis *AA) const; 93 94public: 95 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 96 /// extension instruction. That is, it's like a copy where it's legal for the 97 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 98 /// true, then it's expected the pre-extension value is available as a subreg 99 /// of the result register. This also returns the sub-register index in 100 /// SubIdx. 101 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 102 unsigned &SrcReg, unsigned &DstReg, 103 unsigned &SubIdx) const { 104 return false; 105 } 106 107 /// isLoadFromStackSlot - If the specified machine instruction is a direct 108 /// load from a stack slot, return the virtual or physical register number of 109 /// the destination along with the FrameIndex of the loaded stack slot. If 110 /// not, return 0. This predicate must return 0 if the instruction has 111 /// any side effects other than loading from the stack slot. 112 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 113 int &FrameIndex) const { 114 return 0; 115 } 116 117 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 118 /// stack locations as well. This uses a heuristic so it isn't 119 /// reliable for correctness. 120 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 121 int &FrameIndex) const { 122 return 0; 123 } 124 125 /// hasLoadFromStackSlot - If the specified machine instruction has 126 /// a load from a stack slot, return true along with the FrameIndex 127 /// of the loaded stack slot and the machine mem operand containing 128 /// the reference. If not, return false. Unlike 129 /// isLoadFromStackSlot, this returns true for any instructions that 130 /// loads from the stack. This is just a hint, as some cases may be 131 /// missed. 132 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 133 const MachineMemOperand *&MMO, 134 int &FrameIndex) const { 135 return 0; 136 } 137 138 /// isStoreToStackSlot - If the specified machine instruction is a direct 139 /// store to a stack slot, return the virtual or physical register number of 140 /// the source reg along with the FrameIndex of the loaded stack slot. If 141 /// not, return 0. This predicate must return 0 if the instruction has 142 /// any side effects other than storing to the stack slot. 143 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 144 int &FrameIndex) const { 145 return 0; 146 } 147 148 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 149 /// stack locations as well. This uses a heuristic so it isn't 150 /// reliable for correctness. 151 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 152 int &FrameIndex) const { 153 return 0; 154 } 155 156 /// hasStoreToStackSlot - If the specified machine instruction has a 157 /// store to a stack slot, return true along with the FrameIndex of 158 /// the loaded stack slot and the machine mem operand containing the 159 /// reference. If not, return false. Unlike isStoreToStackSlot, 160 /// this returns true for any instructions that stores to the 161 /// stack. This is just a hint, as some cases may be missed. 162 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 163 const MachineMemOperand *&MMO, 164 int &FrameIndex) const { 165 return 0; 166 } 167 168 /// reMaterialize - Re-issue the specified 'original' instruction at the 169 /// specific location targeting a new destination register. 170 /// The register in Orig->getOperand(0).getReg() will be substituted by 171 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 172 /// SubIdx. 173 virtual void reMaterialize(MachineBasicBlock &MBB, 174 MachineBasicBlock::iterator MI, 175 unsigned DestReg, unsigned SubIdx, 176 const MachineInstr *Orig, 177 const TargetRegisterInfo &TRI) const = 0; 178 179 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 180 /// two-addrss instruction inserted by two-address pass. 181 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 182 MachineInstr *UseMI, 183 const TargetRegisterInfo &TRI) const { 184 // Do nothing. 185 } 186 187 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 188 /// MachineFunction::CloneMachineInstr(), but the target may update operands 189 /// that are required to be unique. 190 /// 191 /// The instruction must be duplicable as indicated by isNotDuplicable(). 192 virtual MachineInstr *duplicate(MachineInstr *Orig, 193 MachineFunction &MF) const = 0; 194 195 /// convertToThreeAddress - This method must be implemented by targets that 196 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 197 /// may be able to convert a two-address instruction into one or more true 198 /// three-address instructions on demand. This allows the X86 target (for 199 /// example) to convert ADD and SHL instructions into LEA instructions if they 200 /// would require register copies due to two-addressness. 201 /// 202 /// This method returns a null pointer if the transformation cannot be 203 /// performed, otherwise it returns the last new instruction. 204 /// 205 virtual MachineInstr * 206 convertToThreeAddress(MachineFunction::iterator &MFI, 207 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 208 return 0; 209 } 210 211 /// commuteInstruction - If a target has any instructions that are 212 /// commutable but require converting to different instructions or making 213 /// non-trivial changes to commute them, this method can overloaded to do 214 /// that. The default implementation simply swaps the commutable operands. 215 /// If NewMI is false, MI is modified in place and returned; otherwise, a 216 /// new machine instruction is created and returned. Do not call this 217 /// method for a non-commutable instruction, but there may be some cases 218 /// where this method fails and returns null. 219 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 220 bool NewMI = false) const = 0; 221 222 /// findCommutedOpIndices - If specified MI is commutable, return the two 223 /// operand indices that would swap value. Return false if the instruction 224 /// is not in a form which this routine understands. 225 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 226 unsigned &SrcOpIdx2) const = 0; 227 228 /// produceSameValue - Return true if two machine instructions would produce 229 /// identical values. By default, this is only true when the two instructions 230 /// are deemed identical except for defs. 231 virtual bool produceSameValue(const MachineInstr *MI0, 232 const MachineInstr *MI1) const = 0; 233 234 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 235 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 236 /// implemented for a target). Upon success, this returns false and returns 237 /// with the following information in various cases: 238 /// 239 /// 1. If this block ends with no branches (it just falls through to its succ) 240 /// just return false, leaving TBB/FBB null. 241 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 242 /// the destination block. 243 /// 3. If this block ends with a conditional branch and it falls through to a 244 /// successor block, it sets TBB to be the branch destination block and a 245 /// list of operands that evaluate the condition. These operands can be 246 /// passed to other TargetInstrInfo methods to create new branches. 247 /// 4. If this block ends with a conditional branch followed by an 248 /// unconditional branch, it returns the 'true' destination in TBB, the 249 /// 'false' destination in FBB, and a list of operands that evaluate the 250 /// condition. These operands can be passed to other TargetInstrInfo 251 /// methods to create new branches. 252 /// 253 /// Note that RemoveBranch and InsertBranch must be implemented to support 254 /// cases where this method returns success. 255 /// 256 /// If AllowModify is true, then this routine is allowed to modify the basic 257 /// block (e.g. delete instructions after the unconditional branch). 258 /// 259 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 260 MachineBasicBlock *&FBB, 261 SmallVectorImpl<MachineOperand> &Cond, 262 bool AllowModify = false) const { 263 return true; 264 } 265 266 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 267 /// This is only invoked in cases where AnalyzeBranch returns success. It 268 /// returns the number of instructions that were removed. 269 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 270 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 271 return 0; 272 } 273 274 /// InsertBranch - Insert branch code into the end of the specified 275 /// MachineBasicBlock. The operands to this method are the same as those 276 /// returned by AnalyzeBranch. This is only invoked in cases where 277 /// AnalyzeBranch returns success. It returns the number of instructions 278 /// inserted. 279 /// 280 /// It is also invoked by tail merging to add unconditional branches in 281 /// cases where AnalyzeBranch doesn't apply because there was no original 282 /// branch to analyze. At least this much must be implemented, else tail 283 /// merging needs to be disabled. 284 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 285 MachineBasicBlock *FBB, 286 const SmallVectorImpl<MachineOperand> &Cond, 287 DebugLoc DL) const { 288 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 289 return 0; 290 } 291 292 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 293 /// after it, replacing it with an unconditional branch to NewDest. This is 294 /// used by the tail merging pass. 295 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 296 MachineBasicBlock *NewDest) const = 0; 297 298 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 299 /// block at the specified instruction (i.e. instruction would be the start 300 /// of a new basic block). 301 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 302 MachineBasicBlock::iterator MBBI) const { 303 return true; 304 } 305 306 /// isProfitableToIfCvt - Return true if it's profitable to first "NumInstrs" 307 /// of the specified basic block, where the probability of the instructions 308 /// being executed is given by Probability, and Confidence is a measure 309 /// of our confidence that it will be properly predicted. 310 virtual 311 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs, 312 float Probability, float Confidence) const { 313 return false; 314 } 315 316 /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 317 /// checks for the case where two basic blocks from true and false path 318 /// of a if-then-else (diamond) are predicated on mutally exclusive 319 /// predicates, where the probability of the true path being taken is given 320 /// by Probability, and Confidence is a measure of our confidence that it 321 /// will be properly predicted. 322 virtual bool 323 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs, 324 MachineBasicBlock &FMBB, unsigned NumFInstrs, 325 float Probability, float Confidence) const { 326 return false; 327 } 328 329 /// isProfitableToDupForIfCvt - Return true if it's profitable for 330 /// if-converter to duplicate a specific number of instructions in the 331 /// specified MBB to enable if-conversion, where the probability of the 332 /// instructions being executed is given by Probability, and Confidence is 333 /// a measure of our confidence that it will be properly predicted. 334 virtual bool 335 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs, 336 float Probability, float Confidence) const { 337 return false; 338 } 339 340 /// copyPhysReg - Emit instructions to copy a pair of physical registers. 341 virtual void copyPhysReg(MachineBasicBlock &MBB, 342 MachineBasicBlock::iterator MI, DebugLoc DL, 343 unsigned DestReg, unsigned SrcReg, 344 bool KillSrc) const { 345 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!"); 346 } 347 348 /// storeRegToStackSlot - Store the specified register of the given register 349 /// class to the specified stack frame index. The store instruction is to be 350 /// added to the given machine basic block before the specified machine 351 /// instruction. If isKill is true, the register operand is the last use and 352 /// must be marked kill. 353 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 354 MachineBasicBlock::iterator MI, 355 unsigned SrcReg, bool isKill, int FrameIndex, 356 const TargetRegisterClass *RC, 357 const TargetRegisterInfo *TRI) const { 358 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 359 } 360 361 /// loadRegFromStackSlot - Load the specified register of the given register 362 /// class from the specified stack frame index. The load instruction is to be 363 /// added to the given machine basic block before the specified machine 364 /// instruction. 365 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 366 MachineBasicBlock::iterator MI, 367 unsigned DestReg, int FrameIndex, 368 const TargetRegisterClass *RC, 369 const TargetRegisterInfo *TRI) const { 370 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 371 } 372 373 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 374 /// saved registers and returns true if it isn't possible / profitable to do 375 /// so by issuing a series of store instructions via 376 /// storeRegToStackSlot(). Returns false otherwise. 377 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 378 MachineBasicBlock::iterator MI, 379 const std::vector<CalleeSavedInfo> &CSI, 380 const TargetRegisterInfo *TRI) const { 381 return false; 382 } 383 384 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 385 /// saved registers and returns true if it isn't possible / profitable to do 386 /// so by issuing a series of load instructions via loadRegToStackSlot(). 387 /// Returns false otherwise. 388 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 389 MachineBasicBlock::iterator MI, 390 const std::vector<CalleeSavedInfo> &CSI, 391 const TargetRegisterInfo *TRI) const { 392 return false; 393 } 394 395 /// emitFrameIndexDebugValue - Emit a target-dependent form of 396 /// DBG_VALUE encoding the address of a frame index. Addresses would 397 /// normally be lowered the same way as other addresses on the target, 398 /// e.g. in load instructions. For targets that do not support this 399 /// the debug info is simply lost. 400 /// If you add this for a target you should handle this DBG_VALUE in the 401 /// target-specific AsmPrinter code as well; you will probably get invalid 402 /// assembly output if you don't. 403 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 404 int FrameIx, 405 uint64_t Offset, 406 const MDNode *MDPtr, 407 DebugLoc dl) const { 408 return 0; 409 } 410 411 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 412 /// slot into the specified machine instruction for the specified operand(s). 413 /// If this is possible, a new instruction is returned with the specified 414 /// operand folded, otherwise NULL is returned. 415 /// The new instruction is inserted before MI, and the client is responsible 416 /// for removing the old instruction. 417 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 418 const SmallVectorImpl<unsigned> &Ops, 419 int FrameIndex) const; 420 421 /// foldMemoryOperand - Same as the previous version except it allows folding 422 /// of any load and store from / to any address, not just from a specific 423 /// stack slot. 424 MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 425 const SmallVectorImpl<unsigned> &Ops, 426 MachineInstr* LoadMI) const; 427 428protected: 429 /// foldMemoryOperandImpl - Target-dependent implementation for 430 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 431 /// take care of adding a MachineMemOperand to the newly created instruction. 432 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 433 MachineInstr* MI, 434 const SmallVectorImpl<unsigned> &Ops, 435 int FrameIndex) const { 436 return 0; 437 } 438 439 /// foldMemoryOperandImpl - Target-dependent implementation for 440 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 441 /// take care of adding a MachineMemOperand to the newly created instruction. 442 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 443 MachineInstr* MI, 444 const SmallVectorImpl<unsigned> &Ops, 445 MachineInstr* LoadMI) const { 446 return 0; 447 } 448 449public: 450 /// canFoldMemoryOperand - Returns true for the specified load / store if 451 /// folding is possible. 452 virtual 453 bool canFoldMemoryOperand(const MachineInstr *MI, 454 const SmallVectorImpl<unsigned> &Ops) const =0; 455 456 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 457 /// a store or a load and a store into two or more instruction. If this is 458 /// possible, returns true as well as the new instructions by reference. 459 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 460 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 461 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 462 return false; 463 } 464 465 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 466 SmallVectorImpl<SDNode*> &NewNodes) const { 467 return false; 468 } 469 470 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 471 /// instruction after load / store are unfolded from an instruction of the 472 /// specified opcode. It returns zero if the specified unfolding is not 473 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 474 /// index of the operand which will hold the register holding the loaded 475 /// value. 476 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 477 bool UnfoldLoad, bool UnfoldStore, 478 unsigned *LoadRegIndex = 0) const { 479 return 0; 480 } 481 482 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 483 /// to determine if two loads are loading from the same base address. It 484 /// should only return true if the base pointers are the same and the 485 /// only differences between the two addresses are the offset. It also returns 486 /// the offsets by reference. 487 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 488 int64_t &Offset1, int64_t &Offset2) const { 489 return false; 490 } 491 492 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 493 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 494 /// be scheduled togther. On some targets if two loads are loading from 495 /// addresses in the same cache line, it's better if they are scheduled 496 /// together. This function takes two integers that represent the load offsets 497 /// from the common base address. It returns true if it decides it's desirable 498 /// to schedule the two loads together. "NumLoads" is the number of loads that 499 /// have already been scheduled after Load1. 500 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 501 int64_t Offset1, int64_t Offset2, 502 unsigned NumLoads) const { 503 return false; 504 } 505 506 /// ReverseBranchCondition - Reverses the branch condition of the specified 507 /// condition list, returning false on success and true if it cannot be 508 /// reversed. 509 virtual 510 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 511 return true; 512 } 513 514 /// insertNoop - Insert a noop into the instruction stream at the specified 515 /// point. 516 virtual void insertNoop(MachineBasicBlock &MBB, 517 MachineBasicBlock::iterator MI) const; 518 519 520 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 521 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 522 // Default to just using 'nop' string. 523 } 524 525 526 /// isPredicated - Returns true if the instruction is already predicated. 527 /// 528 virtual bool isPredicated(const MachineInstr *MI) const { 529 return false; 530 } 531 532 /// isUnpredicatedTerminator - Returns true if the instruction is a 533 /// terminator instruction that has not been predicated. 534 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 535 536 /// PredicateInstruction - Convert the instruction into a predicated 537 /// instruction. It returns true if the operation was successful. 538 virtual 539 bool PredicateInstruction(MachineInstr *MI, 540 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 541 542 /// SubsumesPredicate - Returns true if the first specified predicate 543 /// subsumes the second, e.g. GE subsumes GT. 544 virtual 545 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 546 const SmallVectorImpl<MachineOperand> &Pred2) const { 547 return false; 548 } 549 550 /// DefinesPredicate - If the specified instruction defines any predicate 551 /// or condition code register(s) used for predication, returns true as well 552 /// as the definition predicate(s) by reference. 553 virtual bool DefinesPredicate(MachineInstr *MI, 554 std::vector<MachineOperand> &Pred) const { 555 return false; 556 } 557 558 /// isPredicable - Return true if the specified instruction can be predicated. 559 /// By default, this returns true for every instruction with a 560 /// PredicateOperand. 561 virtual bool isPredicable(MachineInstr *MI) const { 562 return MI->getDesc().isPredicable(); 563 } 564 565 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 566 /// instruction that defines the specified register class. 567 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 568 return true; 569 } 570 571 /// isSchedulingBoundary - Test if the given instruction should be 572 /// considered a scheduling boundary. This primarily includes labels and 573 /// terminators. 574 virtual bool isSchedulingBoundary(const MachineInstr *MI, 575 const MachineBasicBlock *MBB, 576 const MachineFunction &MF) const = 0; 577 578 /// Measure the specified inline asm to determine an approximation of its 579 /// length. 580 virtual unsigned getInlineAsmLength(const char *Str, 581 const MCAsmInfo &MAI) const; 582 583 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer 584 /// to use for this target when scheduling the machine instructions after 585 /// register allocation. 586 virtual ScheduleHazardRecognizer* 587 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const = 0; 588 589 /// AnalyzeCompare - For a comparison instruction, return the source register 590 /// in SrcReg and the value it compares against in CmpValue. Return true if 591 /// the comparison instruction can be analyzed. 592 virtual bool AnalyzeCompare(const MachineInstr *MI, 593 unsigned &SrcReg, int &Mask, int &Value) const { 594 return false; 595 } 596 597 /// OptimizeCompareInstr - See if the comparison instruction can be converted 598 /// into something more efficient. E.g., on ARM most instructions can set the 599 /// flags register, obviating the need for a separate CMP. Update the iterator 600 /// *only* if a transformation took place. 601 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, 602 unsigned SrcReg, int Mask, int Value, 603 MachineBasicBlock::iterator &) const { 604 return false; 605 } 606 607 /// getNumMicroOps - Return the number of u-operations the given machine 608 /// instruction will be decoded to on the target cpu. 609 virtual unsigned getNumMicroOps(const MachineInstr *MI, 610 const InstrItineraryData *ItinData) const; 611}; 612 613/// TargetInstrInfoImpl - This is the default implementation of 614/// TargetInstrInfo, which just provides a couple of default implementations 615/// for various methods. This separated out because it is implemented in 616/// libcodegen, not in libtarget. 617class TargetInstrInfoImpl : public TargetInstrInfo { 618protected: 619 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 620 : TargetInstrInfo(desc, NumOpcodes) {} 621public: 622 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 623 MachineBasicBlock *NewDest) const; 624 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 625 bool NewMI = false) const; 626 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 627 unsigned &SrcOpIdx2) const; 628 virtual bool canFoldMemoryOperand(const MachineInstr *MI, 629 const SmallVectorImpl<unsigned> &Ops) const; 630 virtual bool PredicateInstruction(MachineInstr *MI, 631 const SmallVectorImpl<MachineOperand> &Pred) const; 632 virtual void reMaterialize(MachineBasicBlock &MBB, 633 MachineBasicBlock::iterator MI, 634 unsigned DestReg, unsigned SubReg, 635 const MachineInstr *Orig, 636 const TargetRegisterInfo &TRI) const; 637 virtual MachineInstr *duplicate(MachineInstr *Orig, 638 MachineFunction &MF) const; 639 virtual bool produceSameValue(const MachineInstr *MI0, 640 const MachineInstr *MI1) const; 641 virtual bool isSchedulingBoundary(const MachineInstr *MI, 642 const MachineBasicBlock *MBB, 643 const MachineFunction &MF) const; 644 645 virtual ScheduleHazardRecognizer * 646 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const; 647}; 648 649} // End llvm namespace 650 651#endif 652