TargetInstrInfo.h revision ee9eb411fffddbb8fe70418c05946a131889b487
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class CalleeSavedInfo; 23class LiveVariables; 24class MCAsmInfo; 25class MachineMemOperand; 26class MDNode; 27class MCInst; 28class SDNode; 29class SelectionDAG; 30class TargetRegisterClass; 31class TargetRegisterInfo; 32 33template<class T> class SmallVectorImpl; 34 35 36//--------------------------------------------------------------------------- 37/// 38/// TargetInstrInfo - Interface to description of machine instruction set 39/// 40class TargetInstrInfo { 41 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 42 unsigned NumOpcodes; // Number of entries in the desc array 43 44 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 45 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 46public: 47 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 48 virtual ~TargetInstrInfo(); 49 50 unsigned getNumOpcodes() const { return NumOpcodes; } 51 52 /// get - Return the machine instruction descriptor that corresponds to the 53 /// specified instruction opcode. 54 /// 55 const TargetInstrDesc &get(unsigned Opcode) const { 56 assert(Opcode < NumOpcodes && "Invalid opcode!"); 57 return Descriptors[Opcode]; 58 } 59 60 /// isTriviallyReMaterializable - Return true if the instruction is trivially 61 /// rematerializable, meaning it has no side effects and requires no operands 62 /// that aren't always available. 63 bool isTriviallyReMaterializable(const MachineInstr *MI, 64 AliasAnalysis *AA = 0) const { 65 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 66 (MI->getDesc().isRematerializable() && 67 (isReallyTriviallyReMaterializable(MI, AA) || 68 isReallyTriviallyReMaterializableGeneric(MI, AA))); 69 } 70 71protected: 72 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 73 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 74 /// specify whether the instruction is actually trivially rematerializable, 75 /// taking into consideration its operands. This predicate must return false 76 /// if the instruction has any side effects other than producing a value, or 77 /// if it requres any address registers that are not always available. 78 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 79 AliasAnalysis *AA) const { 80 return false; 81 } 82 83private: 84 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 85 /// for which the M_REMATERIALIZABLE flag is set and the target hook 86 /// isReallyTriviallyReMaterializable returns false, this function does 87 /// target-independent tests to determine if the instruction is really 88 /// trivially rematerializable. 89 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 90 AliasAnalysis *AA) const; 91 92public: 93 /// isMoveInstr - Return true if the instruction is a register to register 94 /// move and return the source and dest operands and their sub-register 95 /// indices by reference. 96 virtual bool isMoveInstr(const MachineInstr& MI, 97 unsigned& SrcReg, unsigned& DstReg, 98 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 99 return false; 100 } 101 102 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 103 /// extension instruction. That is, it's like a copy where it's legal for the 104 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 105 /// true, then it's expected the pre-extension value is available as a subreg 106 /// of the result register. This also returns the sub-register index in 107 /// SubIdx. 108 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 109 unsigned &SrcReg, unsigned &DstReg, 110 unsigned &SubIdx) const { 111 return false; 112 } 113 114 /// isIdentityCopy - Return true if the instruction is a copy (or 115 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 116 /// destination registers are the same. 117 bool isIdentityCopy(const MachineInstr &MI) const { 118 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 119 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 120 SrcReg == DstReg) 121 return true; 122 123 if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG && 124 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 125 return true; 126 127 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG || 128 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) && 129 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 130 return true; 131 return false; 132 } 133 134 /// isLoadFromStackSlot - If the specified machine instruction is a direct 135 /// load from a stack slot, return the virtual or physical register number of 136 /// the destination along with the FrameIndex of the loaded stack slot. If 137 /// not, return 0. This predicate must return 0 if the instruction has 138 /// any side effects other than loading from the stack slot. 139 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 140 int &FrameIndex) const { 141 return 0; 142 } 143 144 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 145 /// stack locations as well. This uses a heuristic so it isn't 146 /// reliable for correctness. 147 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 148 int &FrameIndex) const { 149 return 0; 150 } 151 152 /// hasLoadFromStackSlot - If the specified machine instruction has 153 /// a load from a stack slot, return true along with the FrameIndex 154 /// of the loaded stack slot and the machine mem operand containing 155 /// the reference. If not, return false. Unlike 156 /// isLoadFromStackSlot, this returns true for any instructions that 157 /// loads from the stack. This is just a hint, as some cases may be 158 /// missed. 159 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 160 const MachineMemOperand *&MMO, 161 int &FrameIndex) const { 162 return 0; 163 } 164 165 /// isStoreToStackSlot - If the specified machine instruction is a direct 166 /// store to a stack slot, return the virtual or physical register number of 167 /// the source reg along with the FrameIndex of the loaded stack slot. If 168 /// not, return 0. This predicate must return 0 if the instruction has 169 /// any side effects other than storing to the stack slot. 170 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 171 int &FrameIndex) const { 172 return 0; 173 } 174 175 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 176 /// stack locations as well. This uses a heuristic so it isn't 177 /// reliable for correctness. 178 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 179 int &FrameIndex) const { 180 return 0; 181 } 182 183 /// hasStoreToStackSlot - If the specified machine instruction has a 184 /// store to a stack slot, return true along with the FrameIndex of 185 /// the loaded stack slot and the machine mem operand containing the 186 /// reference. If not, return false. Unlike isStoreToStackSlot, 187 /// this returns true for any instructions that stores to the 188 /// stack. This is just a hint, as some cases may be missed. 189 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 190 const MachineMemOperand *&MMO, 191 int &FrameIndex) const { 192 return 0; 193 } 194 195 /// reMaterialize - Re-issue the specified 'original' instruction at the 196 /// specific location targeting a new destination register. 197 virtual void reMaterialize(MachineBasicBlock &MBB, 198 MachineBasicBlock::iterator MI, 199 unsigned DestReg, unsigned SubIdx, 200 const MachineInstr *Orig, 201 const TargetRegisterInfo *TRI) const = 0; 202 203 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 204 /// MachineFunction::CloneMachineInstr(), but the target may update operands 205 /// that are required to be unique. 206 /// 207 /// The instruction must be duplicable as indicated by isNotDuplicable(). 208 virtual MachineInstr *duplicate(MachineInstr *Orig, 209 MachineFunction &MF) const = 0; 210 211 /// convertToThreeAddress - This method must be implemented by targets that 212 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 213 /// may be able to convert a two-address instruction into one or more true 214 /// three-address instructions on demand. This allows the X86 target (for 215 /// example) to convert ADD and SHL instructions into LEA instructions if they 216 /// would require register copies due to two-addressness. 217 /// 218 /// This method returns a null pointer if the transformation cannot be 219 /// performed, otherwise it returns the last new instruction. 220 /// 221 virtual MachineInstr * 222 convertToThreeAddress(MachineFunction::iterator &MFI, 223 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 224 return 0; 225 } 226 227 /// commuteInstruction - If a target has any instructions that are commutable, 228 /// but require converting to a different instruction or making non-trivial 229 /// changes to commute them, this method can overloaded to do this. The 230 /// default implementation of this method simply swaps the first two operands 231 /// of MI and returns it. 232 /// 233 /// If a target wants to make more aggressive changes, they can construct and 234 /// return a new machine instruction. If an instruction cannot commute, it 235 /// can also return null. 236 /// 237 /// If NewMI is true, then a new machine instruction must be created. 238 /// 239 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 240 bool NewMI = false) const = 0; 241 242 /// findCommutedOpIndices - If specified MI is commutable, return the two 243 /// operand indices that would swap value. Return true if the instruction 244 /// is not in a form which this routine understands. 245 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 246 unsigned &SrcOpIdx2) const = 0; 247 248 /// produceSameValue - Return true if two machine instructions would produce 249 /// identical values. By default, this is only true when the two instructions 250 /// are deemed identical except for defs. 251 virtual bool produceSameValue(const MachineInstr *MI0, 252 const MachineInstr *MI1) const = 0; 253 254 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 255 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 256 /// implemented for a target). Upon success, this returns false and returns 257 /// with the following information in various cases: 258 /// 259 /// 1. If this block ends with no branches (it just falls through to its succ) 260 /// just return false, leaving TBB/FBB null. 261 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 262 /// the destination block. 263 /// 3. If this block ends with a conditional branch and it falls through to a 264 /// successor block, it sets TBB to be the branch destination block and a 265 /// list of operands that evaluate the condition. These operands can be 266 /// passed to other TargetInstrInfo methods to create new branches. 267 /// 4. If this block ends with a conditional branch followed by an 268 /// unconditional branch, it returns the 'true' destination in TBB, the 269 /// 'false' destination in FBB, and a list of operands that evaluate the 270 /// condition. These operands can be passed to other TargetInstrInfo 271 /// methods to create new branches. 272 /// 273 /// Note that RemoveBranch and InsertBranch must be implemented to support 274 /// cases where this method returns success. 275 /// 276 /// If AllowModify is true, then this routine is allowed to modify the basic 277 /// block (e.g. delete instructions after the unconditional branch). 278 /// 279 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 280 MachineBasicBlock *&FBB, 281 SmallVectorImpl<MachineOperand> &Cond, 282 bool AllowModify = false) const { 283 return true; 284 } 285 286 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 287 /// This is only invoked in cases where AnalyzeBranch returns success. It 288 /// returns the number of instructions that were removed. 289 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 290 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 291 return 0; 292 } 293 294 /// InsertBranch - Insert branch code into the end of the specified 295 /// MachineBasicBlock. The operands to this method are the same as those 296 /// returned by AnalyzeBranch. This is only invoked in cases where 297 /// AnalyzeBranch returns success. It returns the number of instructions 298 /// inserted. 299 /// 300 /// It is also invoked by tail merging to add unconditional branches in 301 /// cases where AnalyzeBranch doesn't apply because there was no original 302 /// branch to analyze. At least this much must be implemented, else tail 303 /// merging needs to be disabled. 304 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 305 MachineBasicBlock *FBB, 306 const SmallVectorImpl<MachineOperand> &Cond) const { 307 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 308 return 0; 309 } 310 311 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 312 /// returns false if the target does not how to copy between the specified 313 /// registers. 314 virtual bool copyRegToReg(MachineBasicBlock &MBB, 315 MachineBasicBlock::iterator MI, 316 unsigned DestReg, unsigned SrcReg, 317 const TargetRegisterClass *DestRC, 318 const TargetRegisterClass *SrcRC) const { 319 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 320 return false; 321 } 322 323 /// storeRegToStackSlot - Store the specified register of the given register 324 /// class to the specified stack frame index. The store instruction is to be 325 /// added to the given machine basic block before the specified machine 326 /// instruction. If isKill is true, the register operand is the last use and 327 /// must be marked kill. 328 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 329 MachineBasicBlock::iterator MI, 330 unsigned SrcReg, bool isKill, int FrameIndex, 331 const TargetRegisterClass *RC) const { 332 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 333 } 334 335 /// loadRegFromStackSlot - Load the specified register of the given register 336 /// class from the specified stack frame index. The load instruction is to be 337 /// added to the given machine basic block before the specified machine 338 /// instruction. 339 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 340 MachineBasicBlock::iterator MI, 341 unsigned DestReg, int FrameIndex, 342 const TargetRegisterClass *RC) const { 343 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 344 } 345 346 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 347 /// saved registers and returns true if it isn't possible / profitable to do 348 /// so by issuing a series of store instructions via 349 /// storeRegToStackSlot(). Returns false otherwise. 350 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 351 MachineBasicBlock::iterator MI, 352 const std::vector<CalleeSavedInfo> &CSI) const { 353 return false; 354 } 355 356 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 357 /// saved registers and returns true if it isn't possible / profitable to do 358 /// so by issuing a series of load instructions via loadRegToStackSlot(). 359 /// Returns false otherwise. 360 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 361 MachineBasicBlock::iterator MI, 362 const std::vector<CalleeSavedInfo> &CSI) const { 363 return false; 364 } 365 366 /// emitFrameIndexDebugValue - Emit a target-dependent form of 367 /// DBG_VALUE encoding the address of a frame index. Addresses would 368 /// normally be lowered the same way as other addresses on the target, 369 /// e.g. in load instructions. For targets that do not support this 370 /// the debug info is simply lost. 371 /// If you add this for a target you should handle this DBG_VALUE in the 372 /// target-specific AsmPrinter code as well; you will probably get invalid 373 /// assembly output if you don't. 374 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 375 unsigned FrameIx, 376 uint64_t Offset, 377 const MDNode *MDPtr, 378 DebugLoc dl) const { 379 return 0; 380 } 381 382 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 383 /// slot into the specified machine instruction for the specified operand(s). 384 /// If this is possible, a new instruction is returned with the specified 385 /// operand folded, otherwise NULL is returned. The client is responsible for 386 /// removing the old instruction and adding the new one in the instruction 387 /// stream. 388 MachineInstr* foldMemoryOperand(MachineFunction &MF, 389 MachineInstr* MI, 390 const SmallVectorImpl<unsigned> &Ops, 391 int FrameIndex) const; 392 393 /// foldMemoryOperand - Same as the previous version except it allows folding 394 /// of any load and store from / to any address, not just from a specific 395 /// stack slot. 396 MachineInstr* foldMemoryOperand(MachineFunction &MF, 397 MachineInstr* MI, 398 const SmallVectorImpl<unsigned> &Ops, 399 MachineInstr* LoadMI) const; 400 401protected: 402 /// foldMemoryOperandImpl - Target-dependent implementation for 403 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 404 /// take care of adding a MachineMemOperand to the newly created instruction. 405 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 406 MachineInstr* MI, 407 const SmallVectorImpl<unsigned> &Ops, 408 int FrameIndex) const { 409 return 0; 410 } 411 412 /// foldMemoryOperandImpl - Target-dependent implementation for 413 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 414 /// take care of adding a MachineMemOperand to the newly created instruction. 415 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 416 MachineInstr* MI, 417 const SmallVectorImpl<unsigned> &Ops, 418 MachineInstr* LoadMI) const { 419 return 0; 420 } 421 422public: 423 /// canFoldMemoryOperand - Returns true for the specified load / store if 424 /// folding is possible. 425 virtual 426 bool canFoldMemoryOperand(const MachineInstr *MI, 427 const SmallVectorImpl<unsigned> &Ops) const { 428 return false; 429 } 430 431 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 432 /// a store or a load and a store into two or more instruction. If this is 433 /// possible, returns true as well as the new instructions by reference. 434 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 435 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 436 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 437 return false; 438 } 439 440 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 441 SmallVectorImpl<SDNode*> &NewNodes) const { 442 return false; 443 } 444 445 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 446 /// instruction after load / store are unfolded from an instruction of the 447 /// specified opcode. It returns zero if the specified unfolding is not 448 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 449 /// index of the operand which will hold the register holding the loaded 450 /// value. 451 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 452 bool UnfoldLoad, bool UnfoldStore, 453 unsigned *LoadRegIndex = 0) const { 454 return 0; 455 } 456 457 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 458 /// to determine if two loads are loading from the same base address. It 459 /// should only return true if the base pointers are the same and the 460 /// only differences between the two addresses are the offset. It also returns 461 /// the offsets by reference. 462 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 463 int64_t &Offset1, int64_t &Offset2) const { 464 return false; 465 } 466 467 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 468 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 469 /// be scheduled togther. On some targets if two loads are loading from 470 /// addresses in the same cache line, it's better if they are scheduled 471 /// together. This function takes two integers that represent the load offsets 472 /// from the common base address. It returns true if it decides it's desirable 473 /// to schedule the two loads together. "NumLoads" is the number of loads that 474 /// have already been scheduled after Load1. 475 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 476 int64_t Offset1, int64_t Offset2, 477 unsigned NumLoads) const { 478 return false; 479 } 480 481 /// ReverseBranchCondition - Reverses the branch condition of the specified 482 /// condition list, returning false on success and true if it cannot be 483 /// reversed. 484 virtual 485 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 486 return true; 487 } 488 489 /// insertNoop - Insert a noop into the instruction stream at the specified 490 /// point. 491 virtual void insertNoop(MachineBasicBlock &MBB, 492 MachineBasicBlock::iterator MI) const; 493 494 495 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 496 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 497 // Default to just using 'nop' string. 498 } 499 500 501 /// isPredicated - Returns true if the instruction is already predicated. 502 /// 503 virtual bool isPredicated(const MachineInstr *MI) const { 504 return false; 505 } 506 507 /// isUnpredicatedTerminator - Returns true if the instruction is a 508 /// terminator instruction that has not been predicated. 509 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 510 511 /// PredicateInstruction - Convert the instruction into a predicated 512 /// instruction. It returns true if the operation was successful. 513 virtual 514 bool PredicateInstruction(MachineInstr *MI, 515 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 516 517 /// SubsumesPredicate - Returns true if the first specified predicate 518 /// subsumes the second, e.g. GE subsumes GT. 519 virtual 520 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 521 const SmallVectorImpl<MachineOperand> &Pred2) const { 522 return false; 523 } 524 525 /// DefinesPredicate - If the specified instruction defines any predicate 526 /// or condition code register(s) used for predication, returns true as well 527 /// as the definition predicate(s) by reference. 528 virtual bool DefinesPredicate(MachineInstr *MI, 529 std::vector<MachineOperand> &Pred) const { 530 return false; 531 } 532 533 /// isPredicable - Return true if the specified instruction can be predicated. 534 /// By default, this returns true for every instruction with a 535 /// PredicateOperand. 536 virtual bool isPredicable(MachineInstr *MI) const { 537 return MI->getDesc().isPredicable(); 538 } 539 540 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 541 /// instruction that defines the specified register class. 542 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 543 return true; 544 } 545 546 /// GetInstSize - Returns the size of the specified Instruction. 547 /// 548 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 549 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 550 return 0; 551 } 552 553 /// GetFunctionSizeInBytes - Returns the size of the specified 554 /// MachineFunction. 555 /// 556 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 557 558 /// Measure the specified inline asm to determine an approximation of its 559 /// length. 560 virtual unsigned getInlineAsmLength(const char *Str, 561 const MCAsmInfo &MAI) const; 562}; 563 564/// TargetInstrInfoImpl - This is the default implementation of 565/// TargetInstrInfo, which just provides a couple of default implementations 566/// for various methods. This separated out because it is implemented in 567/// libcodegen, not in libtarget. 568class TargetInstrInfoImpl : public TargetInstrInfo { 569protected: 570 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 571 : TargetInstrInfo(desc, NumOpcodes) {} 572public: 573 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 574 bool NewMI = false) const; 575 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 576 unsigned &SrcOpIdx2) const; 577 virtual bool PredicateInstruction(MachineInstr *MI, 578 const SmallVectorImpl<MachineOperand> &Pred) const; 579 virtual void reMaterialize(MachineBasicBlock &MBB, 580 MachineBasicBlock::iterator MI, 581 unsigned DestReg, unsigned SubReg, 582 const MachineInstr *Orig, 583 const TargetRegisterInfo *TRI) const; 584 virtual MachineInstr *duplicate(MachineInstr *Orig, 585 MachineFunction &MF) const; 586 virtual bool produceSameValue(const MachineInstr *MI0, 587 const MachineInstr *MI1) const; 588 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 589}; 590 591} // End llvm namespace 592 593#endif 594