TargetInstrInfo.h revision f6d12fbd9cc0355978a739f5ab213eff85b75a19
1//===-- llvm/Target/MachineInstrInstrInfo.h - Instruction Infor ---*-C++-*-===// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===----------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "Support/DataTypes.h" 11#include <vector> 12 13class MachineInstrDescriptor; 14class MachineInstr; 15class TargetMachine; 16class Value; 17class Instruction; 18class Constant; 19class Function; 20class MachineCodeForInstruction; 21 22//--------------------------------------------------------------------------- 23// Data types used to define information about a single machine instruction 24//--------------------------------------------------------------------------- 25 26typedef int MachineOpCode; 27typedef unsigned InstrSchedClass; 28 29const MachineOpCode INVALID_MACHINE_OPCODE = -1; 30 31 32//--------------------------------------------------------------------------- 33// struct MachineInstrDescriptor: 34// Predefined information about each machine instruction. 35// Designed to initialized statically. 36// 37// class MachineInstructionInfo 38// Interface to description of machine instructions 39// 40//--------------------------------------------------------------------------- 41 42const unsigned M_NOP_FLAG = 1 << 0; 43const unsigned M_BRANCH_FLAG = 1 << 1; 44const unsigned M_CALL_FLAG = 1 << 2; 45const unsigned M_RET_FLAG = 1 << 3; 46const unsigned M_ARITH_FLAG = 1 << 4; 47const unsigned M_CC_FLAG = 1 << 6; 48const unsigned M_LOGICAL_FLAG = 1 << 6; 49const unsigned M_INT_FLAG = 1 << 7; 50const unsigned M_FLOAT_FLAG = 1 << 8; 51const unsigned M_CONDL_FLAG = 1 << 9; 52const unsigned M_LOAD_FLAG = 1 << 10; 53const unsigned M_PREFETCH_FLAG = 1 << 11; 54const unsigned M_STORE_FLAG = 1 << 12; 55const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 56const unsigned M_PSEUDO_FLAG = 1 << 14; 57 58 59struct MachineInstrDescriptor { 60 const char * Name; // Assembly language mnemonic for the opcode. 61 int numOperands; // Number of args; -1 if variable #args 62 int resultPos; // Position of the result; -1 if no result 63 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 64 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 65 // smallest -ve value is -(maxImmedConst+1). 66 unsigned numDelaySlots; // Number of delay slots after instruction 67 unsigned latency; // Latency in machine cycles 68 InstrSchedClass schedClass; // enum identifying instr sched class 69 unsigned Flags; // flags identifying machine instr class 70 unsigned TSFlags; // Target Specific Flag values 71 const unsigned *ImplicitUses; // Registers implicitly read by this instr 72 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 73}; 74 75 76class MachineInstrInfo { 77 const MachineInstrDescriptor* desc; // raw array to allow static init'n 78 unsigned descSize; // number of entries in the desc array 79 unsigned numRealOpCodes; // number of non-dummy op codes 80 81 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT 82 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT 83public: 84 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize, 85 unsigned numRealOpCodes); 86 virtual ~MachineInstrInfo(); 87 88 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 89 unsigned getNumTotalOpCodes() const { return descSize; } 90 91 /// get - Return the machine instruction descriptor that corresponds to the 92 /// specified instruction opcode. 93 /// 94 const MachineInstrDescriptor& get(MachineOpCode opCode) const { 95 assert(opCode >= 0 && opCode < (int)descSize); 96 return desc[opCode]; 97 } 98 99 /// print - Print out the specified machine instruction in the appropriate 100 /// target specific assembly language. If this method is not overridden, the 101 /// default implementation uses the crummy machine independant printer. 102 /// 103 virtual void print(const MachineInstr *MI, std::ostream &O, 104 const TargetMachine &TM) const; 105 106 const char *getName(MachineOpCode opCode) const { 107 return get(opCode).Name; 108 } 109 110 int getNumOperands(MachineOpCode opCode) const { 111 return get(opCode).numOperands; 112 } 113 114 int getResultPos(MachineOpCode opCode) const { 115 return get(opCode).resultPos; 116 } 117 118 unsigned getNumDelaySlots(MachineOpCode opCode) const { 119 return get(opCode).numDelaySlots; 120 } 121 122 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 123 return get(opCode).schedClass; 124 } 125 126 // 127 // Query instruction class flags according to the machine-independent 128 // flags listed above. 129 // 130 bool isNop(MachineOpCode opCode) const { 131 return get(opCode).Flags & M_NOP_FLAG; 132 } 133 bool isBranch(MachineOpCode opCode) const { 134 return get(opCode).Flags & M_BRANCH_FLAG; 135 } 136 bool isCall(MachineOpCode opCode) const { 137 return get(opCode).Flags & M_CALL_FLAG; 138 } 139 bool isReturn(MachineOpCode opCode) const { 140 return get(opCode).Flags & M_RET_FLAG; 141 } 142 bool isControlFlow(MachineOpCode opCode) const { 143 return get(opCode).Flags & M_BRANCH_FLAG 144 || get(opCode).Flags & M_CALL_FLAG 145 || get(opCode).Flags & M_RET_FLAG; 146 } 147 bool isArith(MachineOpCode opCode) const { 148 return get(opCode).Flags & M_ARITH_FLAG; 149 } 150 bool isCCInstr(MachineOpCode opCode) const { 151 return get(opCode).Flags & M_CC_FLAG; 152 } 153 bool isLogical(MachineOpCode opCode) const { 154 return get(opCode).Flags & M_LOGICAL_FLAG; 155 } 156 bool isIntInstr(MachineOpCode opCode) const { 157 return get(opCode).Flags & M_INT_FLAG; 158 } 159 bool isFloatInstr(MachineOpCode opCode) const { 160 return get(opCode).Flags & M_FLOAT_FLAG; 161 } 162 bool isConditional(MachineOpCode opCode) const { 163 return get(opCode).Flags & M_CONDL_FLAG; 164 } 165 bool isLoad(MachineOpCode opCode) const { 166 return get(opCode).Flags & M_LOAD_FLAG; 167 } 168 bool isPrefetch(MachineOpCode opCode) const { 169 return get(opCode).Flags & M_PREFETCH_FLAG; 170 } 171 bool isLoadOrPrefetch(MachineOpCode opCode) const { 172 return get(opCode).Flags & M_LOAD_FLAG 173 || get(opCode).Flags & M_PREFETCH_FLAG; 174 } 175 bool isStore(MachineOpCode opCode) const { 176 return get(opCode).Flags & M_STORE_FLAG; 177 } 178 bool isMemoryAccess(MachineOpCode opCode) const { 179 return get(opCode).Flags & M_LOAD_FLAG 180 || get(opCode).Flags & M_PREFETCH_FLAG 181 || get(opCode).Flags & M_STORE_FLAG; 182 } 183 bool isDummyPhiInstr(const MachineOpCode opCode) const { 184 return get(opCode).Flags & M_DUMMY_PHI_FLAG; 185 } 186 bool isPseudoInstr(const MachineOpCode opCode) const { 187 return get(opCode).Flags & M_PSEUDO_FLAG; 188 } 189 190 // Check if an instruction can be issued before its operands are ready, 191 // or if a subsequent instruction that uses its result can be issued 192 // before the results are ready. 193 // Default to true since most instructions on many architectures allow this. 194 // 195 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 196 return true; 197 } 198 199 virtual bool hasResultInterlock(MachineOpCode opCode) const { 200 return true; 201 } 202 203 // 204 // Latencies for individual instructions and instruction pairs 205 // 206 virtual int minLatency(MachineOpCode opCode) const { 207 return get(opCode).latency; 208 } 209 210 virtual int maxLatency(MachineOpCode opCode) const { 211 return get(opCode).latency; 212 } 213 214 // 215 // Which operand holds an immediate constant? Returns -1 if none 216 // 217 virtual int getImmedConstantPos(MachineOpCode opCode) const { 218 return -1; // immediate position is machine specific, so say -1 == "none" 219 } 220 221 // Check if the specified constant fits in the immediate field 222 // of this machine instruction 223 // 224 virtual bool constantFitsInImmedField(MachineOpCode opCode, 225 int64_t intValue) const; 226 227 // Return the largest +ve constant that can be held in the IMMMED field 228 // of this machine instruction. 229 // isSignExtended is set to true if the value is sign-extended before use 230 // (this is true for all immediate fields in SPARC instructions). 231 // Return 0 if the instruction has no IMMED field. 232 // 233 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 234 bool &isSignExtended) const { 235 isSignExtended = get(opCode).immedIsSignExtended; 236 return get(opCode).maxImmedConst; 237 } 238 239 //------------------------------------------------------------------------- 240 // Queries about representation of LLVM quantities (e.g., constants) 241 //------------------------------------------------------------------------- 242 243 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 244 /// from memory into a register, i.e., cannot be set bitwise in register and 245 /// cannot use immediate fields of instructions. Note that this only makes 246 /// sense for primitive types. 247 /// 248 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 249 250 // Test if this constant may not fit in the immediate field of the 251 // machine instructions (probably) generated for this instruction. 252 // 253 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 254 const Instruction* I) const { 255 return true; // safe but very conservative 256 } 257 258 //------------------------------------------------------------------------- 259 // Code generation support for creating individual machine instructions 260 //------------------------------------------------------------------------- 261 262 // Get certain common op codes for the current target. this and all the 263 // Create* methods below should be moved to a machine code generation class 264 // 265 virtual MachineOpCode getNOPOpCode() const = 0; 266 267 // Create an instruction sequence to put the constant `val' into 268 // the virtual register `dest'. `val' may be a Constant or a 269 // GlobalValue, viz., the constant address of a global variable or function. 270 // The generated instructions are returned in `mvec'. 271 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 272 // Symbolic constants or constants that must be accessed from memory 273 // are added to the constant pool via MachineFunction::get(F). 274 // 275 virtual void CreateCodeToLoadConst(const TargetMachine& target, 276 Function* F, 277 Value* val, 278 Instruction* dest, 279 std::vector<MachineInstr*>& mvec, 280 MachineCodeForInstruction& mcfi) const=0; 281 282 // Create an instruction sequence to copy an integer value `val' 283 // to a floating point value `dest' by copying to memory and back. 284 // val must be an integral type. dest must be a Float or Double. 285 // The generated instructions are returned in `mvec'. 286 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 287 // Any stack space required is allocated via mcff. 288 // 289 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 290 Function* F, 291 Value* val, 292 Instruction* dest, 293 std::vector<MachineInstr*>& mvec, 294 MachineCodeForInstruction& mcfi)const=0; 295 296 // Similarly, create an instruction sequence to copy an FP value 297 // `val' to an integer value `dest' by copying to memory and back. 298 // The generated instructions are returned in `mvec'. 299 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 300 // Any stack space required is allocated via mcff. 301 // 302 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 303 Function* F, 304 Value* val, 305 Instruction* dest, 306 std::vector<MachineInstr*>& mvec, 307 MachineCodeForInstruction& mcfi)const=0; 308 309 // Create instruction(s) to copy src to dest, for arbitrary types 310 // The generated instructions are returned in `mvec'. 311 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 312 // Any stack space required is allocated via mcff. 313 // 314 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 315 Function* F, 316 Value* src, 317 Instruction* dest, 318 std::vector<MachineInstr*>& mvec, 319 MachineCodeForInstruction& mcfi)const=0; 320 321 // Create instruction sequence to produce a sign-extended register value 322 // from an arbitrary sized value (sized in bits, not bytes). 323 // The generated instructions are appended to `mvec'. 324 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 325 // Any stack space required is allocated via mcff. 326 // 327 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 328 Function* F, 329 Value* srcVal, 330 Value* destVal, 331 unsigned numLowBits, 332 std::vector<MachineInstr*>& mvec, 333 MachineCodeForInstruction& mcfi) const=0; 334 335 // Create instruction sequence to produce a zero-extended register value 336 // from an arbitrary sized value (sized in bits, not bytes). 337 // The generated instructions are appended to `mvec'. 338 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 339 // Any stack space required is allocated via mcff. 340 // 341 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 342 Function* F, 343 Value* srcVal, 344 Value* destVal, 345 unsigned srcSizeInBits, 346 std::vector<MachineInstr*>& mvec, 347 MachineCodeForInstruction& mcfi) const=0; 348}; 349 350#endif 351