TargetInstrInfo.h revision f8c7394781f7cf27ac52ca087e289436d36844da
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class TargetRegisterClass; 23class LiveVariables; 24class CalleeSavedInfo; 25class SDNode; 26class SelectionDAG; 27 28template<class T> class SmallVectorImpl; 29 30 31//--------------------------------------------------------------------------- 32/// 33/// TargetInstrInfo - Interface to description of machine instruction set 34/// 35class TargetInstrInfo { 36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 37 unsigned NumOpcodes; // Number of entries in the desc array 38 39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 41public: 42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 43 virtual ~TargetInstrInfo(); 44 45 // Invariant opcodes: All instruction sets have these as their low opcodes. 46 enum { 47 PHI = 0, 48 INLINEASM = 1, 49 DBG_LABEL = 2, 50 EH_LABEL = 3, 51 GC_LABEL = 4, 52 DECLARE = 5, 53 54 /// EXTRACT_SUBREG - This instruction takes two operands: a register 55 /// that has subregisters, and a subregister index. It returns the 56 /// extracted subregister value. This is commonly used to implement 57 /// truncation operations on target architectures which support it. 58 EXTRACT_SUBREG = 6, 59 60 /// INSERT_SUBREG - This instruction takes three operands: a register 61 /// that has subregisters, a register providing an insert value, and a 62 /// subregister index. It returns the value of the first register with 63 /// the value of the second register inserted. The first register is 64 /// often defined by an IMPLICIT_DEF, as is commonly used to implement 65 /// anyext operations on target architectures which support it. 66 INSERT_SUBREG = 7, 67 68 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 69 IMPLICIT_DEF = 8, 70 71 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 72 /// that the first operand is an immediate integer constant. This constant 73 /// is often zero, as is commonly used to implement zext operations on 74 /// target architectures which support it, such as with x86-64 (with 75 /// zext from i32 to i64 via implicit zero-extension). 76 SUBREG_TO_REG = 9, 77 78 /// COPY_TO_SUBCLASS - This instruction is a placeholder for a plain 79 /// register-to-register copy into a specific register class. This is only 80 /// used between instruction selection and MachineInstr creation, before 81 /// virtual registers have been created for all the instructions. As with 82 /// normal copies, these may be optimized away by the coalescer. 83 COPY_TO_SUBCLASS = 10 84 }; 85 86 unsigned getNumOpcodes() const { return NumOpcodes; } 87 88 /// get - Return the machine instruction descriptor that corresponds to the 89 /// specified instruction opcode. 90 /// 91 const TargetInstrDesc &get(unsigned Opcode) const { 92 assert(Opcode < NumOpcodes && "Invalid opcode!"); 93 return Descriptors[Opcode]; 94 } 95 96 /// isTriviallyReMaterializable - Return true if the instruction is trivially 97 /// rematerializable, meaning it has no side effects and requires no operands 98 /// that aren't always available. 99 bool isTriviallyReMaterializable(const MachineInstr *MI) const { 100 return MI->getDesc().isRematerializable() && 101 isReallyTriviallyReMaterializable(MI); 102 } 103 104protected: 105 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 106 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 107 /// instruction itself is actually trivially rematerializable, considering 108 /// its operands. This is used for targets that have instructions that are 109 /// only trivially rematerializable for specific uses. This predicate must 110 /// return false if the instruction has any side effects other than 111 /// producing a value, or if it requres any address registers that are not 112 /// always available. 113 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 114 return true; 115 } 116 117public: 118 /// Return true if the instruction is a register to register move and return 119 /// the source and dest operands and their sub-register indices by reference. 120 virtual bool isMoveInstr(const MachineInstr& MI, 121 unsigned& SrcReg, unsigned& DstReg, 122 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 123 return false; 124 } 125 126 /// isLoadFromStackSlot - If the specified machine instruction is a direct 127 /// load from a stack slot, return the virtual or physical register number of 128 /// the destination along with the FrameIndex of the loaded stack slot. If 129 /// not, return 0. This predicate must return 0 if the instruction has 130 /// any side effects other than loading from the stack slot. 131 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 132 int &FrameIndex) const { 133 return 0; 134 } 135 136 /// isStoreToStackSlot - If the specified machine instruction is a direct 137 /// store to a stack slot, return the virtual or physical register number of 138 /// the source reg along with the FrameIndex of the loaded stack slot. If 139 /// not, return 0. This predicate must return 0 if the instruction has 140 /// any side effects other than storing to the stack slot. 141 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 142 int &FrameIndex) const { 143 return 0; 144 } 145 146 /// reMaterialize - Re-issue the specified 'original' instruction at the 147 /// specific location targeting a new destination register. 148 virtual void reMaterialize(MachineBasicBlock &MBB, 149 MachineBasicBlock::iterator MI, 150 unsigned DestReg, 151 const MachineInstr *Orig) const = 0; 152 153 /// isInvariantLoad - Return true if the specified instruction (which is 154 /// marked mayLoad) is loading from a location whose value is invariant across 155 /// the function. For example, loading a value from the constant pool or from 156 /// from the argument area of a function if it does not change. This should 157 /// only return true of *all* loads the instruction does are invariant (if it 158 /// does multiple loads). 159 virtual bool isInvariantLoad(const MachineInstr *MI) const { 160 return false; 161 } 162 163 /// convertToThreeAddress - This method must be implemented by targets that 164 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 165 /// may be able to convert a two-address instruction into one or more true 166 /// three-address instructions on demand. This allows the X86 target (for 167 /// example) to convert ADD and SHL instructions into LEA instructions if they 168 /// would require register copies due to two-addressness. 169 /// 170 /// This method returns a null pointer if the transformation cannot be 171 /// performed, otherwise it returns the last new instruction. 172 /// 173 virtual MachineInstr * 174 convertToThreeAddress(MachineFunction::iterator &MFI, 175 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 176 return 0; 177 } 178 179 /// commuteInstruction - If a target has any instructions that are commutable, 180 /// but require converting to a different instruction or making non-trivial 181 /// changes to commute them, this method can overloaded to do this. The 182 /// default implementation of this method simply swaps the first two operands 183 /// of MI and returns it. 184 /// 185 /// If a target wants to make more aggressive changes, they can construct and 186 /// return a new machine instruction. If an instruction cannot commute, it 187 /// can also return null. 188 /// 189 /// If NewMI is true, then a new machine instruction must be created. 190 /// 191 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 192 bool NewMI = false) const = 0; 193 194 /// CommuteChangesDestination - Return true if commuting the specified 195 /// instruction will also changes the destination operand. Also return the 196 /// current operand index of the would be new destination register by 197 /// reference. This can happen when the commutable instruction is also a 198 /// two-address instruction. 199 virtual bool CommuteChangesDestination(MachineInstr *MI, 200 unsigned &OpIdx) const = 0; 201 202 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 203 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 204 /// implemented for a target). Upon success, this returns false and returns 205 /// with the following information in various cases: 206 /// 207 /// 1. If this block ends with no branches (it just falls through to its succ) 208 /// just return false, leaving TBB/FBB null. 209 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 210 /// the destination block. 211 /// 3. If this block ends with an conditional branch and it falls through to 212 /// an successor block, it sets TBB to be the branch destination block and 213 /// a list of operands that evaluate the condition. These 214 /// operands can be passed to other TargetInstrInfo methods to create new 215 /// branches. 216 /// 4. If this block ends with an conditional branch and an unconditional 217 /// block, it returns the 'true' destination in TBB, the 'false' 218 /// destination in FBB, and a list of operands that evaluate the condition. 219 /// These operands can be passed to other TargetInstrInfo methods to create 220 /// new branches. 221 /// 222 /// Note that RemoveBranch and InsertBranch must be implemented to support 223 /// cases where this method returns success. 224 /// 225 /// If AllowModify is true, then this routine is allowed to modify the basic 226 /// block (e.g. delete instructions after the unconditional branch). 227 /// 228 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 229 MachineBasicBlock *&FBB, 230 SmallVectorImpl<MachineOperand> &Cond, 231 bool AllowModify = false) const { 232 return true; 233 } 234 235 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 236 /// This is only invoked in cases where AnalyzeBranch returns success. It 237 /// returns the number of instructions that were removed. 238 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 239 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 240 return 0; 241 } 242 243 /// InsertBranch - Insert a branch into the end of the specified 244 /// MachineBasicBlock. This operands to this method are the same as those 245 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 246 /// returns success and when an unconditional branch (TBB is non-null, FBB is 247 /// null, Cond is empty) needs to be inserted. It returns the number of 248 /// instructions inserted. 249 /// 250 /// It is also invoked by tail merging to add unconditional branches in 251 /// cases where AnalyzeBranch doesn't apply because there was no original 252 /// branch to analyze. At least this much must be implemented, else tail 253 /// merging needs to be disabled. 254 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 255 MachineBasicBlock *FBB, 256 const SmallVectorImpl<MachineOperand> &Cond) const { 257 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 258 return 0; 259 } 260 261 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 262 /// returns false if the target does not how to copy between the specified 263 /// registers. 264 virtual bool copyRegToReg(MachineBasicBlock &MBB, 265 MachineBasicBlock::iterator MI, 266 unsigned DestReg, unsigned SrcReg, 267 const TargetRegisterClass *DestRC, 268 const TargetRegisterClass *SrcRC) const { 269 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 270 return false; 271 } 272 273 /// storeRegToStackSlot - Store the specified register of the given register 274 /// class to the specified stack frame index. The store instruction is to be 275 /// added to the given machine basic block before the specified machine 276 /// instruction. If isKill is true, the register operand is the last use and 277 /// must be marked kill. 278 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 279 MachineBasicBlock::iterator MI, 280 unsigned SrcReg, bool isKill, int FrameIndex, 281 const TargetRegisterClass *RC) const { 282 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 283 } 284 285 /// storeRegToAddr - Store the specified register of the given register class 286 /// to the specified address. The store instruction is to be added to the 287 /// given machine basic block before the specified machine instruction. If 288 /// isKill is true, the register operand is the last use and must be marked 289 /// kill. 290 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 291 SmallVectorImpl<MachineOperand> &Addr, 292 const TargetRegisterClass *RC, 293 SmallVectorImpl<MachineInstr*> &NewMIs) const { 294 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 295 } 296 297 /// loadRegFromStackSlot - Load the specified register of the given register 298 /// class from the specified stack frame index. The load instruction is to be 299 /// added to the given machine basic block before the specified machine 300 /// instruction. 301 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 302 MachineBasicBlock::iterator MI, 303 unsigned DestReg, int FrameIndex, 304 const TargetRegisterClass *RC) const { 305 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 306 } 307 308 /// loadRegFromAddr - Load the specified register of the given register class 309 /// class from the specified address. The load instruction is to be added to 310 /// the given machine basic block before the specified machine instruction. 311 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 312 SmallVectorImpl<MachineOperand> &Addr, 313 const TargetRegisterClass *RC, 314 SmallVectorImpl<MachineInstr*> &NewMIs) const { 315 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 316 } 317 318 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 319 /// saved registers and returns true if it isn't possible / profitable to do 320 /// so by issuing a series of store instructions via 321 /// storeRegToStackSlot(). Returns false otherwise. 322 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 323 MachineBasicBlock::iterator MI, 324 const std::vector<CalleeSavedInfo> &CSI) const { 325 return false; 326 } 327 328 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 329 /// saved registers and returns true if it isn't possible / profitable to do 330 /// so by issuing a series of load instructions via loadRegToStackSlot(). 331 /// Returns false otherwise. 332 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 333 MachineBasicBlock::iterator MI, 334 const std::vector<CalleeSavedInfo> &CSI) const { 335 return false; 336 } 337 338 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 339 /// slot into the specified machine instruction for the specified operand(s). 340 /// If this is possible, a new instruction is returned with the specified 341 /// operand folded, otherwise NULL is returned. The client is responsible for 342 /// removing the old instruction and adding the new one in the instruction 343 /// stream. 344 MachineInstr* foldMemoryOperand(MachineFunction &MF, 345 MachineInstr* MI, 346 const SmallVectorImpl<unsigned> &Ops, 347 int FrameIndex) const; 348 349 /// foldMemoryOperand - Same as the previous version except it allows folding 350 /// of any load and store from / to any address, not just from a specific 351 /// stack slot. 352 MachineInstr* foldMemoryOperand(MachineFunction &MF, 353 MachineInstr* MI, 354 const SmallVectorImpl<unsigned> &Ops, 355 MachineInstr* LoadMI) const; 356 357protected: 358 /// foldMemoryOperandImpl - Target-dependent implementation for 359 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 360 /// take care of adding a MachineMemOperand to the newly created instruction. 361 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 362 MachineInstr* MI, 363 const SmallVectorImpl<unsigned> &Ops, 364 int FrameIndex) const { 365 return 0; 366 } 367 368 /// foldMemoryOperandImpl - Target-dependent implementation for 369 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 370 /// take care of adding a MachineMemOperand to the newly created instruction. 371 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 372 MachineInstr* MI, 373 const SmallVectorImpl<unsigned> &Ops, 374 MachineInstr* LoadMI) const { 375 return 0; 376 } 377 378public: 379 /// canFoldMemoryOperand - Returns true for the specified load / store if 380 /// folding is possible. 381 virtual 382 bool canFoldMemoryOperand(const MachineInstr *MI, 383 const SmallVectorImpl<unsigned> &Ops) const { 384 return false; 385 } 386 387 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 388 /// a store or a load and a store into two or more instruction. If this is 389 /// possible, returns true as well as the new instructions by reference. 390 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 391 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 392 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 393 return false; 394 } 395 396 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 397 SmallVectorImpl<SDNode*> &NewNodes) const { 398 return false; 399 } 400 401 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 402 /// instruction after load / store are unfolded from an instruction of the 403 /// specified opcode. It returns zero if the specified unfolding is not 404 /// possible. 405 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 406 bool UnfoldLoad, bool UnfoldStore) const { 407 return 0; 408 } 409 410 /// BlockHasNoFallThrough - Return true if the specified block does not 411 /// fall-through into its successor block. This is primarily used when a 412 /// branch is unanalyzable. It is useful for things like unconditional 413 /// indirect branches (jump tables). 414 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 415 return false; 416 } 417 418 /// ReverseBranchCondition - Reverses the branch condition of the specified 419 /// condition list, returning false on success and true if it cannot be 420 /// reversed. 421 virtual 422 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 423 return true; 424 } 425 426 /// insertNoop - Insert a noop into the instruction stream at the specified 427 /// point. 428 virtual void insertNoop(MachineBasicBlock &MBB, 429 MachineBasicBlock::iterator MI) const { 430 assert(0 && "Target didn't implement insertNoop!"); 431 abort(); 432 } 433 434 /// isPredicated - Returns true if the instruction is already predicated. 435 /// 436 virtual bool isPredicated(const MachineInstr *MI) const { 437 return false; 438 } 439 440 /// isUnpredicatedTerminator - Returns true if the instruction is a 441 /// terminator instruction that has not been predicated. 442 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 443 444 /// PredicateInstruction - Convert the instruction into a predicated 445 /// instruction. It returns true if the operation was successful. 446 virtual 447 bool PredicateInstruction(MachineInstr *MI, 448 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 449 450 /// SubsumesPredicate - Returns true if the first specified predicate 451 /// subsumes the second, e.g. GE subsumes GT. 452 virtual 453 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 454 const SmallVectorImpl<MachineOperand> &Pred2) const { 455 return false; 456 } 457 458 /// DefinesPredicate - If the specified instruction defines any predicate 459 /// or condition code register(s) used for predication, returns true as well 460 /// as the definition predicate(s) by reference. 461 virtual bool DefinesPredicate(MachineInstr *MI, 462 std::vector<MachineOperand> &Pred) const { 463 return false; 464 } 465 466 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 467 /// instruction that defines the specified register class. 468 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 469 return true; 470 } 471 472 /// GetInstSize - Returns the size of the specified Instruction. 473 /// 474 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 475 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 476 return 0; 477 } 478 479 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction. 480 /// 481 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 482}; 483 484/// TargetInstrInfoImpl - This is the default implementation of 485/// TargetInstrInfo, which just provides a couple of default implementations 486/// for various methods. This separated out because it is implemented in 487/// libcodegen, not in libtarget. 488class TargetInstrInfoImpl : public TargetInstrInfo { 489protected: 490 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 491 : TargetInstrInfo(desc, NumOpcodes) {} 492public: 493 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 494 bool NewMI = false) const; 495 virtual bool CommuteChangesDestination(MachineInstr *MI, 496 unsigned &OpIdx) const; 497 virtual bool PredicateInstruction(MachineInstr *MI, 498 const SmallVectorImpl<MachineOperand> &Pred) const; 499 virtual void reMaterialize(MachineBasicBlock &MBB, 500 MachineBasicBlock::iterator MI, 501 unsigned DestReg, 502 const MachineInstr *Orig) const; 503 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 504}; 505 506} // End llvm namespace 507 508#endif 509