TargetInstrInfo.h revision fe30dd3f2390c26fe1f83868cd57a1e6b27d3075
1//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===---------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "Support/DataTypes.h" 11#include <vector> 12 13class MachineInstrDescriptor; 14class MachineInstr; 15class TargetMachine; 16class Value; 17class Instruction; 18class Constant; 19class Function; 20class MachineCodeForInstruction; 21 22//--------------------------------------------------------------------------- 23// Data types used to define information about a single machine instruction 24//--------------------------------------------------------------------------- 25 26typedef int MachineOpCode; 27typedef unsigned InstrSchedClass; 28 29const MachineOpCode INVALID_MACHINE_OPCODE = -1; 30 31 32//--------------------------------------------------------------------------- 33// struct MachineInstrDescriptor: 34// Predefined information about each machine instruction. 35// Designed to initialized statically. 36// 37// class MachineInstructionInfo 38// Interface to description of machine instructions 39// 40//--------------------------------------------------------------------------- 41 42const unsigned M_NOP_FLAG = 1 << 0; 43const unsigned M_BRANCH_FLAG = 1 << 1; 44const unsigned M_CALL_FLAG = 1 << 2; 45const unsigned M_RET_FLAG = 1 << 3; 46const unsigned M_ARITH_FLAG = 1 << 4; 47const unsigned M_CC_FLAG = 1 << 6; 48const unsigned M_LOGICAL_FLAG = 1 << 6; 49const unsigned M_INT_FLAG = 1 << 7; 50const unsigned M_FLOAT_FLAG = 1 << 8; 51const unsigned M_CONDL_FLAG = 1 << 9; 52const unsigned M_LOAD_FLAG = 1 << 10; 53const unsigned M_PREFETCH_FLAG = 1 << 11; 54const unsigned M_STORE_FLAG = 1 << 12; 55const unsigned M_DUMMY_PHI_FLAG = 1 << 13; 56const unsigned M_PSEUDO_FLAG = 1 << 14; 57 58 59struct MachineInstrDescriptor { 60 const char * Name; // Assembly language mnemonic for the opcode. 61 int numOperands; // Number of args; -1 if variable #args 62 int resultPos; // Position of the result; -1 if no result 63 unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 64 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 65 // smallest -ve value is -(maxImmedConst+1). 66 unsigned numDelaySlots; // Number of delay slots after instruction 67 unsigned latency; // Latency in machine cycles 68 InstrSchedClass schedClass; // enum identifying instr sched class 69 unsigned Flags; // flags identifying machine instr class 70 unsigned TSFlags; // Target Specific Flag values 71}; 72 73 74class MachineInstrInfo { 75 const MachineInstrDescriptor* desc; // raw array to allow static init'n 76 unsigned descSize; // number of entries in the desc array 77 unsigned numRealOpCodes; // number of non-dummy op codes 78 79 MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT 80 void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT 81public: 82 MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize, 83 unsigned numRealOpCodes); 84 virtual ~MachineInstrInfo(); 85 86 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 87 unsigned getNumTotalOpCodes() const { return descSize; } 88 89 /// get - Return the machine instruction descriptor that corresponds to the 90 /// specified instruction opcode. 91 /// 92 const MachineInstrDescriptor& get(MachineOpCode opCode) const { 93 assert(opCode >= 0 && opCode < (int)descSize); 94 return desc[opCode]; 95 } 96 97 /// print - Print out the specified machine instruction in the appropriate 98 /// target specific assembly language. If this method is not overridden, the 99 /// default implementation uses the crummy machine independant printer. 100 /// 101 virtual void print(const MachineInstr *MI, std::ostream &O, 102 const TargetMachine &TM) const; 103 104 const char *getName(MachineOpCode opCode) const { 105 return get(opCode).Name; 106 } 107 108 int getNumOperands(MachineOpCode opCode) const { 109 return get(opCode).numOperands; 110 } 111 112 int getResultPos(MachineOpCode opCode) const { 113 return get(opCode).resultPos; 114 } 115 116 unsigned getNumDelaySlots(MachineOpCode opCode) const { 117 return get(opCode).numDelaySlots; 118 } 119 120 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 121 return get(opCode).schedClass; 122 } 123 124 // 125 // Query instruction class flags according to the machine-independent 126 // flags listed above. 127 // 128 bool isNop(MachineOpCode opCode) const { 129 return get(opCode).Flags & M_NOP_FLAG; 130 } 131 bool isBranch(MachineOpCode opCode) const { 132 return get(opCode).Flags & M_BRANCH_FLAG; 133 } 134 bool isCall(MachineOpCode opCode) const { 135 return get(opCode).Flags & M_CALL_FLAG; 136 } 137 bool isReturn(MachineOpCode opCode) const { 138 return get(opCode).Flags & M_RET_FLAG; 139 } 140 bool isControlFlow(MachineOpCode opCode) const { 141 return get(opCode).Flags & M_BRANCH_FLAG 142 || get(opCode).Flags & M_CALL_FLAG 143 || get(opCode).Flags & M_RET_FLAG; 144 } 145 bool isArith(MachineOpCode opCode) const { 146 return get(opCode).Flags & M_ARITH_FLAG; 147 } 148 bool isCCInstr(MachineOpCode opCode) const { 149 return get(opCode).Flags & M_CC_FLAG; 150 } 151 bool isLogical(MachineOpCode opCode) const { 152 return get(opCode).Flags & M_LOGICAL_FLAG; 153 } 154 bool isIntInstr(MachineOpCode opCode) const { 155 return get(opCode).Flags & M_INT_FLAG; 156 } 157 bool isFloatInstr(MachineOpCode opCode) const { 158 return get(opCode).Flags & M_FLOAT_FLAG; 159 } 160 bool isConditional(MachineOpCode opCode) const { 161 return get(opCode).Flags & M_CONDL_FLAG; 162 } 163 bool isLoad(MachineOpCode opCode) const { 164 return get(opCode).Flags & M_LOAD_FLAG; 165 } 166 bool isPrefetch(MachineOpCode opCode) const { 167 return get(opCode).Flags & M_PREFETCH_FLAG; 168 } 169 bool isLoadOrPrefetch(MachineOpCode opCode) const { 170 return get(opCode).Flags & M_LOAD_FLAG 171 || get(opCode).Flags & M_PREFETCH_FLAG; 172 } 173 bool isStore(MachineOpCode opCode) const { 174 return get(opCode).Flags & M_STORE_FLAG; 175 } 176 bool isMemoryAccess(MachineOpCode opCode) const { 177 return get(opCode).Flags & M_LOAD_FLAG 178 || get(opCode).Flags & M_PREFETCH_FLAG 179 || get(opCode).Flags & M_STORE_FLAG; 180 } 181 bool isDummyPhiInstr(const MachineOpCode opCode) const { 182 return get(opCode).Flags & M_DUMMY_PHI_FLAG; 183 } 184 bool isPseudoInstr(const MachineOpCode opCode) const { 185 return get(opCode).Flags & M_PSEUDO_FLAG; 186 } 187 188 // Check if an instruction can be issued before its operands are ready, 189 // or if a subsequent instruction that uses its result can be issued 190 // before the results are ready. 191 // Default to true since most instructions on many architectures allow this. 192 // 193 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 194 return true; 195 } 196 197 virtual bool hasResultInterlock(MachineOpCode opCode) const { 198 return true; 199 } 200 201 // 202 // Latencies for individual instructions and instruction pairs 203 // 204 virtual int minLatency(MachineOpCode opCode) const { 205 return get(opCode).latency; 206 } 207 208 virtual int maxLatency(MachineOpCode opCode) const { 209 return get(opCode).latency; 210 } 211 212 // 213 // Which operand holds an immediate constant? Returns -1 if none 214 // 215 virtual int getImmedConstantPos(MachineOpCode opCode) const { 216 return -1; // immediate position is machine specific, so say -1 == "none" 217 } 218 219 // Check if the specified constant fits in the immediate field 220 // of this machine instruction 221 // 222 virtual bool constantFitsInImmedField(MachineOpCode opCode, 223 int64_t intValue) const; 224 225 // Return the largest +ve constant that can be held in the IMMMED field 226 // of this machine instruction. 227 // isSignExtended is set to true if the value is sign-extended before use 228 // (this is true for all immediate fields in SPARC instructions). 229 // Return 0 if the instruction has no IMMED field. 230 // 231 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 232 bool &isSignExtended) const { 233 isSignExtended = get(opCode).immedIsSignExtended; 234 return get(opCode).maxImmedConst; 235 } 236 237 //------------------------------------------------------------------------- 238 // Queries about representation of LLVM quantities (e.g., constants) 239 //------------------------------------------------------------------------- 240 241 /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 242 /// from memory into a register, i.e., cannot be set bitwise in register and 243 /// cannot use immediate fields of instructions. Note that this only makes 244 /// sense for primitive types. 245 /// 246 virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 247 248 // Test if this constant may not fit in the immediate field of the 249 // machine instructions (probably) generated for this instruction. 250 // 251 virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 252 const Instruction* I) const { 253 return true; // safe but very conservative 254 } 255 256 //------------------------------------------------------------------------- 257 // Code generation support for creating individual machine instructions 258 //------------------------------------------------------------------------- 259 260 // Get certain common op codes for the current target. this and all the 261 // Create* methods below should be moved to a machine code generation class 262 // 263 virtual MachineOpCode getNOPOpCode() const = 0; 264 265 // Create an instruction sequence to put the constant `val' into 266 // the virtual register `dest'. `val' may be a Constant or a 267 // GlobalValue, viz., the constant address of a global variable or function. 268 // The generated instructions are returned in `mvec'. 269 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 270 // Symbolic constants or constants that must be accessed from memory 271 // are added to the constant pool via MachineFunction::get(F). 272 // 273 virtual void CreateCodeToLoadConst(const TargetMachine& target, 274 Function* F, 275 Value* val, 276 Instruction* dest, 277 std::vector<MachineInstr*>& mvec, 278 MachineCodeForInstruction& mcfi) const=0; 279 280 // Create an instruction sequence to copy an integer value `val' 281 // to a floating point value `dest' by copying to memory and back. 282 // val must be an integral type. dest must be a Float or Double. 283 // The generated instructions are returned in `mvec'. 284 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 285 // Any stack space required is allocated via mcff. 286 // 287 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 288 Function* F, 289 Value* val, 290 Instruction* dest, 291 std::vector<MachineInstr*>& mvec, 292 MachineCodeForInstruction& mcfi)const=0; 293 294 // Similarly, create an instruction sequence to copy an FP value 295 // `val' to an integer value `dest' by copying to memory and back. 296 // The generated instructions are returned in `mvec'. 297 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 298 // Any stack space required is allocated via mcff. 299 // 300 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 301 Function* F, 302 Value* val, 303 Instruction* dest, 304 std::vector<MachineInstr*>& mvec, 305 MachineCodeForInstruction& mcfi)const=0; 306 307 // Create instruction(s) to copy src to dest, for arbitrary types 308 // The generated instructions are returned in `mvec'. 309 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 310 // Any stack space required is allocated via mcff. 311 // 312 virtual void CreateCopyInstructionsByType(const TargetMachine& target, 313 Function* F, 314 Value* src, 315 Instruction* dest, 316 std::vector<MachineInstr*>& mvec, 317 MachineCodeForInstruction& mcfi)const=0; 318 319 // Create instruction sequence to produce a sign-extended register value 320 // from an arbitrary sized value (sized in bits, not bytes). 321 // The generated instructions are appended to `mvec'. 322 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 323 // Any stack space required is allocated via mcff. 324 // 325 virtual void CreateSignExtensionInstructions(const TargetMachine& target, 326 Function* F, 327 Value* srcVal, 328 Value* destVal, 329 unsigned numLowBits, 330 std::vector<MachineInstr*>& mvec, 331 MachineCodeForInstruction& mcfi) const=0; 332 333 // Create instruction sequence to produce a zero-extended register value 334 // from an arbitrary sized value (sized in bits, not bytes). 335 // The generated instructions are appended to `mvec'. 336 // Any temp. registers (TmpInstruction) created are recorded in mcfi. 337 // Any stack space required is allocated via mcff. 338 // 339 virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 340 Function* F, 341 Value* srcVal, 342 Value* destVal, 343 unsigned srcSizeInBits, 344 std::vector<MachineInstr*>& mvec, 345 MachineCodeForInstruction& mcfi) const=0; 346}; 347 348#endif 349