TargetLowering.h revision 00ffed0468ad406062b7c08c2ff46d79d2d1be4d
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/Type.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/CodeGen/ValueTypes.h" 28#include "llvm/Support/DataTypes.h" 29#include <vector> 30 31namespace llvm { 32 class Value; 33 class Function; 34 class TargetMachine; 35 class TargetData; 36 class TargetRegisterClass; 37 class SDNode; 38 class SDOperand; 39 class SelectionDAG; 40 class MachineBasicBlock; 41 class MachineInstr; 42 43//===----------------------------------------------------------------------===// 44/// TargetLowering - This class defines information used to lower LLVM code to 45/// legal SelectionDAG operators that the target instruction selector can accept 46/// natively. 47/// 48/// This class also defines callbacks that targets must implement to lower 49/// target-specific constructs to SelectionDAG operators. 50/// 51class TargetLowering { 52public: 53 /// LegalizeAction - This enum indicates whether operations are valid for a 54 /// target, and if not, what action should be used to make them valid. 55 enum LegalizeAction { 56 Legal, // The target natively supports this operation. 57 Promote, // This operation should be executed in a larger type. 58 Expand, // Try to expand this to other ops, otherwise use a libcall. 59 Custom // Use the LowerOperation hook to implement custom lowering. 60 }; 61 62 enum OutOfRangeShiftAmount { 63 Undefined, // Oversized shift amounts are undefined (default). 64 Mask, // Shift amounts are auto masked (anded) to value size. 65 Extend // Oversized shift pulls in zeros or sign bits. 66 }; 67 68 enum SetCCResultValue { 69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 72 }; 73 74 enum SchedPreference { 75 SchedulingForLatency, // Scheduling for shortest total latency. 76 SchedulingForRegPressure // Scheduling for lowest register pressure. 77 }; 78 79 TargetLowering(TargetMachine &TM); 80 virtual ~TargetLowering(); 81 82 TargetMachine &getTargetMachine() const { return TM; } 83 const TargetData &getTargetData() const { return TD; } 84 85 bool isLittleEndian() const { return IsLittleEndian; } 86 MVT::ValueType getPointerTy() const { return PointerTy; } 87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 89 90 /// isSetCCExpensive - Return true if the setcc operation is expensive for 91 /// this target. 92 bool isSetCCExpensive() const { return SetCCIsExpensive; } 93 94 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 95 /// a sequence of several shifts, adds, and multiplies for this target. 96 bool isIntDivCheap() const { return IntDivIsCheap; } 97 98 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 99 /// srl/add/sra. 100 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 101 102 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 103 /// 104 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 105 106 /// getSetCCResultContents - For targets without boolean registers, this flag 107 /// returns information about the contents of the high-bits in the setcc 108 /// result register. 109 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 110 111 /// getSchedulingPreference - Return target scheduling preference. 112 SchedPreference getSchedulingPreference() const { 113 return SchedPreferenceInfo; 114 } 115 116 /// getRegClassFor - Return the register class that should be used for the 117 /// specified value type. This may only be called on legal types. 118 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 119 TargetRegisterClass *RC = RegClassForVT[VT]; 120 assert(RC && "This value type is not natively supported!"); 121 return RC; 122 } 123 124 /// isTypeLegal - Return true if the target has native support for the 125 /// specified value type. This means that it has a register that directly 126 /// holds it without promotions or expansions. 127 bool isTypeLegal(MVT::ValueType VT) const { 128 return RegClassForVT[VT] != 0; 129 } 130 131 class ValueTypeActionImpl { 132 /// ValueTypeActions - This is a bitvector that contains two bits for each 133 /// value type, where the two bits correspond to the LegalizeAction enum. 134 /// This can be queried with "getTypeAction(VT)". 135 uint32_t ValueTypeActions[2]; 136 public: 137 ValueTypeActionImpl() { 138 ValueTypeActions[0] = ValueTypeActions[1] = 0; 139 } 140 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 141 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 142 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 143 } 144 145 LegalizeAction getTypeAction(MVT::ValueType VT) const { 146 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 147 } 148 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 149 assert(unsigned(VT >> 4) < 150 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 151 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 152 } 153 }; 154 155 const ValueTypeActionImpl &getValueTypeActions() const { 156 return ValueTypeActions; 157 } 158 159 /// getTypeAction - Return how we should legalize values of this type, either 160 /// it is already legal (return 'Legal') or we need to promote it to a larger 161 /// type (return 'Promote'), or we need to expand it into multiple registers 162 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 163 LegalizeAction getTypeAction(MVT::ValueType VT) const { 164 return ValueTypeActions.getTypeAction(VT); 165 } 166 167 /// getTypeToTransformTo - For types supported by the target, this is an 168 /// identity function. For types that must be promoted to larger types, this 169 /// returns the larger type to promote to. For types that are larger than the 170 /// largest integer register, this contains one step in the expansion to get 171 /// to the smaller register. 172 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 173 return TransformToType[VT]; 174 } 175 176 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 177 legal_fpimm_iterator legal_fpimm_begin() const { 178 return LegalFPImmediates.begin(); 179 } 180 legal_fpimm_iterator legal_fpimm_end() const { 181 return LegalFPImmediates.end(); 182 } 183 184 /// getOperationAction - Return how this operation should be treated: either 185 /// it is legal, needs to be promoted to a larger size, needs to be 186 /// expanded to some other code sequence, or the target has a custom expander 187 /// for it. 188 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 189 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 190 } 191 192 /// isOperationLegal - Return true if the specified operation is legal on this 193 /// target. 194 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 195 return getOperationAction(Op, VT) == Legal; 196 } 197 198 /// getTypeToPromoteTo - If the action for this operation is to promote, this 199 /// method returns the ValueType to promote to. 200 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 201 assert(getOperationAction(Op, VT) == Promote && 202 "This operation isn't promoted!"); 203 MVT::ValueType NVT = VT; 204 do { 205 NVT = (MVT::ValueType)(NVT+1); 206 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 207 "Didn't find type to promote to!"); 208 } while (!isTypeLegal(NVT) || 209 getOperationAction(Op, NVT) == Promote); 210 return NVT; 211 } 212 213 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 214 /// This is fixed by the LLVM operations except for the pointer size. 215 MVT::ValueType getValueType(const Type *Ty) const { 216 switch (Ty->getTypeID()) { 217 default: assert(0 && "Unknown type!"); 218 case Type::VoidTyID: return MVT::isVoid; 219 case Type::BoolTyID: return MVT::i1; 220 case Type::UByteTyID: 221 case Type::SByteTyID: return MVT::i8; 222 case Type::ShortTyID: 223 case Type::UShortTyID: return MVT::i16; 224 case Type::IntTyID: 225 case Type::UIntTyID: return MVT::i32; 226 case Type::LongTyID: 227 case Type::ULongTyID: return MVT::i64; 228 case Type::FloatTyID: return MVT::f32; 229 case Type::DoubleTyID: return MVT::f64; 230 case Type::PointerTyID: return PointerTy; 231 case Type::PackedTyID: return MVT::Vector; 232 } 233 } 234 235 /// getNumElements - Return the number of registers that this ValueType will 236 /// eventually require. This is always one for all non-integer types, is 237 /// one for any types promoted to live in larger registers, but may be more 238 /// than one for types (like i64) that are split into pieces. 239 unsigned getNumElements(MVT::ValueType VT) const { 240 return NumElementsForVT[VT]; 241 } 242 243 /// hasTargetDAGCombine - If true, the target has custom DAG combine 244 /// transformations that it can perform for the specified node. 245 bool hasTargetDAGCombine(ISD::NodeType NT) const { 246 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 247 } 248 249 /// This function returns the maximum number of store operations permitted 250 /// to replace a call to llvm.memset. The value is set by the target at the 251 /// performance threshold for such a replacement. 252 /// @brief Get maximum # of store operations permitted for llvm.memset 253 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 254 255 /// This function returns the maximum number of store operations permitted 256 /// to replace a call to llvm.memcpy. The value is set by the target at the 257 /// performance threshold for such a replacement. 258 /// @brief Get maximum # of store operations permitted for llvm.memcpy 259 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 260 261 /// This function returns the maximum number of store operations permitted 262 /// to replace a call to llvm.memmove. The value is set by the target at the 263 /// performance threshold for such a replacement. 264 /// @brief Get maximum # of store operations permitted for llvm.memmove 265 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 266 267 /// This function returns true if the target allows unaligned memory accesses. 268 /// This is used, for example, in situations where an array copy/move/set is 269 /// converted to a sequence of store operations. It's use helps to ensure that 270 /// such replacements don't generate code that causes an alignment error 271 /// (trap) on the target machine. 272 /// @brief Determine if the target supports unaligned memory accesses. 273 bool allowsUnalignedMemoryAccesses() const { 274 return allowUnalignedMemoryAccesses; 275 } 276 277 /// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp 278 /// to implement llvm.setjmp. 279 bool usesUnderscoreSetJmpLongJmp() const { 280 return UseUnderscoreSetJmpLongJmp; 281 } 282 283 /// getStackPointerRegisterToSaveRestore - If a physical register, this 284 /// specifies the register that llvm.savestack/llvm.restorestack should save 285 /// and restore. 286 unsigned getStackPointerRegisterToSaveRestore() const { 287 return StackPointerRegisterToSaveRestore; 288 } 289 290 //===--------------------------------------------------------------------===// 291 // TargetLowering Optimization Methods 292 // 293 294 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 295 /// SDOperands for returning information from TargetLowering to its clients 296 /// that want to combine 297 struct TargetLoweringOpt { 298 SelectionDAG &DAG; 299 SDOperand Old; 300 SDOperand New; 301 302 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 303 304 bool CombineTo(SDOperand O, SDOperand N) { 305 Old = O; 306 New = N; 307 return true; 308 } 309 310 /// ShrinkDemandedConstant - Check to see if the specified operand of the 311 /// specified instruction is a constant integer. If so, check to see if there 312 /// are any bits set in the constant that are not demanded. If so, shrink the 313 /// constant and return true. 314 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 315 }; 316 317 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We 318 /// use this predicate to simplify operations downstream. Op and Mask are 319 /// known to be the same type. 320 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0) 321 const; 322 323 /// ComputeMaskedBits - Determine which of the bits specified in Mask are 324 /// known to be either zero or one and return them in the KnownZero/KnownOne 325 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit 326 /// processing. Targets can implement the computeMaskedBitsForTargetNode 327 /// method, to allow target nodes to be understood. 328 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, 329 uint64_t &KnownOne, unsigned Depth = 0) const; 330 331 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 332 /// DemandedMask bits of the result of Op are ever used downstream. If we can 333 /// use this information to simplify Op, create a new simplified DAG node and 334 /// return true, returning the original and new nodes in Old and New. 335 /// Otherwise, analyze the expression and return a mask of KnownOne and 336 /// KnownZero bits for the expression (used to simplify the caller). 337 /// The KnownZero/One bits may only be accurate for those bits in the 338 /// DemandedMask. 339 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 340 uint64_t &KnownZero, uint64_t &KnownOne, 341 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 342 343 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 344 /// Mask are known to be either zero or one and return them in the 345 /// KnownZero/KnownOne bitsets. 346 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 347 uint64_t Mask, 348 uint64_t &KnownZero, 349 uint64_t &KnownOne, 350 unsigned Depth = 0) const; 351 352 struct DAGCombinerInfo { 353 void *DC; // The DAG Combiner object. 354 bool BeforeLegalize; 355 public: 356 SelectionDAG &DAG; 357 358 DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc) 359 : DC(dc), BeforeLegalize(bl), DAG(dag) {} 360 361 bool isBeforeLegalize() const { return BeforeLegalize; } 362 363 void AddToWorklist(SDNode *N); 364 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 365 SDOperand CombineTo(SDNode *N, SDOperand Res); 366 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 367 }; 368 369 /// PerformDAGCombine - This method will be invoked for all target nodes and 370 /// for any target-independent nodes that the target has registered with 371 /// invoke it for. 372 /// 373 /// The semantics are as follows: 374 /// Return Value: 375 /// SDOperand.Val == 0 - No change was made 376 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 377 /// otherwise - N should be replaced by the returned Operand. 378 /// 379 /// In addition, methods provided by DAGCombinerInfo may be used to perform 380 /// more complex transformations. 381 /// 382 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 383 384 //===--------------------------------------------------------------------===// 385 // TargetLowering Configuration Methods - These methods should be invoked by 386 // the derived class constructor to configure this object for the target. 387 // 388 389protected: 390 391 /// setShiftAmountType - Describe the type that should be used for shift 392 /// amounts. This type defaults to the pointer type. 393 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 394 395 /// setSetCCResultType - Describe the type that shoudl be used as the result 396 /// of a setcc operation. This defaults to the pointer type. 397 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 398 399 /// setSetCCResultContents - Specify how the target extends the result of a 400 /// setcc operation in a register. 401 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 402 403 /// setSchedulingPreference - Specify the target scheduling preference. 404 void setSchedulingPreference(SchedPreference Pref) { 405 SchedPreferenceInfo = Pref; 406 } 407 408 /// setShiftAmountFlavor - Describe how the target handles out of range shift 409 /// amounts. 410 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 411 ShiftAmtHandling = OORSA; 412 } 413 414 /// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to 415 /// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or 416 /// the non _ versions. Defaults to false. 417 void setUseUnderscoreSetJmpLongJmp(bool Val) { 418 UseUnderscoreSetJmpLongJmp = Val; 419 } 420 421 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 422 /// specifies the register that llvm.savestack/llvm.restorestack should save 423 /// and restore. 424 void setStackPointerRegisterToSaveRestore(unsigned R) { 425 StackPointerRegisterToSaveRestore = R; 426 } 427 428 /// setSetCCIxExpensive - This is a short term hack for targets that codegen 429 /// setcc as a conditional branch. This encourages the code generator to fold 430 /// setcc operations into other operations if possible. 431 void setSetCCIsExpensive() { SetCCIsExpensive = true; } 432 433 /// setIntDivIsCheap - Tells the code generator that integer divide is 434 /// expensive, and if possible, should be replaced by an alternate sequence 435 /// of instructions not containing an integer divide. 436 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 437 438 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 439 /// srl/add/sra for a signed divide by power of two, and let the target handle 440 /// it. 441 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 442 443 /// addRegisterClass - Add the specified register class as an available 444 /// regclass for the specified value type. This indicates the selector can 445 /// handle values of that class natively. 446 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 447 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 448 RegClassForVT[VT] = RC; 449 } 450 451 /// computeRegisterProperties - Once all of the register classes are added, 452 /// this allows us to compute derived properties we expose. 453 void computeRegisterProperties(); 454 455 /// setOperationAction - Indicate that the specified operation does not work 456 /// with the specified type and indicate what to do about it. 457 void setOperationAction(unsigned Op, MVT::ValueType VT, 458 LegalizeAction Action) { 459 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 460 "Table isn't big enough!"); 461 OpActions[Op] &= ~(3ULL << VT*2); 462 OpActions[Op] |= (uint64_t)Action << VT*2; 463 } 464 465 /// addLegalFPImmediate - Indicate that this target can instruction select 466 /// the specified FP immediate natively. 467 void addLegalFPImmediate(double Imm) { 468 LegalFPImmediates.push_back(Imm); 469 } 470 471 /// setTargetDAGCombine - Targets should invoke this method for each target 472 /// independent node that they want to provide a custom DAG combiner for by 473 /// implementing the PerformDAGCombine virtual method. 474 void setTargetDAGCombine(ISD::NodeType NT) { 475 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 476 } 477 478public: 479 480 //===--------------------------------------------------------------------===// 481 // Lowering methods - These methods must be implemented by targets so that 482 // the SelectionDAGLowering code knows how to lower these. 483 // 484 485 /// LowerArguments - This hook must be implemented to indicate how we should 486 /// lower the arguments for the specified function, into the specified DAG. 487 virtual std::vector<SDOperand> 488 LowerArguments(Function &F, SelectionDAG &DAG) = 0; 489 490 /// LowerCallTo - This hook lowers an abstract call to a function into an 491 /// actual call. This returns a pair of operands. The first element is the 492 /// return value for the function (if RetTy is not VoidTy). The second 493 /// element is the outgoing token chain. 494 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy; 495 virtual std::pair<SDOperand, SDOperand> 496 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 497 unsigned CallingConv, bool isTailCall, SDOperand Callee, 498 ArgListTy &Args, SelectionDAG &DAG) = 0; 499 500 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or 501 /// llvm.frameaddress (depending on the value of the first argument). The 502 /// return values are the result pointer and the resultant token chain. If 503 /// not implemented, both of these intrinsics will return null. 504 virtual std::pair<SDOperand, SDOperand> 505 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 506 SelectionDAG &DAG); 507 508 /// LowerOperation - This callback is invoked for operations that are 509 /// unsupported by the target, which are registered to use 'custom' lowering, 510 /// and whose defined values are all legal. 511 /// If the target has no operations that require custom lowering, it need not 512 /// implement this. The default implementation of this aborts. 513 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 514 515 /// CustomPromoteOperation - This callback is invoked for operations that are 516 /// unsupported by the target, are registered to use 'custom' lowering, and 517 /// whose type needs to be promoted. 518 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 519 520 /// getTargetNodeName() - This method returns the name of a target specific 521 /// DAG node. 522 virtual const char *getTargetNodeName(unsigned Opcode) const; 523 524 //===--------------------------------------------------------------------===// 525 // Inline Asm Support hooks 526 // 527 528 enum ConstraintType { 529 C_Register, // Constraint represents a single register. 530 C_RegisterClass, // Constraint represents one or more registers. 531 C_Memory, // Memory constraint. 532 C_Other, // Something else. 533 C_Unknown // Unsupported constraint. 534 }; 535 536 /// getConstraintType - Given a constraint letter, return the type of 537 /// constraint it is for this target. 538 virtual ConstraintType getConstraintType(char ConstraintLetter) const; 539 540 541 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 542 /// return a list of registers that can be used to satisfy the constraint. 543 /// This should only be used for C_RegisterClass constraints. 544 virtual std::vector<unsigned> 545 getRegClassForInlineAsmConstraint(const std::string &Constraint, 546 MVT::ValueType VT) const; 547 548 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 549 /// {edx}), return the register number and the register class for the 550 /// register. This should only be used for C_Register constraints. On error, 551 /// this returns a register number of 0. 552 virtual std::pair<unsigned, const TargetRegisterClass*> 553 getRegForInlineAsmConstraint(const std::string &Constraint, 554 MVT::ValueType VT) const; 555 556 557 /// isOperandValidForConstraint - Return true if the specified SDOperand is 558 /// valid for the specified target constraint letter. 559 virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); 560 561 //===--------------------------------------------------------------------===// 562 // Scheduler hooks 563 // 564 565 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 566 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 567 // instructions are special in various ways, which require special support to 568 // insert. The specified MachineInstr is created but not inserted into any 569 // basic blocks, and the scheduler passes ownership of it to this method. 570 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 571 MachineBasicBlock *MBB); 572 573private: 574 TargetMachine &TM; 575 const TargetData &TD; 576 577 /// IsLittleEndian - True if this is a little endian target. 578 /// 579 bool IsLittleEndian; 580 581 /// PointerTy - The type to use for pointers, usually i32 or i64. 582 /// 583 MVT::ValueType PointerTy; 584 585 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 586 /// PointerTy is. 587 MVT::ValueType ShiftAmountTy; 588 589 OutOfRangeShiftAmount ShiftAmtHandling; 590 591 /// SetCCIsExpensive - This is a short term hack for targets that codegen 592 /// setcc as a conditional branch. This encourages the code generator to fold 593 /// setcc operations into other operations if possible. 594 bool SetCCIsExpensive; 595 596 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 597 /// constants into a sequence of muls, adds, and shifts. This is a hack until 598 /// a real cost model is in place. If we ever optimize for size, this will be 599 /// set to true unconditionally. 600 bool IntDivIsCheap; 601 602 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 603 /// srl/add/sra for a signed divide by power of two, and let the target handle 604 /// it. 605 bool Pow2DivIsCheap; 606 607 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 608 /// PointerTy. 609 MVT::ValueType SetCCResultTy; 610 611 /// SetCCResultContents - Information about the contents of the high-bits in 612 /// the result of a setcc comparison operation. 613 SetCCResultValue SetCCResultContents; 614 615 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 616 /// total cycles or lowest register usage. 617 SchedPreference SchedPreferenceInfo; 618 619 /// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and 620 /// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false. 621 bool UseUnderscoreSetJmpLongJmp; 622 623 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 624 /// specifies the register that llvm.savestack/llvm.restorestack should save 625 /// and restore. 626 unsigned StackPointerRegisterToSaveRestore; 627 628 /// RegClassForVT - This indicates the default register class to use for 629 /// each ValueType the target supports natively. 630 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 631 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE]; 632 633 /// TransformToType - For any value types we are promoting or expanding, this 634 /// contains the value type that we are changing to. For Expanded types, this 635 /// contains one step of the expand (e.g. i64 -> i32), even if there are 636 /// multiple steps required (e.g. i64 -> i16). For types natively supported 637 /// by the system, this holds the same type (e.g. i32 -> i32). 638 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 639 640 /// OpActions - For each operation and each value type, keep a LegalizeAction 641 /// that indicates how instruction selection should deal with the operation. 642 /// Most operations are Legal (aka, supported natively by the target), but 643 /// operations that are not should be described. Note that operations on 644 /// non-legal value types are not described here. 645 uint64_t OpActions[128]; 646 647 ValueTypeActionImpl ValueTypeActions; 648 649 std::vector<double> LegalFPImmediates; 650 651 std::vector<std::pair<MVT::ValueType, 652 TargetRegisterClass*> > AvailableRegClasses; 653 654 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 655 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 656 /// which sets a bit in this array. 657 unsigned char TargetDAGCombineArray[128/(sizeof(unsigned char)*8)]; 658 659protected: 660 /// When lowering %llvm.memset this field specifies the maximum number of 661 /// store operations that may be substituted for the call to memset. Targets 662 /// must set this value based on the cost threshold for that target. Targets 663 /// should assume that the memset will be done using as many of the largest 664 /// store operations first, followed by smaller ones, if necessary, per 665 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 666 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 667 /// store. This only applies to setting a constant array of a constant size. 668 /// @brief Specify maximum number of store instructions per memset call. 669 unsigned maxStoresPerMemset; 670 671 /// When lowering %llvm.memcpy this field specifies the maximum number of 672 /// store operations that may be substituted for a call to memcpy. Targets 673 /// must set this value based on the cost threshold for that target. Targets 674 /// should assume that the memcpy will be done using as many of the largest 675 /// store operations first, followed by smaller ones, if necessary, per 676 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 677 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 678 /// and one 1-byte store. This only applies to copying a constant array of 679 /// constant size. 680 /// @brief Specify maximum bytes of store instructions per memcpy call. 681 unsigned maxStoresPerMemcpy; 682 683 /// When lowering %llvm.memmove this field specifies the maximum number of 684 /// store instructions that may be substituted for a call to memmove. Targets 685 /// must set this value based on the cost threshold for that target. Targets 686 /// should assume that the memmove will be done using as many of the largest 687 /// store operations first, followed by smaller ones, if necessary, per 688 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 689 /// with 8-bit alignment would result in nine 1-byte stores. This only 690 /// applies to copying a constant array of constant size. 691 /// @brief Specify maximum bytes of store instructions per memmove call. 692 unsigned maxStoresPerMemmove; 693 694 /// This field specifies whether the target machine permits unaligned memory 695 /// accesses. This is used, for example, to determine the size of store 696 /// operations when copying small arrays and other similar tasks. 697 /// @brief Indicate whether the target permits unaligned memory accesses. 698 bool allowUnalignedMemoryAccesses; 699}; 700} // end llvm namespace 701 702#endif 703