TargetLowering.h revision 211ffa13519cadfb7f9baf4c8447fa055bf38fe8
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/CodeGen/SelectionDAGNodes.h" 28#include "llvm/CodeGen/RuntimeLibcalls.h" 29#include "llvm/ADT/APFloat.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallSet.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/STLExtras.h" 34#include "llvm/Support/DebugLoc.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class AllocaInst; 42 class CallInst; 43 class Function; 44 class FastISel; 45 class MachineBasicBlock; 46 class MachineFunction; 47 class MachineFrameInfo; 48 class MachineInstr; 49 class MachineJumpTableInfo; 50 class MCContext; 51 class MCExpr; 52 class SDNode; 53 class SDValue; 54 class SelectionDAG; 55 class TargetData; 56 class TargetMachine; 57 class TargetRegisterClass; 58 class TargetLoweringObjectFile; 59 class Value; 60 61 // FIXME: should this be here? 62 namespace TLSModel { 63 enum Model { 64 GeneralDynamic, 65 LocalDynamic, 66 InitialExec, 67 LocalExec 68 }; 69 } 70 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 71 72 73//===----------------------------------------------------------------------===// 74/// TargetLowering - This class defines information used to lower LLVM code to 75/// legal SelectionDAG operators that the target instruction selector can accept 76/// natively. 77/// 78/// This class also defines callbacks that targets must implement to lower 79/// target-specific constructs to SelectionDAG operators. 80/// 81class TargetLowering { 82 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 83 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 84public: 85 /// LegalizeAction - This enum indicates whether operations are valid for a 86 /// target, and if not, what action should be used to make them valid. 87 enum LegalizeAction { 88 Legal, // The target natively supports this operation. 89 Promote, // This operation should be executed in a larger type. 90 Expand, // Try to expand this to other ops, otherwise use a libcall. 91 Custom // Use the LowerOperation hook to implement custom lowering. 92 }; 93 94 enum BooleanContent { // How the target represents true/false values. 95 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 96 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 97 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 98 }; 99 100 /// NOTE: The constructor takes ownership of TLOF. 101 explicit TargetLowering(const TargetMachine &TM, 102 const TargetLoweringObjectFile *TLOF); 103 virtual ~TargetLowering(); 104 105 const TargetMachine &getTargetMachine() const { return TM; } 106 const TargetData *getTargetData() const { return TD; } 107 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 108 109 bool isBigEndian() const { return !IsLittleEndian; } 110 bool isLittleEndian() const { return IsLittleEndian; } 111 MVT getPointerTy() const { return PointerTy; } 112 MVT getShiftAmountTy() const { return ShiftAmountTy; } 113 114 /// isSelectExpensive - Return true if the select operation is expensive for 115 /// this target. 116 bool isSelectExpensive() const { return SelectIsExpensive; } 117 118 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 119 /// a sequence of several shifts, adds, and multiplies for this target. 120 bool isIntDivCheap() const { return IntDivIsCheap; } 121 122 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 123 /// srl/add/sra. 124 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 125 126 /// getSetCCResultType - Return the ValueType of the result of SETCC 127 /// operations. Also used to obtain the target's preferred type for 128 /// the condition operand of SELECT and BRCOND nodes. In the case of 129 /// BRCOND the argument passed is MVT::Other since there are no other 130 /// operands to get a type hint from. 131 virtual 132 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 133 134 /// getCmpLibcallReturnType - Return the ValueType for comparison 135 /// libcalls. Comparions libcalls include floating point comparion calls, 136 /// and Ordered/Unordered check calls on floating point numbers. 137 virtual 138 MVT::SimpleValueType getCmpLibcallReturnType() const; 139 140 /// getBooleanContents - For targets without i1 registers, this gives the 141 /// nature of the high-bits of boolean values held in types wider than i1. 142 /// "Boolean values" are special true/false values produced by nodes like 143 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 144 /// Not to be confused with general values promoted from i1. 145 BooleanContent getBooleanContents() const { return BooleanContents;} 146 147 /// getSchedulingPreference - Return target scheduling preference. 148 Sched::Preference getSchedulingPreference() const { 149 return SchedPreferenceInfo; 150 } 151 152 /// getRegClassFor - Return the register class that should be used for the 153 /// specified value type. 154 virtual TargetRegisterClass *getRegClassFor(EVT VT) const { 155 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 156 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 157 assert(RC && "This value type is not natively supported!"); 158 return RC; 159 } 160 161 /// isTypeLegal - Return true if the target has native support for the 162 /// specified value type. This means that it has a register that directly 163 /// holds it without promotions or expansions. 164 bool isTypeLegal(EVT VT) const { 165 assert(!VT.isSimple() || 166 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 167 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 168 } 169 170 /// isTypeSynthesizable - Return true if it's OK for the compiler to create 171 /// new operations of this type. All Legal types are synthesizable except 172 /// MMX vector types on X86. Non-Legal types are not synthesizable. 173 bool isTypeSynthesizable(EVT VT) const { 174 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy]; 175 } 176 177 class ValueTypeActionImpl { 178 /// ValueTypeActions - For each value type, keep a LegalizeAction enum 179 /// that indicates how instruction selection should deal with the type. 180 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 181 public: 182 ValueTypeActionImpl() { 183 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 184 } 185 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 186 if (VT.isExtended()) { 187 if (VT.isVector()) { 188 return VT.isPow2VectorType() ? Expand : Promote; 189 } 190 if (VT.isInteger()) 191 // First promote to a power-of-two size, then expand if necessary. 192 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote; 193 assert(0 && "Unsupported extended type!"); 194 return Legal; 195 } 196 unsigned I = VT.getSimpleVT().SimpleTy; 197 return (LegalizeAction)ValueTypeActions[I]; 198 } 199 void setTypeAction(EVT VT, LegalizeAction Action) { 200 unsigned I = VT.getSimpleVT().SimpleTy; 201 ValueTypeActions[I] = Action; 202 } 203 }; 204 205 const ValueTypeActionImpl &getValueTypeActions() const { 206 return ValueTypeActions; 207 } 208 209 /// getTypeAction - Return how we should legalize values of this type, either 210 /// it is already legal (return 'Legal') or we need to promote it to a larger 211 /// type (return 'Promote'), or we need to expand it into multiple registers 212 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 213 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 214 return ValueTypeActions.getTypeAction(Context, VT); 215 } 216 217 /// getTypeToTransformTo - For types supported by the target, this is an 218 /// identity function. For types that must be promoted to larger types, this 219 /// returns the larger type to promote to. For integer types that are larger 220 /// than the largest integer register, this contains one step in the expansion 221 /// to get to the smaller register. For illegal floating point types, this 222 /// returns the integer type to transform to. 223 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 224 if (VT.isSimple()) { 225 assert((unsigned)VT.getSimpleVT().SimpleTy < 226 array_lengthof(TransformToType)); 227 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 228 assert(getTypeAction(Context, NVT) != Promote && 229 "Promote may not follow Expand or Promote"); 230 return NVT; 231 } 232 233 if (VT.isVector()) { 234 EVT NVT = VT.getPow2VectorType(Context); 235 if (NVT == VT) { 236 // Vector length is a power of 2 - split to half the size. 237 unsigned NumElts = VT.getVectorNumElements(); 238 EVT EltVT = VT.getVectorElementType(); 239 return (NumElts == 1) ? 240 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 241 } 242 // Promote to a power of two size, avoiding multi-step promotion. 243 return getTypeAction(Context, NVT) == Promote ? 244 getTypeToTransformTo(Context, NVT) : NVT; 245 } else if (VT.isInteger()) { 246 EVT NVT = VT.getRoundIntegerType(Context); 247 if (NVT == VT) 248 // Size is a power of two - expand to half the size. 249 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 250 else 251 // Promote to a power of two size, avoiding multi-step promotion. 252 return getTypeAction(Context, NVT) == Promote ? 253 getTypeToTransformTo(Context, NVT) : NVT; 254 } 255 assert(0 && "Unsupported extended type!"); 256 return MVT(MVT::Other); // Not reached 257 } 258 259 /// getTypeToExpandTo - For types supported by the target, this is an 260 /// identity function. For types that must be expanded (i.e. integer types 261 /// that are larger than the largest integer register or illegal floating 262 /// point types), this returns the largest legal type it will be expanded to. 263 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 264 assert(!VT.isVector()); 265 while (true) { 266 switch (getTypeAction(Context, VT)) { 267 case Legal: 268 return VT; 269 case Expand: 270 VT = getTypeToTransformTo(Context, VT); 271 break; 272 default: 273 assert(false && "Type is not legal nor is it to be expanded!"); 274 return VT; 275 } 276 } 277 return VT; 278 } 279 280 /// getVectorTypeBreakdown - Vector types are broken down into some number of 281 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 282 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 283 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 284 /// 285 /// This method returns the number of registers needed, and the VT for each 286 /// register. It also returns the VT and quantity of the intermediate values 287 /// before they are promoted/expanded. 288 /// 289 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 290 EVT &IntermediateVT, 291 unsigned &NumIntermediates, 292 EVT &RegisterVT) const; 293 294 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 295 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 296 /// this is the case, it returns true and store the intrinsic 297 /// information into the IntrinsicInfo that was passed to the function. 298 struct IntrinsicInfo { 299 unsigned opc; // target opcode 300 EVT memVT; // memory VT 301 const Value* ptrVal; // value representing memory location 302 int offset; // offset off of ptrVal 303 unsigned align; // alignment 304 bool vol; // is volatile? 305 bool readMem; // reads memory? 306 bool writeMem; // writes memory? 307 }; 308 309 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 310 const CallInst &I, unsigned Intrinsic) const { 311 return false; 312 } 313 314 /// isFPImmLegal - Returns true if the target can instruction select the 315 /// specified FP immediate natively. If false, the legalizer will materialize 316 /// the FP immediate as a load from a constant pool. 317 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const { 318 return false; 319 } 320 321 /// isShuffleMaskLegal - Targets can use this to indicate that they only 322 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 323 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 324 /// are assumed to be legal. 325 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 326 EVT VT) const { 327 return true; 328 } 329 330 /// canOpTrap - Returns true if the operation can trap for the value type. 331 /// VT must be a legal type. By default, we optimistically assume most 332 /// operations don't trap except for divide and remainder. 333 virtual bool canOpTrap(unsigned Op, EVT VT) const; 334 335 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 336 /// used by Targets can use this to indicate if there is a suitable 337 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 338 /// pool entry. 339 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 340 EVT VT) const { 341 return false; 342 } 343 344 /// getOperationAction - Return how this operation should be treated: either 345 /// it is legal, needs to be promoted to a larger size, needs to be 346 /// expanded to some other code sequence, or the target has a custom expander 347 /// for it. 348 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 349 if (VT.isExtended()) return Expand; 350 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 351 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 352 return (LegalizeAction)OpActions[I][Op]; 353 } 354 355 /// isOperationLegalOrCustom - Return true if the specified operation is 356 /// legal on this target or can be made legal with custom lowering. This 357 /// is used to help guide high-level lowering decisions. 358 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 359 return (VT == MVT::Other || isTypeLegal(VT)) && 360 (getOperationAction(Op, VT) == Legal || 361 getOperationAction(Op, VT) == Custom); 362 } 363 364 /// isOperationLegal - Return true if the specified operation is legal on this 365 /// target. 366 bool isOperationLegal(unsigned Op, EVT VT) const { 367 return (VT == MVT::Other || isTypeLegal(VT)) && 368 getOperationAction(Op, VT) == Legal; 369 } 370 371 /// getLoadExtAction - Return how this load with extension should be treated: 372 /// either it is legal, needs to be promoted to a larger size, needs to be 373 /// expanded to some other code sequence, or the target has a custom expander 374 /// for it. 375 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { 376 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 377 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 378 "Table isn't big enough!"); 379 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 380 } 381 382 /// isLoadExtLegal - Return true if the specified load with extension is legal 383 /// on this target. 384 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 385 return VT.isSimple() && 386 (getLoadExtAction(ExtType, VT) == Legal || 387 getLoadExtAction(ExtType, VT) == Custom); 388 } 389 390 /// getTruncStoreAction - Return how this store with truncation should be 391 /// treated: either it is legal, needs to be promoted to a larger size, needs 392 /// to be expanded to some other code sequence, or the target has a custom 393 /// expander for it. 394 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 395 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 396 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 397 "Table isn't big enough!"); 398 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] 399 [MemVT.getSimpleVT().SimpleTy]; 400 } 401 402 /// isTruncStoreLegal - Return true if the specified store with truncation is 403 /// legal on this target. 404 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 405 return isTypeLegal(ValVT) && MemVT.isSimple() && 406 (getTruncStoreAction(ValVT, MemVT) == Legal || 407 getTruncStoreAction(ValVT, MemVT) == Custom); 408 } 409 410 /// getIndexedLoadAction - Return how the indexed load should be treated: 411 /// either it is legal, needs to be promoted to a larger size, needs to be 412 /// expanded to some other code sequence, or the target has a custom expander 413 /// for it. 414 LegalizeAction 415 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 416 assert( IdxMode < ISD::LAST_INDEXED_MODE && 417 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 418 "Table isn't big enough!"); 419 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 420 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 421 } 422 423 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 424 /// on this target. 425 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 426 return VT.isSimple() && 427 (getIndexedLoadAction(IdxMode, VT) == Legal || 428 getIndexedLoadAction(IdxMode, VT) == Custom); 429 } 430 431 /// getIndexedStoreAction - Return how the indexed store should be treated: 432 /// either it is legal, needs to be promoted to a larger size, needs to be 433 /// expanded to some other code sequence, or the target has a custom expander 434 /// for it. 435 LegalizeAction 436 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 437 assert( IdxMode < ISD::LAST_INDEXED_MODE && 438 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 439 "Table isn't big enough!"); 440 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 441 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 442 } 443 444 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 445 /// on this target. 446 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 447 return VT.isSimple() && 448 (getIndexedStoreAction(IdxMode, VT) == Legal || 449 getIndexedStoreAction(IdxMode, VT) == Custom); 450 } 451 452 /// getCondCodeAction - Return how the condition code should be treated: 453 /// either it is legal, needs to be expanded to some other code sequence, 454 /// or the target has a custom expander for it. 455 LegalizeAction 456 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 457 assert((unsigned)CC < array_lengthof(CondCodeActions) && 458 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 459 "Table isn't big enough!"); 460 LegalizeAction Action = (LegalizeAction) 461 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 462 assert(Action != Promote && "Can't promote condition code!"); 463 return Action; 464 } 465 466 /// isCondCodeLegal - Return true if the specified condition code is legal 467 /// on this target. 468 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 469 return getCondCodeAction(CC, VT) == Legal || 470 getCondCodeAction(CC, VT) == Custom; 471 } 472 473 474 /// getTypeToPromoteTo - If the action for this operation is to promote, this 475 /// method returns the ValueType to promote to. 476 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 477 assert(getOperationAction(Op, VT) == Promote && 478 "This operation isn't promoted!"); 479 480 // See if this has an explicit type specified. 481 std::map<std::pair<unsigned, MVT::SimpleValueType>, 482 MVT::SimpleValueType>::const_iterator PTTI = 483 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 484 if (PTTI != PromoteToType.end()) return PTTI->second; 485 486 assert((VT.isInteger() || VT.isFloatingPoint()) && 487 "Cannot autopromote this type, add it with AddPromotedToType."); 488 489 EVT NVT = VT; 490 do { 491 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 492 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 493 "Didn't find type to promote to!"); 494 } while (!isTypeLegal(NVT) || 495 getOperationAction(Op, NVT) == Promote); 496 return NVT; 497 } 498 499 /// getValueType - Return the EVT corresponding to this LLVM type. 500 /// This is fixed by the LLVM operations except for the pointer size. If 501 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 502 /// counterpart (e.g. structs), otherwise it will assert. 503 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 504 EVT VT = EVT::getEVT(Ty, AllowUnknown); 505 return VT == MVT::iPTR ? PointerTy : VT; 506 } 507 508 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 509 /// function arguments in the caller parameter area. This is the actual 510 /// alignment, not its logarithm. 511 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 512 513 /// getRegisterType - Return the type of registers that this ValueType will 514 /// eventually require. 515 EVT getRegisterType(MVT VT) const { 516 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 517 return RegisterTypeForVT[VT.SimpleTy]; 518 } 519 520 /// getRegisterType - Return the type of registers that this ValueType will 521 /// eventually require. 522 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 523 if (VT.isSimple()) { 524 assert((unsigned)VT.getSimpleVT().SimpleTy < 525 array_lengthof(RegisterTypeForVT)); 526 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 527 } 528 if (VT.isVector()) { 529 EVT VT1, RegisterVT; 530 unsigned NumIntermediates; 531 (void)getVectorTypeBreakdown(Context, VT, VT1, 532 NumIntermediates, RegisterVT); 533 return RegisterVT; 534 } 535 if (VT.isInteger()) { 536 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 537 } 538 assert(0 && "Unsupported extended type!"); 539 return EVT(MVT::Other); // Not reached 540 } 541 542 /// getNumRegisters - Return the number of registers that this ValueType will 543 /// eventually require. This is one for any types promoted to live in larger 544 /// registers, but may be more than one for types (like i64) that are split 545 /// into pieces. For types like i140, which are first promoted then expanded, 546 /// it is the number of registers needed to hold all the bits of the original 547 /// type. For an i140 on a 32 bit machine this means 5 registers. 548 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 549 if (VT.isSimple()) { 550 assert((unsigned)VT.getSimpleVT().SimpleTy < 551 array_lengthof(NumRegistersForVT)); 552 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 553 } 554 if (VT.isVector()) { 555 EVT VT1, VT2; 556 unsigned NumIntermediates; 557 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 558 } 559 if (VT.isInteger()) { 560 unsigned BitWidth = VT.getSizeInBits(); 561 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 562 return (BitWidth + RegWidth - 1) / RegWidth; 563 } 564 assert(0 && "Unsupported extended type!"); 565 return 0; // Not reached 566 } 567 568 /// ShouldShrinkFPConstant - If true, then instruction selection should 569 /// seek to shrink the FP constant of the specified type to a smaller type 570 /// in order to save space and / or reduce runtime. 571 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 572 573 /// hasTargetDAGCombine - If true, the target has custom DAG combine 574 /// transformations that it can perform for the specified node. 575 bool hasTargetDAGCombine(ISD::NodeType NT) const { 576 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 577 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 578 } 579 580 /// This function returns the maximum number of store operations permitted 581 /// to replace a call to llvm.memset. The value is set by the target at the 582 /// performance threshold for such a replacement. 583 /// @brief Get maximum # of store operations permitted for llvm.memset 584 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 585 586 /// This function returns the maximum number of store operations permitted 587 /// to replace a call to llvm.memcpy. The value is set by the target at the 588 /// performance threshold for such a replacement. 589 /// @brief Get maximum # of store operations permitted for llvm.memcpy 590 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 591 592 /// This function returns the maximum number of store operations permitted 593 /// to replace a call to llvm.memmove. The value is set by the target at the 594 /// performance threshold for such a replacement. 595 /// @brief Get maximum # of store operations permitted for llvm.memmove 596 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 597 598 /// This function returns true if the target allows unaligned memory accesses. 599 /// of the specified type. This is used, for example, in situations where an 600 /// array copy/move/set is converted to a sequence of store operations. It's 601 /// use helps to ensure that such replacements don't generate code that causes 602 /// an alignment error (trap) on the target machine. 603 /// @brief Determine if the target supports unaligned memory accesses. 604 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 605 return false; 606 } 607 608 /// This function returns true if the target would benefit from code placement 609 /// optimization. 610 /// @brief Determine if the target should perform code placement optimization. 611 bool shouldOptimizeCodePlacement() const { 612 return benefitFromCodePlacementOpt; 613 } 614 615 /// getOptimalMemOpType - Returns the target specific optimal type for load 616 /// and store operations as a result of memset, memcpy, and memmove 617 /// lowering. If DstAlign is zero that means it's safe to destination 618 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 619 /// means there isn't a need to check it against alignment requirement, 620 /// probably because the source does not need to be loaded. If 621 /// 'NonScalarIntSafe' is true, that means it's safe to return a 622 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 623 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 624 /// constant so it does not need to be loaded. 625 /// It returns EVT::Other if the type should be determined using generic 626 /// target-independent logic. 627 virtual EVT getOptimalMemOpType(uint64_t Size, 628 unsigned DstAlign, unsigned SrcAlign, 629 bool NonScalarIntSafe, bool MemcpyStrSrc, 630 MachineFunction &MF) const { 631 return MVT::Other; 632 } 633 634 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 635 /// to implement llvm.setjmp. 636 bool usesUnderscoreSetJmp() const { 637 return UseUnderscoreSetJmp; 638 } 639 640 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 641 /// to implement llvm.longjmp. 642 bool usesUnderscoreLongJmp() const { 643 return UseUnderscoreLongJmp; 644 } 645 646 /// getStackPointerRegisterToSaveRestore - If a physical register, this 647 /// specifies the register that llvm.savestack/llvm.restorestack should save 648 /// and restore. 649 unsigned getStackPointerRegisterToSaveRestore() const { 650 return StackPointerRegisterToSaveRestore; 651 } 652 653 /// getExceptionAddressRegister - If a physical register, this returns 654 /// the register that receives the exception address on entry to a landing 655 /// pad. 656 unsigned getExceptionAddressRegister() const { 657 return ExceptionPointerRegister; 658 } 659 660 /// getExceptionSelectorRegister - If a physical register, this returns 661 /// the register that receives the exception typeid on entry to a landing 662 /// pad. 663 unsigned getExceptionSelectorRegister() const { 664 return ExceptionSelectorRegister; 665 } 666 667 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 668 /// set, the default is 200) 669 unsigned getJumpBufSize() const { 670 return JumpBufSize; 671 } 672 673 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 674 /// (if never set, the default is 0) 675 unsigned getJumpBufAlignment() const { 676 return JumpBufAlignment; 677 } 678 679 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 680 /// limit. Any block whose size is greater should not be predicated. 681 unsigned getIfCvtBlockSizeLimit() const { 682 return IfCvtBlockSizeLimit; 683 } 684 685 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 686 /// block to be considered for duplication. Any block whose size is greater 687 /// should not be duplicated to facilitate its predication. 688 unsigned getIfCvtDupBlockSizeLimit() const { 689 return IfCvtDupBlockSizeLimit; 690 } 691 692 /// getPrefLoopAlignment - return the preferred loop alignment. 693 /// 694 unsigned getPrefLoopAlignment() const { 695 return PrefLoopAlignment; 696 } 697 698 /// getPreIndexedAddressParts - returns true by value, base pointer and 699 /// offset pointer and addressing mode by reference if the node's address 700 /// can be legally represented as pre-indexed load / store address. 701 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 702 SDValue &Offset, 703 ISD::MemIndexedMode &AM, 704 SelectionDAG &DAG) const { 705 return false; 706 } 707 708 /// getPostIndexedAddressParts - returns true by value, base pointer and 709 /// offset pointer and addressing mode by reference if this node can be 710 /// combined with a load / store to form a post-indexed load / store. 711 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 712 SDValue &Base, SDValue &Offset, 713 ISD::MemIndexedMode &AM, 714 SelectionDAG &DAG) const { 715 return false; 716 } 717 718 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 719 /// current function. The returned value is a member of the 720 /// MachineJumpTableInfo::JTEntryKind enum. 721 virtual unsigned getJumpTableEncoding() const; 722 723 virtual const MCExpr * 724 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 725 const MachineBasicBlock *MBB, unsigned uid, 726 MCContext &Ctx) const { 727 assert(0 && "Need to implement this hook if target has custom JTIs"); 728 return 0; 729 } 730 731 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 732 /// jumptable. 733 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 734 SelectionDAG &DAG) const; 735 736 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 737 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 738 /// MCExpr. 739 virtual const MCExpr * 740 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 741 unsigned JTI, MCContext &Ctx) const; 742 743 /// isOffsetFoldingLegal - Return true if folding a constant offset 744 /// with the given GlobalAddress is legal. It is frequently not legal in 745 /// PIC relocation models. 746 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 747 748 /// getFunctionAlignment - Return the Log2 alignment of this function. 749 virtual unsigned getFunctionAlignment(const Function *) const = 0; 750 751 //===--------------------------------------------------------------------===// 752 // TargetLowering Optimization Methods 753 // 754 755 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 756 /// SDValues for returning information from TargetLowering to its clients 757 /// that want to combine 758 struct TargetLoweringOpt { 759 SelectionDAG &DAG; 760 bool LegalTys; 761 bool LegalOps; 762 bool ShrinkOps; 763 SDValue Old; 764 SDValue New; 765 766 explicit TargetLoweringOpt(SelectionDAG &InDAG, 767 bool LT, bool LO, 768 bool Shrink = false) : 769 DAG(InDAG), LegalTys(LT), LegalOps(LO), ShrinkOps(Shrink) {} 770 771 bool LegalTypes() const { return LegalTys; } 772 bool LegalOperations() const { return LegalOps; } 773 774 bool CombineTo(SDValue O, SDValue N) { 775 Old = O; 776 New = N; 777 return true; 778 } 779 780 /// ShrinkDemandedConstant - Check to see if the specified operand of the 781 /// specified instruction is a constant integer. If so, check to see if 782 /// there are any bits set in the constant that are not demanded. If so, 783 /// shrink the constant and return true. 784 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 785 786 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 787 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 788 /// cast, but it could be generalized for targets with other types of 789 /// implicit widening casts. 790 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 791 DebugLoc dl); 792 }; 793 794 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 795 /// DemandedMask bits of the result of Op are ever used downstream. If we can 796 /// use this information to simplify Op, create a new simplified DAG node and 797 /// return true, returning the original and new nodes in Old and New. 798 /// Otherwise, analyze the expression and return a mask of KnownOne and 799 /// KnownZero bits for the expression (used to simplify the caller). 800 /// The KnownZero/One bits may only be accurate for those bits in the 801 /// DemandedMask. 802 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 803 APInt &KnownZero, APInt &KnownOne, 804 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 805 806 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 807 /// Mask are known to be either zero or one and return them in the 808 /// KnownZero/KnownOne bitsets. 809 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 810 const APInt &Mask, 811 APInt &KnownZero, 812 APInt &KnownOne, 813 const SelectionDAG &DAG, 814 unsigned Depth = 0) const; 815 816 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 817 /// targets that want to expose additional information about sign bits to the 818 /// DAG Combiner. 819 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 820 unsigned Depth = 0) const; 821 822 struct DAGCombinerInfo { 823 void *DC; // The DAG Combiner object. 824 bool BeforeLegalize; 825 bool BeforeLegalizeOps; 826 bool CalledByLegalizer; 827 public: 828 SelectionDAG &DAG; 829 830 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 831 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 832 CalledByLegalizer(cl), DAG(dag) {} 833 834 bool isBeforeLegalize() const { return BeforeLegalize; } 835 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 836 bool isCalledByLegalizer() const { return CalledByLegalizer; } 837 838 void AddToWorklist(SDNode *N); 839 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 840 bool AddTo = true); 841 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 842 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 843 844 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 845 }; 846 847 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 848 /// and cc. If it is unable to simplify it, return a null SDValue. 849 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 850 ISD::CondCode Cond, bool foldBooleans, 851 DAGCombinerInfo &DCI, DebugLoc dl) const; 852 853 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 854 /// node is a GlobalAddress + offset. 855 virtual bool 856 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 857 858 /// PerformDAGCombine - This method will be invoked for all target nodes and 859 /// for any target-independent nodes that the target has registered with 860 /// invoke it for. 861 /// 862 /// The semantics are as follows: 863 /// Return Value: 864 /// SDValue.Val == 0 - No change was made 865 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 866 /// otherwise - N should be replaced by the returned Operand. 867 /// 868 /// In addition, methods provided by DAGCombinerInfo may be used to perform 869 /// more complex transformations. 870 /// 871 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 872 873 /// isTypeDesirableForOp - Return true if the target has native support for 874 /// the specified value type and it is 'desirable' to use the type for the 875 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 876 /// instruction encodings are longer and some i16 instructions are slow. 877 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const { 878 // By default, assume all legal types are desirable. 879 return isTypeLegal(VT); 880 } 881 882 /// IsDesirableToPromoteOp - This method query the target whether it is 883 /// beneficial for dag combiner to promote the specified node. If true, it 884 /// should return the desired promotion type by reference. 885 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 886 return false; 887 } 888 889 //===--------------------------------------------------------------------===// 890 // TargetLowering Configuration Methods - These methods should be invoked by 891 // the derived class constructor to configure this object for the target. 892 // 893 894protected: 895 /// setShiftAmountType - Describe the type that should be used for shift 896 /// amounts. This type defaults to the pointer type. 897 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 898 899 /// setBooleanContents - Specify how the target extends the result of a 900 /// boolean value from i1 to a wider type. See getBooleanContents. 901 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 902 903 /// setSchedulingPreference - Specify the target scheduling preference. 904 void setSchedulingPreference(Sched::Preference Pref) { 905 SchedPreferenceInfo = Pref; 906 } 907 908 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 909 /// use _setjmp to implement llvm.setjmp or the non _ version. 910 /// Defaults to false. 911 void setUseUnderscoreSetJmp(bool Val) { 912 UseUnderscoreSetJmp = Val; 913 } 914 915 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 916 /// use _longjmp to implement llvm.longjmp or the non _ version. 917 /// Defaults to false. 918 void setUseUnderscoreLongJmp(bool Val) { 919 UseUnderscoreLongJmp = Val; 920 } 921 922 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 923 /// specifies the register that llvm.savestack/llvm.restorestack should save 924 /// and restore. 925 void setStackPointerRegisterToSaveRestore(unsigned R) { 926 StackPointerRegisterToSaveRestore = R; 927 } 928 929 /// setExceptionPointerRegister - If set to a physical register, this sets 930 /// the register that receives the exception address on entry to a landing 931 /// pad. 932 void setExceptionPointerRegister(unsigned R) { 933 ExceptionPointerRegister = R; 934 } 935 936 /// setExceptionSelectorRegister - If set to a physical register, this sets 937 /// the register that receives the exception typeid on entry to a landing 938 /// pad. 939 void setExceptionSelectorRegister(unsigned R) { 940 ExceptionSelectorRegister = R; 941 } 942 943 /// SelectIsExpensive - Tells the code generator not to expand operations 944 /// into sequences that use the select operations if possible. 945 void setSelectIsExpensive() { SelectIsExpensive = true; } 946 947 /// setIntDivIsCheap - Tells the code generator that integer divide is 948 /// expensive, and if possible, should be replaced by an alternate sequence 949 /// of instructions not containing an integer divide. 950 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 951 952 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 953 /// srl/add/sra for a signed divide by power of two, and let the target handle 954 /// it. 955 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 956 957 /// addRegisterClass - Add the specified register class as an available 958 /// regclass for the specified value type. This indicates the selector can 959 /// handle values of that class natively. 960 void addRegisterClass(EVT VT, TargetRegisterClass *RC, 961 bool isSynthesizable = true) { 962 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 963 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 964 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 965 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable; 966 } 967 968 /// computeRegisterProperties - Once all of the register classes are added, 969 /// this allows us to compute derived properties we expose. 970 void computeRegisterProperties(); 971 972 /// setOperationAction - Indicate that the specified operation does not work 973 /// with the specified type and indicate what to do about it. 974 void setOperationAction(unsigned Op, MVT VT, 975 LegalizeAction Action) { 976 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 977 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 978 } 979 980 /// setLoadExtAction - Indicate that the specified load with extension does 981 /// not work with the specified type and indicate what to do about it. 982 void setLoadExtAction(unsigned ExtType, MVT VT, 983 LegalizeAction Action) { 984 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 985 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 986 "Table isn't big enough!"); 987 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 988 } 989 990 /// setTruncStoreAction - Indicate that the specified truncating store does 991 /// not work with the specified type and indicate what to do about it. 992 void setTruncStoreAction(MVT ValVT, MVT MemVT, 993 LegalizeAction Action) { 994 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE && 995 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE && 996 "Table isn't big enough!"); 997 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 998 } 999 1000 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1001 /// does not work with the specified type and indicate what to do abort 1002 /// it. NOTE: All indexed mode loads are initialized to Expand in 1003 /// TargetLowering.cpp 1004 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1005 LegalizeAction Action) { 1006 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1007 IdxMode < ISD::LAST_INDEXED_MODE && 1008 (unsigned)Action < 0xf && 1009 "Table isn't big enough!"); 1010 // Load action are kept in the upper half. 1011 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1012 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1013 } 1014 1015 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1016 /// does not work with the specified type and indicate what to do about 1017 /// it. NOTE: All indexed mode stores are initialized to Expand in 1018 /// TargetLowering.cpp 1019 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1020 LegalizeAction Action) { 1021 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1022 IdxMode < ISD::LAST_INDEXED_MODE && 1023 (unsigned)Action < 0xf && 1024 "Table isn't big enough!"); 1025 // Store action are kept in the lower half. 1026 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1027 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1028 } 1029 1030 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1031 /// supported on the target and indicate what to do about it. 1032 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1033 LegalizeAction Action) { 1034 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1035 (unsigned)CC < array_lengthof(CondCodeActions) && 1036 "Table isn't big enough!"); 1037 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1038 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1039 } 1040 1041 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1042 /// promotion code defaults to trying a larger integer/fp until it can find 1043 /// one that works. If that default is insufficient, this method can be used 1044 /// by the target to override the default. 1045 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1046 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1047 } 1048 1049 /// setTargetDAGCombine - Targets should invoke this method for each target 1050 /// independent node that they want to provide a custom DAG combiner for by 1051 /// implementing the PerformDAGCombine virtual method. 1052 void setTargetDAGCombine(ISD::NodeType NT) { 1053 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1054 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1055 } 1056 1057 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1058 /// bytes); default is 200 1059 void setJumpBufSize(unsigned Size) { 1060 JumpBufSize = Size; 1061 } 1062 1063 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1064 /// alignment (in bytes); default is 0 1065 void setJumpBufAlignment(unsigned Align) { 1066 JumpBufAlignment = Align; 1067 } 1068 1069 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1070 /// limit (in number of instructions); default is 2. 1071 void setIfCvtBlockSizeLimit(unsigned Limit) { 1072 IfCvtBlockSizeLimit = Limit; 1073 } 1074 1075 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1076 /// of instructions) to be considered for code duplication during 1077 /// if-conversion; default is 2. 1078 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1079 IfCvtDupBlockSizeLimit = Limit; 1080 } 1081 1082 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1083 /// alignment is zero, it means the target does not care about loop alignment. 1084 void setPrefLoopAlignment(unsigned Align) { 1085 PrefLoopAlignment = Align; 1086 } 1087 1088public: 1089 //===--------------------------------------------------------------------===// 1090 // Lowering methods - These methods must be implemented by targets so that 1091 // the SelectionDAGLowering code knows how to lower these. 1092 // 1093 1094 /// LowerFormalArguments - This hook must be implemented to lower the 1095 /// incoming (formal) arguments, described by the Ins array, into the 1096 /// specified DAG. The implementation should fill in the InVals array 1097 /// with legal-type argument values, and return the resulting token 1098 /// chain value. 1099 /// 1100 virtual SDValue 1101 LowerFormalArguments(SDValue Chain, 1102 CallingConv::ID CallConv, bool isVarArg, 1103 const SmallVectorImpl<ISD::InputArg> &Ins, 1104 DebugLoc dl, SelectionDAG &DAG, 1105 SmallVectorImpl<SDValue> &InVals) const { 1106 assert(0 && "Not Implemented"); 1107 return SDValue(); // this is here to silence compiler errors 1108 } 1109 1110 /// LowerCallTo - This function lowers an abstract call to a function into an 1111 /// actual call. This returns a pair of operands. The first element is the 1112 /// return value for the function (if RetTy is not VoidTy). The second 1113 /// element is the outgoing token chain. It calls LowerCall to do the actual 1114 /// lowering. 1115 struct ArgListEntry { 1116 SDValue Node; 1117 const Type* Ty; 1118 bool isSExt : 1; 1119 bool isZExt : 1; 1120 bool isInReg : 1; 1121 bool isSRet : 1; 1122 bool isNest : 1; 1123 bool isByVal : 1; 1124 uint16_t Alignment; 1125 1126 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1127 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1128 }; 1129 typedef std::vector<ArgListEntry> ArgListTy; 1130 std::pair<SDValue, SDValue> 1131 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1132 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1133 CallingConv::ID CallConv, bool isTailCall, 1134 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1135 SelectionDAG &DAG, DebugLoc dl) const; 1136 1137 /// LowerCall - This hook must be implemented to lower calls into the 1138 /// the specified DAG. The outgoing arguments to the call are described 1139 /// by the Outs array, and the values to be returned by the call are 1140 /// described by the Ins array. The implementation should fill in the 1141 /// InVals array with legal-type return values from the call, and return 1142 /// the resulting token chain value. 1143 virtual SDValue 1144 LowerCall(SDValue Chain, SDValue Callee, 1145 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 1146 const SmallVectorImpl<ISD::OutputArg> &Outs, 1147 const SmallVectorImpl<ISD::InputArg> &Ins, 1148 DebugLoc dl, SelectionDAG &DAG, 1149 SmallVectorImpl<SDValue> &InVals) const { 1150 assert(0 && "Not Implemented"); 1151 return SDValue(); // this is here to silence compiler errors 1152 } 1153 1154 /// CanLowerReturn - This hook should be implemented to check whether the 1155 /// return values described by the Outs array can fit into the return 1156 /// registers. If false is returned, an sret-demotion is performed. 1157 /// 1158 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1159 const SmallVectorImpl<EVT> &OutTys, 1160 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1161 SelectionDAG &DAG) const 1162 { 1163 // Return true by default to get preexisting behavior. 1164 return true; 1165 } 1166 1167 /// LowerReturn - This hook must be implemented to lower outgoing 1168 /// return values, described by the Outs array, into the specified 1169 /// DAG. The implementation should return the resulting token chain 1170 /// value. 1171 /// 1172 virtual SDValue 1173 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1174 const SmallVectorImpl<ISD::OutputArg> &Outs, 1175 DebugLoc dl, SelectionDAG &DAG) const { 1176 assert(0 && "Not Implemented"); 1177 return SDValue(); // this is here to silence compiler errors 1178 } 1179 1180 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1181 /// to legalize nodes with an illegal operand type but legal result types. 1182 /// It replaces the LowerOperation callback in the type Legalizer. 1183 /// The reason we can not do away with LowerOperation entirely is that 1184 /// LegalizeDAG isn't yet ready to use this callback. 1185 /// TODO: Consider merging with ReplaceNodeResults. 1186 1187 /// The target places new result values for the node in Results (their number 1188 /// and types must exactly match those of the original return values of 1189 /// the node), or leaves Results empty, which indicates that the node is not 1190 /// to be custom lowered after all. 1191 /// The default implementation calls LowerOperation. 1192 virtual void LowerOperationWrapper(SDNode *N, 1193 SmallVectorImpl<SDValue> &Results, 1194 SelectionDAG &DAG) const; 1195 1196 /// LowerOperation - This callback is invoked for operations that are 1197 /// unsupported by the target, which are registered to use 'custom' lowering, 1198 /// and whose defined values are all legal. 1199 /// If the target has no operations that require custom lowering, it need not 1200 /// implement this. The default implementation of this aborts. 1201 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1202 1203 /// ReplaceNodeResults - This callback is invoked when a node result type is 1204 /// illegal for the target, and the operation was registered to use 'custom' 1205 /// lowering for that result type. The target places new result values for 1206 /// the node in Results (their number and types must exactly match those of 1207 /// the original return values of the node), or leaves Results empty, which 1208 /// indicates that the node is not to be custom lowered after all. 1209 /// 1210 /// If the target has no operations that require custom lowering, it need not 1211 /// implement this. The default implementation aborts. 1212 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1213 SelectionDAG &DAG) const { 1214 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1215 } 1216 1217 /// getTargetNodeName() - This method returns the name of a target specific 1218 /// DAG node. 1219 virtual const char *getTargetNodeName(unsigned Opcode) const; 1220 1221 /// createFastISel - This method returns a target specific FastISel object, 1222 /// or null if the target does not support "fast" ISel. 1223 virtual FastISel * 1224 createFastISel(MachineFunction &, 1225 DenseMap<const Value *, unsigned> &, 1226 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1227 DenseMap<const AllocaInst *, int> &, 1228 std::vector<std::pair<MachineInstr*, unsigned> > & 1229#ifndef NDEBUG 1230 , SmallSet<const Instruction *, 8> &CatchInfoLost 1231#endif 1232 ) const { 1233 return 0; 1234 } 1235 1236 //===--------------------------------------------------------------------===// 1237 // Inline Asm Support hooks 1238 // 1239 1240 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1241 /// call to be explicit llvm code if it wants to. This is useful for 1242 /// turning simple inline asms into LLVM intrinsics, which gives the 1243 /// compiler more information about the behavior of the code. 1244 virtual bool ExpandInlineAsm(CallInst *CI) const { 1245 return false; 1246 } 1247 1248 enum ConstraintType { 1249 C_Register, // Constraint represents specific register(s). 1250 C_RegisterClass, // Constraint represents any of register(s) in class. 1251 C_Memory, // Memory constraint. 1252 C_Other, // Something else. 1253 C_Unknown // Unsupported constraint. 1254 }; 1255 1256 /// AsmOperandInfo - This contains information for each constraint that we are 1257 /// lowering. 1258 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1259 /// ConstraintCode - This contains the actual string for the code, like "m". 1260 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1261 /// most closely matches the operand. 1262 std::string ConstraintCode; 1263 1264 /// ConstraintType - Information about the constraint code, e.g. Register, 1265 /// RegisterClass, Memory, Other, Unknown. 1266 TargetLowering::ConstraintType ConstraintType; 1267 1268 /// CallOperandval - If this is the result output operand or a 1269 /// clobber, this is null, otherwise it is the incoming operand to the 1270 /// CallInst. This gets modified as the asm is processed. 1271 Value *CallOperandVal; 1272 1273 /// ConstraintVT - The ValueType for the operand value. 1274 EVT ConstraintVT; 1275 1276 /// isMatchingInputConstraint - Return true of this is an input operand that 1277 /// is a matching constraint like "4". 1278 bool isMatchingInputConstraint() const; 1279 1280 /// getMatchedOperand - If this is an input matching constraint, this method 1281 /// returns the output operand it matches. 1282 unsigned getMatchedOperand() const; 1283 1284 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1285 : InlineAsm::ConstraintInfo(info), 1286 ConstraintType(TargetLowering::C_Unknown), 1287 CallOperandVal(0), ConstraintVT(MVT::Other) { 1288 } 1289 }; 1290 1291 /// ComputeConstraintToUse - Determines the constraint code and constraint 1292 /// type to use for the specific AsmOperandInfo, setting 1293 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1294 /// being passed in is available, it can be passed in as Op, otherwise an 1295 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1296 /// constraint of the inline asm instruction being processed is 'm'. 1297 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1298 SDValue Op, 1299 bool hasMemory, 1300 SelectionDAG *DAG = 0) const; 1301 1302 /// getConstraintType - Given a constraint, return the type of constraint it 1303 /// is for this target. 1304 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1305 1306 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1307 /// return a list of registers that can be used to satisfy the constraint. 1308 /// This should only be used for C_RegisterClass constraints. 1309 virtual std::vector<unsigned> 1310 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1311 EVT VT) const; 1312 1313 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1314 /// {edx}), return the register number and the register class for the 1315 /// register. 1316 /// 1317 /// Given a register class constraint, like 'r', if this corresponds directly 1318 /// to an LLVM register class, return a register of 0 and the register class 1319 /// pointer. 1320 /// 1321 /// This should only be used for C_Register constraints. On error, 1322 /// this returns a register number of 0 and a null register class pointer.. 1323 virtual std::pair<unsigned, const TargetRegisterClass*> 1324 getRegForInlineAsmConstraint(const std::string &Constraint, 1325 EVT VT) const; 1326 1327 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1328 /// with another that has more specific requirements based on the type of the 1329 /// corresponding operand. This returns null if there is no replacement to 1330 /// make. 1331 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1332 1333 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1334 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1335 /// it means one of the asm constraint of the inline asm instruction being 1336 /// processed is 'm'. 1337 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1338 bool hasMemory, 1339 std::vector<SDValue> &Ops, 1340 SelectionDAG &DAG) const; 1341 1342 //===--------------------------------------------------------------------===// 1343 // Instruction Emitting Hooks 1344 // 1345 1346 // EmitInstrWithCustomInserter - This method should be implemented by targets 1347 // that mark instructions with the 'usesCustomInserter' flag. These 1348 // instructions are special in various ways, which require special support to 1349 // insert. The specified MachineInstr is created but not inserted into any 1350 // basic blocks, and this method is called to expand it into a sequence of 1351 // instructions, potentially also creating new basic blocks and control flow. 1352 virtual MachineBasicBlock * 1353 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 1354 1355 //===--------------------------------------------------------------------===// 1356 // Addressing mode description hooks (used by LSR etc). 1357 // 1358 1359 /// AddrMode - This represents an addressing mode of: 1360 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1361 /// If BaseGV is null, there is no BaseGV. 1362 /// If BaseOffs is zero, there is no base offset. 1363 /// If HasBaseReg is false, there is no base register. 1364 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1365 /// no scale. 1366 /// 1367 struct AddrMode { 1368 GlobalValue *BaseGV; 1369 int64_t BaseOffs; 1370 bool HasBaseReg; 1371 int64_t Scale; 1372 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1373 }; 1374 1375 /// isLegalAddressingMode - Return true if the addressing mode represented by 1376 /// AM is legal for this target, for a load/store of the specified type. 1377 /// The type may be VoidTy, in which case only return true if the addressing 1378 /// mode is legal for a load/store of any legal type. 1379 /// TODO: Handle pre/postinc as well. 1380 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1381 1382 /// isTruncateFree - Return true if it's free to truncate a value of 1383 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1384 /// register EAX to i16 by referencing its sub-register AX. 1385 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1386 return false; 1387 } 1388 1389 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1390 return false; 1391 } 1392 1393 /// isZExtFree - Return true if any actual instruction that defines a 1394 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1395 /// register. This does not necessarily include registers defined in 1396 /// unknown ways, such as incoming arguments, or copies from unknown 1397 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1398 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1399 /// all instructions that define 32-bit values implicit zero-extend the 1400 /// result out to 64 bits. 1401 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1402 return false; 1403 } 1404 1405 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1406 return false; 1407 } 1408 1409 /// isNarrowingProfitable - Return true if it's profitable to narrow 1410 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1411 /// from i32 to i8 but not from i32 to i16. 1412 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1413 return false; 1414 } 1415 1416 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1417 /// icmp immediate, that is the target has icmp instructions which can compare 1418 /// a register against the immediate without having to materialize the 1419 /// immediate into a register. 1420 virtual bool isLegalICmpImmediate(int64_t Imm) const { 1421 return true; 1422 } 1423 1424 //===--------------------------------------------------------------------===// 1425 // Div utility functions 1426 // 1427 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1428 std::vector<SDNode*>* Created) const; 1429 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1430 std::vector<SDNode*>* Created) const; 1431 1432 1433 //===--------------------------------------------------------------------===// 1434 // Runtime Library hooks 1435 // 1436 1437 /// setLibcallName - Rename the default libcall routine name for the specified 1438 /// libcall. 1439 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1440 LibcallRoutineNames[Call] = Name; 1441 } 1442 1443 /// getLibcallName - Get the libcall routine name for the specified libcall. 1444 /// 1445 const char *getLibcallName(RTLIB::Libcall Call) const { 1446 return LibcallRoutineNames[Call]; 1447 } 1448 1449 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1450 /// result of the comparison libcall against zero. 1451 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1452 CmpLibcallCCs[Call] = CC; 1453 } 1454 1455 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1456 /// the comparison libcall against zero. 1457 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1458 return CmpLibcallCCs[Call]; 1459 } 1460 1461 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1462 /// specified libcall. 1463 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1464 LibcallCallingConvs[Call] = CC; 1465 } 1466 1467 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1468 /// specified libcall. 1469 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1470 return LibcallCallingConvs[Call]; 1471 } 1472 1473private: 1474 const TargetMachine &TM; 1475 const TargetData *TD; 1476 const TargetLoweringObjectFile &TLOF; 1477 1478 /// PointerTy - The type to use for pointers, usually i32 or i64. 1479 /// 1480 MVT PointerTy; 1481 1482 /// IsLittleEndian - True if this is a little endian target. 1483 /// 1484 bool IsLittleEndian; 1485 1486 /// SelectIsExpensive - Tells the code generator not to expand operations 1487 /// into sequences that use the select operations if possible. 1488 bool SelectIsExpensive; 1489 1490 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1491 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1492 /// a real cost model is in place. If we ever optimize for size, this will be 1493 /// set to true unconditionally. 1494 bool IntDivIsCheap; 1495 1496 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1497 /// srl/add/sra for a signed divide by power of two, and let the target handle 1498 /// it. 1499 bool Pow2DivIsCheap; 1500 1501 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1502 /// llvm.setjmp. Defaults to false. 1503 bool UseUnderscoreSetJmp; 1504 1505 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1506 /// llvm.longjmp. Defaults to false. 1507 bool UseUnderscoreLongJmp; 1508 1509 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1510 /// PointerTy is. 1511 MVT ShiftAmountTy; 1512 1513 /// BooleanContents - Information about the contents of the high-bits in 1514 /// boolean values held in a type wider than i1. See getBooleanContents. 1515 BooleanContent BooleanContents; 1516 1517 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1518 /// total cycles or lowest register usage. 1519 Sched::Preference SchedPreferenceInfo; 1520 1521 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1522 unsigned JumpBufSize; 1523 1524 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1525 /// buffers 1526 unsigned JumpBufAlignment; 1527 1528 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1529 /// if-converted. 1530 unsigned IfCvtBlockSizeLimit; 1531 1532 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1533 /// duplicated during if-conversion. 1534 unsigned IfCvtDupBlockSizeLimit; 1535 1536 /// PrefLoopAlignment - The perferred loop alignment. 1537 /// 1538 unsigned PrefLoopAlignment; 1539 1540 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1541 /// specifies the register that llvm.savestack/llvm.restorestack should save 1542 /// and restore. 1543 unsigned StackPointerRegisterToSaveRestore; 1544 1545 /// ExceptionPointerRegister - If set to a physical register, this specifies 1546 /// the register that receives the exception address on entry to a landing 1547 /// pad. 1548 unsigned ExceptionPointerRegister; 1549 1550 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1551 /// the register that receives the exception typeid on entry to a landing 1552 /// pad. 1553 unsigned ExceptionSelectorRegister; 1554 1555 /// RegClassForVT - This indicates the default register class to use for 1556 /// each ValueType the target supports natively. 1557 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1558 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1559 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1560 1561 /// Synthesizable indicates whether it is OK for the compiler to create new 1562 /// operations using this type. All Legal types are Synthesizable except 1563 /// MMX types on X86. Non-Legal types are not Synthesizable. 1564 bool Synthesizable[MVT::LAST_VALUETYPE]; 1565 1566 /// TransformToType - For any value types we are promoting or expanding, this 1567 /// contains the value type that we are changing to. For Expanded types, this 1568 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1569 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1570 /// by the system, this holds the same type (e.g. i32 -> i32). 1571 EVT TransformToType[MVT::LAST_VALUETYPE]; 1572 1573 /// OpActions - For each operation and each value type, keep a LegalizeAction 1574 /// that indicates how instruction selection should deal with the operation. 1575 /// Most operations are Legal (aka, supported natively by the target), but 1576 /// operations that are not should be described. Note that operations on 1577 /// non-legal value types are not described here. 1578 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1579 1580 /// LoadExtActions - For each load extension type and each value type, 1581 /// keep a LegalizeAction that indicates how instruction selection should deal 1582 /// with a load of a specific value type and extension type. 1583 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1584 1585 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1586 /// indicates whether a truncating store of a specific value type and 1587 /// truncating type is legal. 1588 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1589 1590 /// IndexedModeActions - For each indexed mode and each value type, 1591 /// keep a pair of LegalizeAction that indicates how instruction 1592 /// selection should deal with the load / store. The first dimension is the 1593 /// value_type for the reference. The second dimension represents the various 1594 /// modes for load store. 1595 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1596 1597 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1598 /// LegalizeAction that indicates how instruction selection should 1599 /// deal with the condition code. 1600 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1601 1602 ValueTypeActionImpl ValueTypeActions; 1603 1604 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1605 1606 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1607 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1608 /// which sets a bit in this array. 1609 unsigned char 1610 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1611 1612 /// PromoteToType - For operations that must be promoted to a specific type, 1613 /// this holds the destination type. This map should be sparse, so don't hold 1614 /// it as an array. 1615 /// 1616 /// Targets add entries to this map with AddPromotedToType(..), clients access 1617 /// this with getTypeToPromoteTo(..). 1618 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1619 PromoteToType; 1620 1621 /// LibcallRoutineNames - Stores the name each libcall. 1622 /// 1623 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1624 1625 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1626 /// of each of the comparison libcall against zero. 1627 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1628 1629 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1630 /// libcall. 1631 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1632 1633protected: 1634 /// When lowering \@llvm.memset this field specifies the maximum number of 1635 /// store operations that may be substituted for the call to memset. Targets 1636 /// must set this value based on the cost threshold for that target. Targets 1637 /// should assume that the memset will be done using as many of the largest 1638 /// store operations first, followed by smaller ones, if necessary, per 1639 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1640 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1641 /// store. This only applies to setting a constant array of a constant size. 1642 /// @brief Specify maximum number of store instructions per memset call. 1643 unsigned maxStoresPerMemset; 1644 1645 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1646 /// store operations that may be substituted for a call to memcpy. Targets 1647 /// must set this value based on the cost threshold for that target. Targets 1648 /// should assume that the memcpy will be done using as many of the largest 1649 /// store operations first, followed by smaller ones, if necessary, per 1650 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1651 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1652 /// and one 1-byte store. This only applies to copying a constant array of 1653 /// constant size. 1654 /// @brief Specify maximum bytes of store instructions per memcpy call. 1655 unsigned maxStoresPerMemcpy; 1656 1657 /// When lowering \@llvm.memmove this field specifies the maximum number of 1658 /// store instructions that may be substituted for a call to memmove. Targets 1659 /// must set this value based on the cost threshold for that target. Targets 1660 /// should assume that the memmove will be done using as many of the largest 1661 /// store operations first, followed by smaller ones, if necessary, per 1662 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1663 /// with 8-bit alignment would result in nine 1-byte stores. This only 1664 /// applies to copying a constant array of constant size. 1665 /// @brief Specify maximum bytes of store instructions per memmove call. 1666 unsigned maxStoresPerMemmove; 1667 1668 /// This field specifies whether the target can benefit from code placement 1669 /// optimization. 1670 bool benefitFromCodePlacementOpt; 1671}; 1672} // end llvm namespace 1673 1674#endif 1675