TargetLowering.h revision 25cf2275ff7de3de3bc0e508abaf457413d74725
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/Constants.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Instructions.h" 28#include "llvm/CodeGen/SelectionDAGNodes.h" 29#include "llvm/CodeGen/RuntimeLibcalls.h" 30#include "llvm/ADT/APFloat.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/SmallSet.h" 33#include "llvm/ADT/STLExtras.h" 34#include <map> 35#include <vector> 36 37namespace llvm { 38 class AllocaInst; 39 class Function; 40 class FastISel; 41 class MachineBasicBlock; 42 class MachineFunction; 43 class MachineFrameInfo; 44 class MachineInstr; 45 class MachineModuleInfo; 46 class SDNode; 47 class SDValue; 48 class SelectionDAG; 49 class TargetData; 50 class TargetMachine; 51 class TargetRegisterClass; 52 class TargetSubtarget; 53 class Value; 54 class VectorType; 55 56//===----------------------------------------------------------------------===// 57/// TargetLowering - This class defines information used to lower LLVM code to 58/// legal SelectionDAG operators that the target instruction selector can accept 59/// natively. 60/// 61/// This class also defines callbacks that targets must implement to lower 62/// target-specific constructs to SelectionDAG operators. 63/// 64class TargetLowering { 65public: 66 /// LegalizeAction - This enum indicates whether operations are valid for a 67 /// target, and if not, what action should be used to make them valid. 68 enum LegalizeAction { 69 Legal, // The target natively supports this operation. 70 Promote, // This operation should be executed in a larger type. 71 Expand, // Try to expand this to other ops, otherwise use a libcall. 72 Custom // Use the LowerOperation hook to implement custom lowering. 73 }; 74 75 enum OutOfRangeShiftAmount { 76 Undefined, // Oversized shift amounts are undefined (default). 77 Mask, // Shift amounts are auto masked (anded) to value size. 78 Extend // Oversized shift pulls in zeros or sign bits. 79 }; 80 81 enum BooleanContent { // How the target represents true/false values. 82 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 83 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 84 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 85 }; 86 87 enum SchedPreference { 88 SchedulingForLatency, // Scheduling for shortest total latency. 89 SchedulingForRegPressure // Scheduling for lowest register pressure. 90 }; 91 92 explicit TargetLowering(TargetMachine &TM); 93 virtual ~TargetLowering(); 94 95 TargetMachine &getTargetMachine() const { return TM; } 96 const TargetData *getTargetData() const { return TD; } 97 98 bool isBigEndian() const { return !IsLittleEndian; } 99 bool isLittleEndian() const { return IsLittleEndian; } 100 MVT getPointerTy() const { return PointerTy; } 101 MVT getShiftAmountTy() const { return ShiftAmountTy; } 102 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 103 104 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 105 /// codegen. 106 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 107 108 /// isSelectExpensive - Return true if the select operation is expensive for 109 /// this target. 110 bool isSelectExpensive() const { return SelectIsExpensive; } 111 112 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 113 /// a sequence of several shifts, adds, and multiplies for this target. 114 bool isIntDivCheap() const { return IntDivIsCheap; } 115 116 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 117 /// srl/add/sra. 118 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 119 120 /// getSetCCResultType - Return the ValueType of the result of setcc 121 /// operations. 122 virtual MVT getSetCCResultType(const SDValue &) const; 123 124 /// getBooleanContents - For targets without i1 registers, this gives the 125 /// nature of the high-bits of boolean values held in types wider than i1. 126 /// "Boolean values" are special true/false values produced by nodes like 127 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 128 /// Not to be confused with general values promoted from i1. 129 BooleanContent getBooleanContents() const { return BooleanContents;} 130 131 /// getSchedulingPreference - Return target scheduling preference. 132 SchedPreference getSchedulingPreference() const { 133 return SchedPreferenceInfo; 134 } 135 136 /// getRegClassFor - Return the register class that should be used for the 137 /// specified value type. This may only be called on legal types. 138 TargetRegisterClass *getRegClassFor(MVT VT) const { 139 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 140 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()]; 141 assert(RC && "This value type is not natively supported!"); 142 return RC; 143 } 144 145 /// isTypeLegal - Return true if the target has native support for the 146 /// specified value type. This means that it has a register that directly 147 /// holds it without promotions or expansions. 148 bool isTypeLegal(MVT VT) const { 149 assert(!VT.isSimple() || 150 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 151 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0; 152 } 153 154 class ValueTypeActionImpl { 155 /// ValueTypeActions - This is a bitvector that contains two bits for each 156 /// value type, where the two bits correspond to the LegalizeAction enum. 157 /// This can be queried with "getTypeAction(VT)". 158 uint32_t ValueTypeActions[2]; 159 public: 160 ValueTypeActionImpl() { 161 ValueTypeActions[0] = ValueTypeActions[1] = 0; 162 } 163 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 164 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 165 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 166 } 167 168 LegalizeAction getTypeAction(MVT VT) const { 169 if (VT.isExtended()) { 170 if (VT.isVector()) { 171 // First try vector widening 172 return Promote; 173 } 174 if (VT.isInteger()) 175 // First promote to a power-of-two size, then expand if necessary. 176 return VT == VT.getRoundIntegerType() ? Expand : Promote; 177 assert(0 && "Unsupported extended type!"); 178 return Legal; 179 } 180 unsigned I = VT.getSimpleVT(); 181 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 182 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 183 } 184 void setTypeAction(MVT VT, LegalizeAction Action) { 185 unsigned I = VT.getSimpleVT(); 186 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 187 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 188 } 189 }; 190 191 const ValueTypeActionImpl &getValueTypeActions() const { 192 return ValueTypeActions; 193 } 194 195 /// getTypeAction - Return how we should legalize values of this type, either 196 /// it is already legal (return 'Legal') or we need to promote it to a larger 197 /// type (return 'Promote'), or we need to expand it into multiple registers 198 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 199 LegalizeAction getTypeAction(MVT VT) const { 200 return ValueTypeActions.getTypeAction(VT); 201 } 202 203 /// getTypeToTransformTo - For types supported by the target, this is an 204 /// identity function. For types that must be promoted to larger types, this 205 /// returns the larger type to promote to. For integer types that are larger 206 /// than the largest integer register, this contains one step in the expansion 207 /// to get to the smaller register. For illegal floating point types, this 208 /// returns the integer type to transform to. 209 MVT getTypeToTransformTo(MVT VT) const { 210 if (VT.isSimple()) { 211 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType)); 212 MVT NVT = TransformToType[VT.getSimpleVT()]; 213 assert(getTypeAction(NVT) != Promote && 214 "Promote may not follow Expand or Promote"); 215 return NVT; 216 } 217 218 if (VT.isVector()) { 219 unsigned NumElts = VT.getVectorNumElements(); 220 MVT EltVT = VT.getVectorElementType(); 221 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2); 222 } else if (VT.isInteger()) { 223 MVT NVT = VT.getRoundIntegerType(); 224 if (NVT == VT) 225 // Size is a power of two - expand to half the size. 226 return MVT::getIntegerVT(VT.getSizeInBits() / 2); 227 else 228 // Promote to a power of two size, avoiding multi-step promotion. 229 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 230 } 231 assert(0 && "Unsupported extended type!"); 232 return MVT(); // Not reached 233 } 234 235 /// getTypeToExpandTo - For types supported by the target, this is an 236 /// identity function. For types that must be expanded (i.e. integer types 237 /// that are larger than the largest integer register or illegal floating 238 /// point types), this returns the largest legal type it will be expanded to. 239 MVT getTypeToExpandTo(MVT VT) const { 240 assert(!VT.isVector()); 241 while (true) { 242 switch (getTypeAction(VT)) { 243 case Legal: 244 return VT; 245 case Expand: 246 VT = getTypeToTransformTo(VT); 247 break; 248 default: 249 assert(false && "Type is not legal nor is it to be expanded!"); 250 return VT; 251 } 252 } 253 return VT; 254 } 255 256 /// getVectorTypeBreakdown - Vector types are broken down into some number of 257 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 258 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 259 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 260 /// 261 /// This method returns the number of registers needed, and the VT for each 262 /// register. It also returns the VT and quantity of the intermediate values 263 /// before they are promoted/expanded. 264 /// 265 unsigned getVectorTypeBreakdown(MVT VT, 266 MVT &IntermediateVT, 267 unsigned &NumIntermediates, 268 MVT &RegisterVT) const; 269 270 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 271 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 272 /// this is the case, it returns true and store the intrinsic 273 /// information into the IntrinsicInfo that was passed to the function. 274 typedef struct IntrinsicInfo { 275 unsigned opc; // target opcode 276 MVT memVT; // memory VT 277 const Value* ptrVal; // value representing memory location 278 int offset; // offset off of ptrVal 279 unsigned align; // alignment 280 bool vol; // is volatile? 281 bool readMem; // reads memory? 282 bool writeMem; // writes memory? 283 } IntrinisicInfo; 284 285 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 286 CallInst &I, unsigned Intrinsic) { 287 return false; 288 } 289 290 /// getWidenVectorType: given a vector type, returns the type to widen to 291 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 292 /// If there is no vector type that we want to widen to, returns MVT::Other 293 /// When and were to widen is target dependent based on the cost of 294 /// scalarizing vs using the wider vector type. 295 virtual MVT getWidenVectorType(MVT VT); 296 297 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 298 legal_fpimm_iterator legal_fpimm_begin() const { 299 return LegalFPImmediates.begin(); 300 } 301 legal_fpimm_iterator legal_fpimm_end() const { 302 return LegalFPImmediates.end(); 303 } 304 305 /// isShuffleMaskLegal - Targets can use this to indicate that they only 306 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 307 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 308 /// are assumed to be legal. 309 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const { 310 return true; 311 } 312 313 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 314 /// used by Targets can use this to indicate if there is a suitable 315 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 316 /// pool entry. 317 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, 318 MVT EVT, 319 SelectionDAG &DAG) const { 320 return false; 321 } 322 323 /// getOperationAction - Return how this operation should be treated: either 324 /// it is legal, needs to be promoted to a larger size, needs to be 325 /// expanded to some other code sequence, or the target has a custom expander 326 /// for it. 327 LegalizeAction getOperationAction(unsigned Op, MVT VT) const { 328 if (VT.isExtended()) return Expand; 329 assert(Op < array_lengthof(OpActions) && 330 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 331 "Table isn't big enough!"); 332 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3); 333 } 334 335 /// isOperationLegal - Return true if the specified operation is legal on this 336 /// target. 337 bool isOperationLegal(unsigned Op, MVT VT) const { 338 return (VT == MVT::Other || isTypeLegal(VT)) && 339 (getOperationAction(Op, VT) == Legal || 340 getOperationAction(Op, VT) == Custom); 341 } 342 343 /// getLoadExtAction - Return how this load with extension should be treated: 344 /// either it is legal, needs to be promoted to a larger size, needs to be 345 /// expanded to some other code sequence, or the target has a custom expander 346 /// for it. 347 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const { 348 assert(LType < array_lengthof(LoadExtActions) && 349 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 350 "Table isn't big enough!"); 351 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3); 352 } 353 354 /// isLoadExtLegal - Return true if the specified load with extension is legal 355 /// on this target. 356 bool isLoadExtLegal(unsigned LType, MVT VT) const { 357 return VT.isSimple() && 358 (getLoadExtAction(LType, VT) == Legal || 359 getLoadExtAction(LType, VT) == Custom); 360 } 361 362 /// getTruncStoreAction - Return how this store with truncation should be 363 /// treated: either it is legal, needs to be promoted to a larger size, needs 364 /// to be expanded to some other code sequence, or the target has a custom 365 /// expander for it. 366 LegalizeAction getTruncStoreAction(MVT ValVT, 367 MVT MemVT) const { 368 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 369 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 370 "Table isn't big enough!"); 371 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >> 372 (2*MemVT.getSimpleVT())) & 3); 373 } 374 375 /// isTruncStoreLegal - Return true if the specified store with truncation is 376 /// legal on this target. 377 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const { 378 return isTypeLegal(ValVT) && MemVT.isSimple() && 379 (getTruncStoreAction(ValVT, MemVT) == Legal || 380 getTruncStoreAction(ValVT, MemVT) == Custom); 381 } 382 383 /// getIndexedLoadAction - Return how the indexed load should be treated: 384 /// either it is legal, needs to be promoted to a larger size, needs to be 385 /// expanded to some other code sequence, or the target has a custom expander 386 /// for it. 387 LegalizeAction 388 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 389 assert(IdxMode < array_lengthof(IndexedModeActions[0]) && 390 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 && 391 "Table isn't big enough!"); 392 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> 393 (2*VT.getSimpleVT())) & 3); 394 } 395 396 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 397 /// on this target. 398 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const { 399 return VT.isSimple() && 400 (getIndexedLoadAction(IdxMode, VT) == Legal || 401 getIndexedLoadAction(IdxMode, VT) == Custom); 402 } 403 404 /// getIndexedStoreAction - Return how the indexed store should be treated: 405 /// either it is legal, needs to be promoted to a larger size, needs to be 406 /// expanded to some other code sequence, or the target has a custom expander 407 /// for it. 408 LegalizeAction 409 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 410 assert(IdxMode < array_lengthof(IndexedModeActions[1]) && 411 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 412 "Table isn't big enough!"); 413 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> 414 (2*VT.getSimpleVT())) & 3); 415 } 416 417 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 418 /// on this target. 419 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const { 420 return VT.isSimple() && 421 (getIndexedStoreAction(IdxMode, VT) == Legal || 422 getIndexedStoreAction(IdxMode, VT) == Custom); 423 } 424 425 /// getConvertAction - Return how the conversion should be treated: 426 /// either it is legal, needs to be promoted to a larger size, needs to be 427 /// expanded to some other code sequence, or the target has a custom expander 428 /// for it. 429 LegalizeAction 430 getConvertAction(MVT FromVT, MVT ToVT) const { 431 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 432 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 433 "Table isn't big enough!"); 434 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >> 435 (2*ToVT.getSimpleVT())) & 3); 436 } 437 438 /// isConvertLegal - Return true if the specified conversion is legal 439 /// on this target. 440 bool isConvertLegal(MVT FromVT, MVT ToVT) const { 441 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 442 (getConvertAction(FromVT, ToVT) == Legal || 443 getConvertAction(FromVT, ToVT) == Custom); 444 } 445 446 /// getCondCodeAction - Return how the condition code should be treated: 447 /// either it is legal, needs to be expanded to some other code sequence, 448 /// or the target has a custom expander for it. 449 LegalizeAction 450 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 451 assert((unsigned)CC < array_lengthof(CondCodeActions) && 452 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 453 "Table isn't big enough!"); 454 LegalizeAction Action = (LegalizeAction) 455 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3); 456 assert(Action != Promote && "Can't promote condition code!"); 457 return Action; 458 } 459 460 /// isCondCodeLegal - Return true if the specified condition code is legal 461 /// on this target. 462 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 463 return getCondCodeAction(CC, VT) == Legal || 464 getCondCodeAction(CC, VT) == Custom; 465 } 466 467 468 /// getTypeToPromoteTo - If the action for this operation is to promote, this 469 /// method returns the ValueType to promote to. 470 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 471 assert(getOperationAction(Op, VT) == Promote && 472 "This operation isn't promoted!"); 473 474 // See if this has an explicit type specified. 475 std::map<std::pair<unsigned, MVT::SimpleValueType>, 476 MVT::SimpleValueType>::const_iterator PTTI = 477 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT())); 478 if (PTTI != PromoteToType.end()) return PTTI->second; 479 480 assert((VT.isInteger() || VT.isFloatingPoint()) && 481 "Cannot autopromote this type, add it with AddPromotedToType."); 482 483 MVT NVT = VT; 484 do { 485 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1); 486 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 487 "Didn't find type to promote to!"); 488 } while (!isTypeLegal(NVT) || 489 getOperationAction(Op, NVT) == Promote); 490 return NVT; 491 } 492 493 /// getValueType - Return the MVT corresponding to this LLVM type. 494 /// This is fixed by the LLVM operations except for the pointer size. If 495 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 496 /// counterpart (e.g. structs), otherwise it will assert. 497 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 498 MVT VT = MVT::getMVT(Ty, AllowUnknown); 499 return VT == MVT::iPTR ? PointerTy : VT; 500 } 501 502 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 503 /// function arguments in the caller parameter area. This is the actual 504 /// alignment, not its logarithm. 505 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 506 507 /// getRegisterType - Return the type of registers that this ValueType will 508 /// eventually require. 509 MVT getRegisterType(MVT VT) const { 510 if (VT.isSimple()) { 511 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT)); 512 return RegisterTypeForVT[VT.getSimpleVT()]; 513 } 514 if (VT.isVector()) { 515 MVT VT1, RegisterVT; 516 unsigned NumIntermediates; 517 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 518 return RegisterVT; 519 } 520 if (VT.isInteger()) { 521 return getRegisterType(getTypeToTransformTo(VT)); 522 } 523 assert(0 && "Unsupported extended type!"); 524 return MVT(); // Not reached 525 } 526 527 /// getNumRegisters - Return the number of registers that this ValueType will 528 /// eventually require. This is one for any types promoted to live in larger 529 /// registers, but may be more than one for types (like i64) that are split 530 /// into pieces. For types like i140, which are first promoted then expanded, 531 /// it is the number of registers needed to hold all the bits of the original 532 /// type. For an i140 on a 32 bit machine this means 5 registers. 533 unsigned getNumRegisters(MVT VT) const { 534 if (VT.isSimple()) { 535 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT)); 536 return NumRegistersForVT[VT.getSimpleVT()]; 537 } 538 if (VT.isVector()) { 539 MVT VT1, VT2; 540 unsigned NumIntermediates; 541 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 542 } 543 if (VT.isInteger()) { 544 unsigned BitWidth = VT.getSizeInBits(); 545 unsigned RegWidth = getRegisterType(VT).getSizeInBits(); 546 return (BitWidth + RegWidth - 1) / RegWidth; 547 } 548 assert(0 && "Unsupported extended type!"); 549 return 0; // Not reached 550 } 551 552 /// ShouldShrinkFPConstant - If true, then instruction selection should 553 /// seek to shrink the FP constant of the specified type to a smaller type 554 /// in order to save space and / or reduce runtime. 555 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; } 556 557 /// hasTargetDAGCombine - If true, the target has custom DAG combine 558 /// transformations that it can perform for the specified node. 559 bool hasTargetDAGCombine(ISD::NodeType NT) const { 560 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 561 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 562 } 563 564 /// This function returns the maximum number of store operations permitted 565 /// to replace a call to llvm.memset. The value is set by the target at the 566 /// performance threshold for such a replacement. 567 /// @brief Get maximum # of store operations permitted for llvm.memset 568 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 569 570 /// This function returns the maximum number of store operations permitted 571 /// to replace a call to llvm.memcpy. The value is set by the target at the 572 /// performance threshold for such a replacement. 573 /// @brief Get maximum # of store operations permitted for llvm.memcpy 574 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 575 576 /// This function returns the maximum number of store operations permitted 577 /// to replace a call to llvm.memmove. The value is set by the target at the 578 /// performance threshold for such a replacement. 579 /// @brief Get maximum # of store operations permitted for llvm.memmove 580 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 581 582 /// This function returns true if the target allows unaligned memory accesses. 583 /// This is used, for example, in situations where an array copy/move/set is 584 /// converted to a sequence of store operations. It's use helps to ensure that 585 /// such replacements don't generate code that causes an alignment error 586 /// (trap) on the target machine. 587 /// @brief Determine if the target supports unaligned memory accesses. 588 bool allowsUnalignedMemoryAccesses() const { 589 return allowUnalignedMemoryAccesses; 590 } 591 592 /// getOptimalMemOpType - Returns the target specific optimal type for load 593 /// and store operations as a result of memset, memcpy, and memmove lowering. 594 /// It returns MVT::iAny if SelectionDAG should be responsible for 595 /// determining it. 596 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, 597 bool isSrcConst, bool isSrcStr) const { 598 return MVT::iAny; 599 } 600 601 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 602 /// to implement llvm.setjmp. 603 bool usesUnderscoreSetJmp() const { 604 return UseUnderscoreSetJmp; 605 } 606 607 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 608 /// to implement llvm.longjmp. 609 bool usesUnderscoreLongJmp() const { 610 return UseUnderscoreLongJmp; 611 } 612 613 /// getStackPointerRegisterToSaveRestore - If a physical register, this 614 /// specifies the register that llvm.savestack/llvm.restorestack should save 615 /// and restore. 616 unsigned getStackPointerRegisterToSaveRestore() const { 617 return StackPointerRegisterToSaveRestore; 618 } 619 620 /// getExceptionAddressRegister - If a physical register, this returns 621 /// the register that receives the exception address on entry to a landing 622 /// pad. 623 unsigned getExceptionAddressRegister() const { 624 return ExceptionPointerRegister; 625 } 626 627 /// getExceptionSelectorRegister - If a physical register, this returns 628 /// the register that receives the exception typeid on entry to a landing 629 /// pad. 630 unsigned getExceptionSelectorRegister() const { 631 return ExceptionSelectorRegister; 632 } 633 634 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 635 /// set, the default is 200) 636 unsigned getJumpBufSize() const { 637 return JumpBufSize; 638 } 639 640 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 641 /// (if never set, the default is 0) 642 unsigned getJumpBufAlignment() const { 643 return JumpBufAlignment; 644 } 645 646 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 647 /// limit. Any block whose size is greater should not be predicated. 648 unsigned getIfCvtBlockSizeLimit() const { 649 return IfCvtBlockSizeLimit; 650 } 651 652 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 653 /// block to be considered for duplication. Any block whose size is greater 654 /// should not be duplicated to facilitate its predication. 655 unsigned getIfCvtDupBlockSizeLimit() const { 656 return IfCvtDupBlockSizeLimit; 657 } 658 659 /// getPrefLoopAlignment - return the preferred loop alignment. 660 /// 661 unsigned getPrefLoopAlignment() const { 662 return PrefLoopAlignment; 663 } 664 665 /// getPreIndexedAddressParts - returns true by value, base pointer and 666 /// offset pointer and addressing mode by reference if the node's address 667 /// can be legally represented as pre-indexed load / store address. 668 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 669 SDValue &Offset, 670 ISD::MemIndexedMode &AM, 671 SelectionDAG &DAG) { 672 return false; 673 } 674 675 /// getPostIndexedAddressParts - returns true by value, base pointer and 676 /// offset pointer and addressing mode by reference if this node can be 677 /// combined with a load / store to form a post-indexed load / store. 678 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 679 SDValue &Base, SDValue &Offset, 680 ISD::MemIndexedMode &AM, 681 SelectionDAG &DAG) { 682 return false; 683 } 684 685 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 686 /// jumptable. 687 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 688 SelectionDAG &DAG) const; 689 690 /// isOffsetFoldingLegal - Return true if folding a constant offset 691 /// with the given GlobalAddress is legal. It is frequently not legal in 692 /// PIC relocation models. 693 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 694 695 //===--------------------------------------------------------------------===// 696 // TargetLowering Optimization Methods 697 // 698 699 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 700 /// SDValues for returning information from TargetLowering to its clients 701 /// that want to combine 702 struct TargetLoweringOpt { 703 SelectionDAG &DAG; 704 SDValue Old; 705 SDValue New; 706 707 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 708 709 bool CombineTo(SDValue O, SDValue N) { 710 Old = O; 711 New = N; 712 return true; 713 } 714 715 /// ShrinkDemandedConstant - Check to see if the specified operand of the 716 /// specified instruction is a constant integer. If so, check to see if 717 /// there are any bits set in the constant that are not demanded. If so, 718 /// shrink the constant and return true. 719 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 720 }; 721 722 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 723 /// DemandedMask bits of the result of Op are ever used downstream. If we can 724 /// use this information to simplify Op, create a new simplified DAG node and 725 /// return true, returning the original and new nodes in Old and New. 726 /// Otherwise, analyze the expression and return a mask of KnownOne and 727 /// KnownZero bits for the expression (used to simplify the caller). 728 /// The KnownZero/One bits may only be accurate for those bits in the 729 /// DemandedMask. 730 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 731 APInt &KnownZero, APInt &KnownOne, 732 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 733 734 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 735 /// Mask are known to be either zero or one and return them in the 736 /// KnownZero/KnownOne bitsets. 737 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 738 const APInt &Mask, 739 APInt &KnownZero, 740 APInt &KnownOne, 741 const SelectionDAG &DAG, 742 unsigned Depth = 0) const; 743 744 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 745 /// targets that want to expose additional information about sign bits to the 746 /// DAG Combiner. 747 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 748 unsigned Depth = 0) const; 749 750 struct DAGCombinerInfo { 751 void *DC; // The DAG Combiner object. 752 bool BeforeLegalize; 753 bool CalledByLegalizer; 754 public: 755 SelectionDAG &DAG; 756 757 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 758 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 759 760 bool isBeforeLegalize() const { return BeforeLegalize; } 761 bool isCalledByLegalizer() const { return CalledByLegalizer; } 762 763 void AddToWorklist(SDNode *N); 764 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To); 765 SDValue CombineTo(SDNode *N, SDValue Res); 766 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1); 767 }; 768 769 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 770 /// and cc. If it is unable to simplify it, return a null SDValue. 771 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 772 ISD::CondCode Cond, bool foldBooleans, 773 DAGCombinerInfo &DCI) const; 774 775 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 776 /// node is a GlobalAddress + offset. 777 virtual bool 778 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 779 780 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 781 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the 782 /// location that the 'Base' load is loading from. 783 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist, 784 const MachineFrameInfo *MFI) const; 785 786 /// PerformDAGCombine - This method will be invoked for all target nodes and 787 /// for any target-independent nodes that the target has registered with 788 /// invoke it for. 789 /// 790 /// The semantics are as follows: 791 /// Return Value: 792 /// SDValue.Val == 0 - No change was made 793 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 794 /// otherwise - N should be replaced by the returned Operand. 795 /// 796 /// In addition, methods provided by DAGCombinerInfo may be used to perform 797 /// more complex transformations. 798 /// 799 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 800 801 //===--------------------------------------------------------------------===// 802 // TargetLowering Configuration Methods - These methods should be invoked by 803 // the derived class constructor to configure this object for the target. 804 // 805 806protected: 807 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 808 /// GOT for PC-relative code. 809 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 810 811 /// setShiftAmountType - Describe the type that should be used for shift 812 /// amounts. This type defaults to the pointer type. 813 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 814 815 /// setBooleanContents - Specify how the target extends the result of a 816 /// boolean value from i1 to a wider type. See getBooleanContents. 817 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 818 819 /// setSchedulingPreference - Specify the target scheduling preference. 820 void setSchedulingPreference(SchedPreference Pref) { 821 SchedPreferenceInfo = Pref; 822 } 823 824 /// setShiftAmountFlavor - Describe how the target handles out of range shift 825 /// amounts. 826 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 827 ShiftAmtHandling = OORSA; 828 } 829 830 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 831 /// use _setjmp to implement llvm.setjmp or the non _ version. 832 /// Defaults to false. 833 void setUseUnderscoreSetJmp(bool Val) { 834 UseUnderscoreSetJmp = Val; 835 } 836 837 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 838 /// use _longjmp to implement llvm.longjmp or the non _ version. 839 /// Defaults to false. 840 void setUseUnderscoreLongJmp(bool Val) { 841 UseUnderscoreLongJmp = Val; 842 } 843 844 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 845 /// specifies the register that llvm.savestack/llvm.restorestack should save 846 /// and restore. 847 void setStackPointerRegisterToSaveRestore(unsigned R) { 848 StackPointerRegisterToSaveRestore = R; 849 } 850 851 /// setExceptionPointerRegister - If set to a physical register, this sets 852 /// the register that receives the exception address on entry to a landing 853 /// pad. 854 void setExceptionPointerRegister(unsigned R) { 855 ExceptionPointerRegister = R; 856 } 857 858 /// setExceptionSelectorRegister - If set to a physical register, this sets 859 /// the register that receives the exception typeid on entry to a landing 860 /// pad. 861 void setExceptionSelectorRegister(unsigned R) { 862 ExceptionSelectorRegister = R; 863 } 864 865 /// SelectIsExpensive - Tells the code generator not to expand operations 866 /// into sequences that use the select operations if possible. 867 void setSelectIsExpensive() { SelectIsExpensive = true; } 868 869 /// setIntDivIsCheap - Tells the code generator that integer divide is 870 /// expensive, and if possible, should be replaced by an alternate sequence 871 /// of instructions not containing an integer divide. 872 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 873 874 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 875 /// srl/add/sra for a signed divide by power of two, and let the target handle 876 /// it. 877 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 878 879 /// addRegisterClass - Add the specified register class as an available 880 /// regclass for the specified value type. This indicates the selector can 881 /// handle values of that class natively. 882 void addRegisterClass(MVT VT, TargetRegisterClass *RC) { 883 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 884 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 885 RegClassForVT[VT.getSimpleVT()] = RC; 886 } 887 888 /// computeRegisterProperties - Once all of the register classes are added, 889 /// this allows us to compute derived properties we expose. 890 void computeRegisterProperties(); 891 892 /// setOperationAction - Indicate that the specified operation does not work 893 /// with the specified type and indicate what to do about it. 894 void setOperationAction(unsigned Op, MVT VT, 895 LegalizeAction Action) { 896 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 897 Op < array_lengthof(OpActions) && "Table isn't big enough!"); 898 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 899 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2; 900 } 901 902 /// setLoadExtAction - Indicate that the specified load with extension does 903 /// not work with the with specified type and indicate what to do about it. 904 void setLoadExtAction(unsigned ExtType, MVT VT, 905 LegalizeAction Action) { 906 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 907 ExtType < array_lengthof(LoadExtActions) && 908 "Table isn't big enough!"); 909 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 910 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2; 911 } 912 913 /// setTruncStoreAction - Indicate that the specified truncating store does 914 /// not work with the with specified type and indicate what to do about it. 915 void setTruncStoreAction(MVT ValVT, MVT MemVT, 916 LegalizeAction Action) { 917 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 918 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 919 "Table isn't big enough!"); 920 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) << 921 MemVT.getSimpleVT()*2); 922 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action << 923 MemVT.getSimpleVT()*2; 924 } 925 926 /// setIndexedLoadAction - Indicate that the specified indexed load does or 927 /// does not work with the with specified type and indicate what to do abort 928 /// it. NOTE: All indexed mode loads are initialized to Expand in 929 /// TargetLowering.cpp 930 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 931 LegalizeAction Action) { 932 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 && 933 IdxMode < array_lengthof(IndexedModeActions[0]) && 934 "Table isn't big enough!"); 935 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 936 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 937 } 938 939 /// setIndexedStoreAction - Indicate that the specified indexed store does or 940 /// does not work with the with specified type and indicate what to do about 941 /// it. NOTE: All indexed mode stores are initialized to Expand in 942 /// TargetLowering.cpp 943 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 944 LegalizeAction Action) { 945 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 946 IdxMode < array_lengthof(IndexedModeActions[1]) && 947 "Table isn't big enough!"); 948 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 949 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 950 } 951 952 /// setConvertAction - Indicate that the specified conversion does or does 953 /// not work with the with specified type and indicate what to do about it. 954 void setConvertAction(MVT FromVT, MVT ToVT, 955 LegalizeAction Action) { 956 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 957 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 958 "Table isn't big enough!"); 959 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) << 960 ToVT.getSimpleVT()*2); 961 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action << 962 ToVT.getSimpleVT()*2; 963 } 964 965 /// setCondCodeAction - Indicate that the specified condition code is or isn't 966 /// supported on the target and indicate what to do about it. 967 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { 968 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 969 (unsigned)CC < array_lengthof(CondCodeActions) && 970 "Table isn't big enough!"); 971 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 972 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2; 973 } 974 975 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 976 /// promotion code defaults to trying a larger integer/fp until it can find 977 /// one that works. If that default is insufficient, this method can be used 978 /// by the target to override the default. 979 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 980 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] = 981 DestVT.getSimpleVT(); 982 } 983 984 /// addLegalFPImmediate - Indicate that this target can instruction select 985 /// the specified FP immediate natively. 986 void addLegalFPImmediate(const APFloat& Imm) { 987 LegalFPImmediates.push_back(Imm); 988 } 989 990 /// setTargetDAGCombine - Targets should invoke this method for each target 991 /// independent node that they want to provide a custom DAG combiner for by 992 /// implementing the PerformDAGCombine virtual method. 993 void setTargetDAGCombine(ISD::NodeType NT) { 994 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 995 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 996 } 997 998 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 999 /// bytes); default is 200 1000 void setJumpBufSize(unsigned Size) { 1001 JumpBufSize = Size; 1002 } 1003 1004 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1005 /// alignment (in bytes); default is 0 1006 void setJumpBufAlignment(unsigned Align) { 1007 JumpBufAlignment = Align; 1008 } 1009 1010 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1011 /// limit (in number of instructions); default is 2. 1012 void setIfCvtBlockSizeLimit(unsigned Limit) { 1013 IfCvtBlockSizeLimit = Limit; 1014 } 1015 1016 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1017 /// of instructions) to be considered for code duplication during 1018 /// if-conversion; default is 2. 1019 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1020 IfCvtDupBlockSizeLimit = Limit; 1021 } 1022 1023 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1024 /// alignment is zero, it means the target does not care about loop alignment. 1025 void setPrefLoopAlignment(unsigned Align) { 1026 PrefLoopAlignment = Align; 1027 } 1028 1029public: 1030 1031 virtual const TargetSubtarget *getSubtarget() { 1032 assert(0 && "Not Implemented"); 1033 return NULL; // this is here to silence compiler errors 1034 } 1035 //===--------------------------------------------------------------------===// 1036 // Lowering methods - These methods must be implemented by targets so that 1037 // the SelectionDAGLowering code knows how to lower these. 1038 // 1039 1040 /// LowerArguments - This hook must be implemented to indicate how we should 1041 /// lower the arguments for the specified function, into the specified DAG. 1042 virtual void 1043 LowerArguments(Function &F, SelectionDAG &DAG, 1044 SmallVectorImpl<SDValue>& ArgValues); 1045 1046 /// LowerCallTo - This hook lowers an abstract call to a function into an 1047 /// actual call. This returns a pair of operands. The first element is the 1048 /// return value for the function (if RetTy is not VoidTy). The second 1049 /// element is the outgoing token chain. 1050 struct ArgListEntry { 1051 SDValue Node; 1052 const Type* Ty; 1053 bool isSExt : 1; 1054 bool isZExt : 1; 1055 bool isInReg : 1; 1056 bool isSRet : 1; 1057 bool isNest : 1; 1058 bool isByVal : 1; 1059 uint16_t Alignment; 1060 1061 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1062 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1063 }; 1064 typedef std::vector<ArgListEntry> ArgListTy; 1065 virtual std::pair<SDValue, SDValue> 1066 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1067 bool isVarArg, bool isInreg, unsigned CallingConv, 1068 bool isTailCall, SDValue Callee, ArgListTy &Args, 1069 SelectionDAG &DAG); 1070 1071 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1072 /// memcpy. This can be used by targets to provide code sequences for cases 1073 /// that don't fit the target's parameters for simple loads/stores and can be 1074 /// more efficient than using a library call. This function can return a null 1075 /// SDValue if the target declines to use custom code and a different 1076 /// lowering strategy should be used. 1077 /// 1078 /// If AlwaysInline is true, the size is constant and the target should not 1079 /// emit any calls and is strongly encouraged to attempt to emit inline code 1080 /// even if it is beyond the usual threshold because this intrinsic is being 1081 /// expanded in a place where calls are not feasible (e.g. within the prologue 1082 /// for another call). If the target chooses to decline an AlwaysInline 1083 /// request here, legalize will resort to using simple loads and stores. 1084 virtual SDValue 1085 EmitTargetCodeForMemcpy(SelectionDAG &DAG, 1086 SDValue Chain, 1087 SDValue Op1, SDValue Op2, 1088 SDValue Op3, unsigned Align, 1089 bool AlwaysInline, 1090 const Value *DstSV, uint64_t DstOff, 1091 const Value *SrcSV, uint64_t SrcOff) { 1092 return SDValue(); 1093 } 1094 1095 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1096 /// memmove. This can be used by targets to provide code sequences for cases 1097 /// that don't fit the target's parameters for simple loads/stores and can be 1098 /// more efficient than using a library call. This function can return a null 1099 /// SDValue if the target declines to use custom code and a different 1100 /// lowering strategy should be used. 1101 virtual SDValue 1102 EmitTargetCodeForMemmove(SelectionDAG &DAG, 1103 SDValue Chain, 1104 SDValue Op1, SDValue Op2, 1105 SDValue Op3, unsigned Align, 1106 const Value *DstSV, uint64_t DstOff, 1107 const Value *SrcSV, uint64_t SrcOff) { 1108 return SDValue(); 1109 } 1110 1111 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1112 /// memset. This can be used by targets to provide code sequences for cases 1113 /// that don't fit the target's parameters for simple stores and can be more 1114 /// efficient than using a library call. This function can return a null 1115 /// SDValue if the target declines to use custom code and a different 1116 /// lowering strategy should be used. 1117 virtual SDValue 1118 EmitTargetCodeForMemset(SelectionDAG &DAG, 1119 SDValue Chain, 1120 SDValue Op1, SDValue Op2, 1121 SDValue Op3, unsigned Align, 1122 const Value *DstSV, uint64_t DstOff) { 1123 return SDValue(); 1124 } 1125 1126 /// LowerOperation - This callback is invoked for operations that are 1127 /// unsupported by the target, which are registered to use 'custom' lowering, 1128 /// and whose defined values are all legal. 1129 /// If the target has no operations that require custom lowering, it need not 1130 /// implement this. The default implementation of this aborts. 1131 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1132 1133 /// ReplaceNodeResults - This callback is invoked for operations that are 1134 /// unsupported by the target, which are registered to use 'custom' lowering, 1135 /// and whose result type is illegal. This must return a node whose results 1136 /// precisely match the results of the input node. This typically involves a 1137 /// MERGE_VALUES node and/or BUILD_PAIR. 1138 /// 1139 /// If the target has no operations that require custom lowering, it need not 1140 /// implement this. The default implementation aborts. 1141 virtual SDNode *ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { 1142 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1143 return 0; 1144 } 1145 1146 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1147 /// tail call optimization. Targets which want to do tail call optimization 1148 /// should override this function. 1149 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call, 1150 SDValue Ret, 1151 SelectionDAG &DAG) const { 1152 return false; 1153 } 1154 1155 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly 1156 /// preceeds the RET node and whether the return uses the result of the node 1157 /// or is a void return. This function can be used by the target to determine 1158 /// eligiblity of tail call optimization. 1159 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret) { 1160 unsigned NumOps = Ret.getNumOperands(); 1161 if ((NumOps == 1 && 1162 (Ret.getOperand(0) == SDValue(TheCall,1) || 1163 Ret.getOperand(0) == SDValue(TheCall,0))) || 1164 (NumOps > 1 && 1165 Ret.getOperand(0) == SDValue(TheCall, 1166 TheCall->getNumValues()-1) && 1167 Ret.getOperand(1) == SDValue(TheCall,0))) 1168 return true; 1169 return false; 1170 } 1171 1172 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if 1173 /// it exists skip possible ISD:TokenFactor. 1174 static SDValue GetPossiblePreceedingTailCall(SDValue Chain, 1175 unsigned TailCallNodeOpCode) { 1176 if (Chain.getOpcode() == TailCallNodeOpCode) { 1177 return Chain; 1178 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1179 if (Chain.getNumOperands() && 1180 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode) 1181 return Chain.getOperand(0); 1182 } 1183 return Chain; 1184 } 1185 1186 /// getTargetNodeName() - This method returns the name of a target specific 1187 /// DAG node. 1188 virtual const char *getTargetNodeName(unsigned Opcode) const; 1189 1190 /// createFastISel - This method returns a target specific FastISel object, 1191 /// or null if the target does not support "fast" ISel. 1192 virtual FastISel * 1193 createFastISel(MachineFunction &, 1194 MachineModuleInfo *, 1195 DenseMap<const Value *, unsigned> &, 1196 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1197 DenseMap<const AllocaInst *, int> & 1198#ifndef NDEBUG 1199 , SmallSet<Instruction*, 8> &CatchInfoLost 1200#endif 1201 ) { 1202 return 0; 1203 } 1204 1205 //===--------------------------------------------------------------------===// 1206 // Inline Asm Support hooks 1207 // 1208 1209 enum ConstraintType { 1210 C_Register, // Constraint represents specific register(s). 1211 C_RegisterClass, // Constraint represents any of register(s) in class. 1212 C_Memory, // Memory constraint. 1213 C_Other, // Something else. 1214 C_Unknown // Unsupported constraint. 1215 }; 1216 1217 /// AsmOperandInfo - This contains information for each constraint that we are 1218 /// lowering. 1219 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1220 /// ConstraintCode - This contains the actual string for the code, like "m". 1221 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1222 /// most closely matches the operand. 1223 std::string ConstraintCode; 1224 1225 /// ConstraintType - Information about the constraint code, e.g. Register, 1226 /// RegisterClass, Memory, Other, Unknown. 1227 TargetLowering::ConstraintType ConstraintType; 1228 1229 /// CallOperandval - If this is the result output operand or a 1230 /// clobber, this is null, otherwise it is the incoming operand to the 1231 /// CallInst. This gets modified as the asm is processed. 1232 Value *CallOperandVal; 1233 1234 /// ConstraintVT - The ValueType for the operand value. 1235 MVT ConstraintVT; 1236 1237 /// isMatchingInputConstraint - Return true of this is an input operand that 1238 /// is a matching constraint like "4". 1239 bool isMatchingInputConstraint() const; 1240 1241 /// getMatchedOperand - If this is an input matching constraint, this method 1242 /// returns the output operand it matches. 1243 unsigned getMatchedOperand() const; 1244 1245 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1246 : InlineAsm::ConstraintInfo(info), 1247 ConstraintType(TargetLowering::C_Unknown), 1248 CallOperandVal(0), ConstraintVT(MVT::Other) { 1249 } 1250 }; 1251 1252 /// ComputeConstraintToUse - Determines the constraint code and constraint 1253 /// type to use for the specific AsmOperandInfo, setting 1254 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1255 /// being passed in is available, it can be passed in as Op, otherwise an 1256 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1257 /// constraint of the inline asm instruction being processed is 'm'. 1258 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1259 SDValue Op, 1260 bool hasMemory, 1261 SelectionDAG *DAG = 0) const; 1262 1263 /// getConstraintType - Given a constraint, return the type of constraint it 1264 /// is for this target. 1265 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1266 1267 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1268 /// return a list of registers that can be used to satisfy the constraint. 1269 /// This should only be used for C_RegisterClass constraints. 1270 virtual std::vector<unsigned> 1271 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1272 MVT VT) const; 1273 1274 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1275 /// {edx}), return the register number and the register class for the 1276 /// register. 1277 /// 1278 /// Given a register class constraint, like 'r', if this corresponds directly 1279 /// to an LLVM register class, return a register of 0 and the register class 1280 /// pointer. 1281 /// 1282 /// This should only be used for C_Register constraints. On error, 1283 /// this returns a register number of 0 and a null register class pointer.. 1284 virtual std::pair<unsigned, const TargetRegisterClass*> 1285 getRegForInlineAsmConstraint(const std::string &Constraint, 1286 MVT VT) const; 1287 1288 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1289 /// with another that has more specific requirements based on the type of the 1290 /// corresponding operand. This returns null if there is no replacement to 1291 /// make. 1292 virtual const char *LowerXConstraint(MVT ConstraintVT) const; 1293 1294 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1295 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1296 /// it means one of the asm constraint of the inline asm instruction being 1297 /// processed is 'm'. 1298 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1299 bool hasMemory, 1300 std::vector<SDValue> &Ops, 1301 SelectionDAG &DAG) const; 1302 1303 //===--------------------------------------------------------------------===// 1304 // Scheduler hooks 1305 // 1306 1307 // EmitInstrWithCustomInserter - This method should be implemented by targets 1308 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1309 // instructions are special in various ways, which require special support to 1310 // insert. The specified MachineInstr is created but not inserted into any 1311 // basic blocks, and the scheduler passes ownership of it to this method. 1312 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1313 MachineBasicBlock *MBB); 1314 1315 //===--------------------------------------------------------------------===// 1316 // Addressing mode description hooks (used by LSR etc). 1317 // 1318 1319 /// AddrMode - This represents an addressing mode of: 1320 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1321 /// If BaseGV is null, there is no BaseGV. 1322 /// If BaseOffs is zero, there is no base offset. 1323 /// If HasBaseReg is false, there is no base register. 1324 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1325 /// no scale. 1326 /// 1327 struct AddrMode { 1328 GlobalValue *BaseGV; 1329 int64_t BaseOffs; 1330 bool HasBaseReg; 1331 int64_t Scale; 1332 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1333 }; 1334 1335 /// isLegalAddressingMode - Return true if the addressing mode represented by 1336 /// AM is legal for this target, for a load/store of the specified type. 1337 /// TODO: Handle pre/postinc as well. 1338 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1339 1340 /// isTruncateFree - Return true if it's free to truncate a value of 1341 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1342 /// register EAX to i16 by referencing its sub-register AX. 1343 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1344 return false; 1345 } 1346 1347 virtual bool isTruncateFree(MVT VT1, MVT VT2) const { 1348 return false; 1349 } 1350 1351 //===--------------------------------------------------------------------===// 1352 // Div utility functions 1353 // 1354 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1355 std::vector<SDNode*>* Created) const; 1356 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1357 std::vector<SDNode*>* Created) const; 1358 1359 1360 //===--------------------------------------------------------------------===// 1361 // Runtime Library hooks 1362 // 1363 1364 /// setLibcallName - Rename the default libcall routine name for the specified 1365 /// libcall. 1366 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1367 LibcallRoutineNames[Call] = Name; 1368 } 1369 1370 /// getLibcallName - Get the libcall routine name for the specified libcall. 1371 /// 1372 const char *getLibcallName(RTLIB::Libcall Call) const { 1373 return LibcallRoutineNames[Call]; 1374 } 1375 1376 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1377 /// result of the comparison libcall against zero. 1378 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1379 CmpLibcallCCs[Call] = CC; 1380 } 1381 1382 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1383 /// the comparison libcall against zero. 1384 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1385 return CmpLibcallCCs[Call]; 1386 } 1387 1388private: 1389 TargetMachine &TM; 1390 const TargetData *TD; 1391 1392 /// PointerTy - The type to use for pointers, usually i32 or i64. 1393 /// 1394 MVT PointerTy; 1395 1396 /// IsLittleEndian - True if this is a little endian target. 1397 /// 1398 bool IsLittleEndian; 1399 1400 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1401 /// 1402 bool UsesGlobalOffsetTable; 1403 1404 /// SelectIsExpensive - Tells the code generator not to expand operations 1405 /// into sequences that use the select operations if possible. 1406 bool SelectIsExpensive; 1407 1408 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1409 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1410 /// a real cost model is in place. If we ever optimize for size, this will be 1411 /// set to true unconditionally. 1412 bool IntDivIsCheap; 1413 1414 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1415 /// srl/add/sra for a signed divide by power of two, and let the target handle 1416 /// it. 1417 bool Pow2DivIsCheap; 1418 1419 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1420 /// llvm.setjmp. Defaults to false. 1421 bool UseUnderscoreSetJmp; 1422 1423 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1424 /// llvm.longjmp. Defaults to false. 1425 bool UseUnderscoreLongJmp; 1426 1427 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1428 /// PointerTy is. 1429 MVT ShiftAmountTy; 1430 1431 OutOfRangeShiftAmount ShiftAmtHandling; 1432 1433 /// BooleanContents - Information about the contents of the high-bits in 1434 /// boolean values held in a type wider than i1. See getBooleanContents. 1435 BooleanContent BooleanContents; 1436 1437 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1438 /// total cycles or lowest register usage. 1439 SchedPreference SchedPreferenceInfo; 1440 1441 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1442 unsigned JumpBufSize; 1443 1444 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1445 /// buffers 1446 unsigned JumpBufAlignment; 1447 1448 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1449 /// if-converted. 1450 unsigned IfCvtBlockSizeLimit; 1451 1452 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1453 /// duplicated during if-conversion. 1454 unsigned IfCvtDupBlockSizeLimit; 1455 1456 /// PrefLoopAlignment - The perferred loop alignment. 1457 /// 1458 unsigned PrefLoopAlignment; 1459 1460 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1461 /// specifies the register that llvm.savestack/llvm.restorestack should save 1462 /// and restore. 1463 unsigned StackPointerRegisterToSaveRestore; 1464 1465 /// ExceptionPointerRegister - If set to a physical register, this specifies 1466 /// the register that receives the exception address on entry to a landing 1467 /// pad. 1468 unsigned ExceptionPointerRegister; 1469 1470 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1471 /// the register that receives the exception typeid on entry to a landing 1472 /// pad. 1473 unsigned ExceptionSelectorRegister; 1474 1475 /// RegClassForVT - This indicates the default register class to use for 1476 /// each ValueType the target supports natively. 1477 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1478 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1479 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1480 1481 /// TransformToType - For any value types we are promoting or expanding, this 1482 /// contains the value type that we are changing to. For Expanded types, this 1483 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1484 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1485 /// by the system, this holds the same type (e.g. i32 -> i32). 1486 MVT TransformToType[MVT::LAST_VALUETYPE]; 1487 1488 // Defines the capacity of the TargetLowering::OpActions table 1489 static const int OpActionsCapacity = 218; 1490 1491 /// OpActions - For each operation and each value type, keep a LegalizeAction 1492 /// that indicates how instruction selection should deal with the operation. 1493 /// Most operations are Legal (aka, supported natively by the target), but 1494 /// operations that are not should be described. Note that operations on 1495 /// non-legal value types are not described here. 1496 uint64_t OpActions[OpActionsCapacity]; 1497 1498 /// LoadExtActions - For each load of load extension type and each value type, 1499 /// keep a LegalizeAction that indicates how instruction selection should deal 1500 /// with the load. 1501 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1502 1503 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1504 /// indicates how instruction selection should deal with the store. 1505 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1506 1507 /// IndexedModeActions - For each indexed mode and each value type, keep a 1508 /// pair of LegalizeAction that indicates how instruction selection should 1509 /// deal with the load / store. 1510 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1511 1512 /// ConvertActions - For each conversion from source type to destination type, 1513 /// keep a LegalizeAction that indicates how instruction selection should 1514 /// deal with the conversion. 1515 /// Currently, this is used only for floating->floating conversions 1516 /// (FP_EXTEND and FP_ROUND). 1517 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1518 1519 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1520 /// LegalizeAction that indicates how instruction selection should 1521 /// deal with the condition code. 1522 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1523 1524 ValueTypeActionImpl ValueTypeActions; 1525 1526 std::vector<APFloat> LegalFPImmediates; 1527 1528 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses; 1529 1530 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1531 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1532 /// which sets a bit in this array. 1533 unsigned char 1534 TargetDAGCombineArray[OpActionsCapacity/(sizeof(unsigned char)*8)]; 1535 1536 /// PromoteToType - For operations that must be promoted to a specific type, 1537 /// this holds the destination type. This map should be sparse, so don't hold 1538 /// it as an array. 1539 /// 1540 /// Targets add entries to this map with AddPromotedToType(..), clients access 1541 /// this with getTypeToPromoteTo(..). 1542 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1543 PromoteToType; 1544 1545 /// LibcallRoutineNames - Stores the name each libcall. 1546 /// 1547 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1548 1549 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1550 /// of each of the comparison libcall against zero. 1551 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1552 1553protected: 1554 /// When lowering @llvm.memset this field specifies the maximum number of 1555 /// store operations that may be substituted for the call to memset. Targets 1556 /// must set this value based on the cost threshold for that target. Targets 1557 /// should assume that the memset will be done using as many of the largest 1558 /// store operations first, followed by smaller ones, if necessary, per 1559 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1560 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1561 /// store. This only applies to setting a constant array of a constant size. 1562 /// @brief Specify maximum number of store instructions per memset call. 1563 unsigned maxStoresPerMemset; 1564 1565 /// When lowering @llvm.memcpy this field specifies the maximum number of 1566 /// store operations that may be substituted for a call to memcpy. Targets 1567 /// must set this value based on the cost threshold for that target. Targets 1568 /// should assume that the memcpy will be done using as many of the largest 1569 /// store operations first, followed by smaller ones, if necessary, per 1570 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1571 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1572 /// and one 1-byte store. This only applies to copying a constant array of 1573 /// constant size. 1574 /// @brief Specify maximum bytes of store instructions per memcpy call. 1575 unsigned maxStoresPerMemcpy; 1576 1577 /// When lowering @llvm.memmove this field specifies the maximum number of 1578 /// store instructions that may be substituted for a call to memmove. Targets 1579 /// must set this value based on the cost threshold for that target. Targets 1580 /// should assume that the memmove will be done using as many of the largest 1581 /// store operations first, followed by smaller ones, if necessary, per 1582 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1583 /// with 8-bit alignment would result in nine 1-byte stores. This only 1584 /// applies to copying a constant array of constant size. 1585 /// @brief Specify maximum bytes of store instructions per memmove call. 1586 unsigned maxStoresPerMemmove; 1587 1588 /// This field specifies whether the target machine permits unaligned memory 1589 /// accesses. This is used, for example, to determine the size of store 1590 /// operations when copying small arrays and other similar tasks. 1591 /// @brief Indicate whether the target permits unaligned memory accesses. 1592 bool allowUnalignedMemoryAccesses; 1593}; 1594} // end llvm namespace 1595 1596#endif 1597