TargetLowering.h revision 368e18d56a87308045d341e85584597bfe7426e9
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/Type.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/CodeGen/ValueTypes.h" 28#include "llvm/Support/DataTypes.h" 29#include <vector> 30 31namespace llvm { 32 class Value; 33 class Function; 34 class TargetMachine; 35 class TargetData; 36 class TargetRegisterClass; 37 class SDNode; 38 class SDOperand; 39 class SelectionDAG; 40 class MachineBasicBlock; 41 class MachineInstr; 42 43//===----------------------------------------------------------------------===// 44/// TargetLowering - This class defines information used to lower LLVM code to 45/// legal SelectionDAG operators that the target instruction selector can accept 46/// natively. 47/// 48/// This class also defines callbacks that targets must implement to lower 49/// target-specific constructs to SelectionDAG operators. 50/// 51class TargetLowering { 52public: 53 /// LegalizeAction - This enum indicates whether operations are valid for a 54 /// target, and if not, what action should be used to make them valid. 55 enum LegalizeAction { 56 Legal, // The target natively supports this operation. 57 Promote, // This operation should be executed in a larger type. 58 Expand, // Try to expand this to other ops, otherwise use a libcall. 59 Custom, // Use the LowerOperation hook to implement custom lowering. 60 }; 61 62 enum OutOfRangeShiftAmount { 63 Undefined, // Oversized shift amounts are undefined (default). 64 Mask, // Shift amounts are auto masked (anded) to value size. 65 Extend, // Oversized shift pulls in zeros or sign bits. 66 }; 67 68 enum SetCCResultValue { 69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 71 ZeroOrNegativeOneSetCCResult, // SetCC returns a sign extended result. 72 }; 73 74 enum SchedPreference { 75 SchedulingForLatency, // Scheduling for shortest total latency. 76 SchedulingForRegPressure, // Scheduling for lowest register pressure. 77 }; 78 79 TargetLowering(TargetMachine &TM); 80 virtual ~TargetLowering(); 81 82 TargetMachine &getTargetMachine() const { return TM; } 83 const TargetData &getTargetData() const { return TD; } 84 85 bool isLittleEndian() const { return IsLittleEndian; } 86 MVT::ValueType getPointerTy() const { return PointerTy; } 87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 89 90 /// isSetCCExpensive - Return true if the setcc operation is expensive for 91 /// this target. 92 bool isSetCCExpensive() const { return SetCCIsExpensive; } 93 94 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 95 /// a sequence of several shifts, adds, and multiplies for this target. 96 bool isIntDivCheap() const { return IntDivIsCheap; } 97 98 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 99 /// srl/add/sra. 100 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 101 102 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 103 /// 104 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 105 106 /// getSetCCResultContents - For targets without boolean registers, this flag 107 /// returns information about the contents of the high-bits in the setcc 108 /// result register. 109 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 110 111 /// getSchedulingPreference - Return target scheduling preference. 112 SchedPreference getSchedulingPreference() const { 113 return SchedPreferenceInfo; 114 } 115 116 /// getRegClassFor - Return the register class that should be used for the 117 /// specified value type. This may only be called on legal types. 118 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 119 TargetRegisterClass *RC = RegClassForVT[VT]; 120 assert(RC && "This value type is not natively supported!"); 121 return RC; 122 } 123 124 /// isTypeLegal - Return true if the target has native support for the 125 /// specified value type. This means that it has a register that directly 126 /// holds it without promotions or expansions. 127 bool isTypeLegal(MVT::ValueType VT) const { 128 return RegClassForVT[VT] != 0; 129 } 130 131 class ValueTypeActionImpl { 132 /// ValueTypeActions - This is a bitvector that contains two bits for each 133 /// value type, where the two bits correspond to the LegalizeAction enum. 134 /// This can be queried with "getTypeAction(VT)". 135 uint32_t ValueTypeActions[2]; 136 public: 137 ValueTypeActionImpl() { 138 ValueTypeActions[0] = ValueTypeActions[1] = 0; 139 } 140 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 141 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 142 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 143 } 144 145 LegalizeAction getTypeAction(MVT::ValueType VT) const { 146 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 147 } 148 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 149 assert(unsigned(VT >> 4) < 150 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 151 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 152 } 153 }; 154 155 const ValueTypeActionImpl &getValueTypeActions() const { 156 return ValueTypeActions; 157 } 158 159 /// getTypeAction - Return how we should legalize values of this type, either 160 /// it is already legal (return 'Legal') or we need to promote it to a larger 161 /// type (return 'Promote'), or we need to expand it into multiple registers 162 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 163 LegalizeAction getTypeAction(MVT::ValueType VT) const { 164 return ValueTypeActions.getTypeAction(VT); 165 } 166 167 /// getTypeToTransformTo - For types supported by the target, this is an 168 /// identity function. For types that must be promoted to larger types, this 169 /// returns the larger type to promote to. For types that are larger than the 170 /// largest integer register, this contains one step in the expansion to get 171 /// to the smaller register. 172 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 173 return TransformToType[VT]; 174 } 175 176 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 177 legal_fpimm_iterator legal_fpimm_begin() const { 178 return LegalFPImmediates.begin(); 179 } 180 legal_fpimm_iterator legal_fpimm_end() const { 181 return LegalFPImmediates.end(); 182 } 183 184 /// getOperationAction - Return how this operation should be treated: either 185 /// it is legal, needs to be promoted to a larger size, needs to be 186 /// expanded to some other code sequence, or the target has a custom expander 187 /// for it. 188 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 189 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 190 } 191 192 /// isOperationLegal - Return true if the specified operation is legal on this 193 /// target. 194 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 195 return getOperationAction(Op, VT) == Legal; 196 } 197 198 /// getTypeToPromoteTo - If the action for this operation is to promote, this 199 /// method returns the ValueType to promote to. 200 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 201 assert(getOperationAction(Op, VT) == Promote && 202 "This operation isn't promoted!"); 203 MVT::ValueType NVT = VT; 204 do { 205 NVT = (MVT::ValueType)(NVT+1); 206 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 207 "Didn't find type to promote to!"); 208 } while (!isTypeLegal(NVT) || 209 getOperationAction(Op, NVT) == Promote); 210 return NVT; 211 } 212 213 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 214 /// This is fixed by the LLVM operations except for the pointer size. 215 MVT::ValueType getValueType(const Type *Ty) const { 216 switch (Ty->getTypeID()) { 217 default: assert(0 && "Unknown type!"); 218 case Type::VoidTyID: return MVT::isVoid; 219 case Type::BoolTyID: return MVT::i1; 220 case Type::UByteTyID: 221 case Type::SByteTyID: return MVT::i8; 222 case Type::ShortTyID: 223 case Type::UShortTyID: return MVT::i16; 224 case Type::IntTyID: 225 case Type::UIntTyID: return MVT::i32; 226 case Type::LongTyID: 227 case Type::ULongTyID: return MVT::i64; 228 case Type::FloatTyID: return MVT::f32; 229 case Type::DoubleTyID: return MVT::f64; 230 case Type::PointerTyID: return PointerTy; 231 case Type::PackedTyID: return MVT::Vector; 232 } 233 } 234 235 /// getNumElements - Return the number of registers that this ValueType will 236 /// eventually require. This is always one for all non-integer types, is 237 /// one for any types promoted to live in larger registers, but may be more 238 /// than one for types (like i64) that are split into pieces. 239 unsigned getNumElements(MVT::ValueType VT) const { 240 return NumElementsForVT[VT]; 241 } 242 243 /// This function returns the maximum number of store operations permitted 244 /// to replace a call to llvm.memset. The value is set by the target at the 245 /// performance threshold for such a replacement. 246 /// @brief Get maximum # of store operations permitted for llvm.memset 247 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 248 249 /// This function returns the maximum number of store operations permitted 250 /// to replace a call to llvm.memcpy. The value is set by the target at the 251 /// performance threshold for such a replacement. 252 /// @brief Get maximum # of store operations permitted for llvm.memcpy 253 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 254 255 /// This function returns the maximum number of store operations permitted 256 /// to replace a call to llvm.memmove. The value is set by the target at the 257 /// performance threshold for such a replacement. 258 /// @brief Get maximum # of store operations permitted for llvm.memmove 259 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 260 261 /// This function returns true if the target allows unaligned memory accesses. 262 /// This is used, for example, in situations where an array copy/move/set is 263 /// converted to a sequence of store operations. It's use helps to ensure that 264 /// such replacements don't generate code that causes an alignment error 265 /// (trap) on the target machine. 266 /// @brief Determine if the target supports unaligned memory accesses. 267 bool allowsUnalignedMemoryAccesses() const { 268 return allowUnalignedMemoryAccesses; 269 } 270 271 /// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp 272 /// to implement llvm.setjmp. 273 bool usesUnderscoreSetJmpLongJmp() const { 274 return UseUnderscoreSetJmpLongJmp; 275 } 276 277 /// getStackPointerRegisterToSaveRestore - If a physical register, this 278 /// specifies the register that llvm.savestack/llvm.restorestack should save 279 /// and restore. 280 unsigned getStackPointerRegisterToSaveRestore() const { 281 return StackPointerRegisterToSaveRestore; 282 } 283 284 //===--------------------------------------------------------------------===// 285 // TargetLowering Optimization Methods 286 // 287 288 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 289 /// SDOperands for returning information from TargetLowering to its clients 290 /// that want to combine 291 struct TargetLoweringOpt { 292 SelectionDAG &DAG; 293 SDOperand Old; 294 SDOperand New; 295 296 TargetLoweringOpt::TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 297 298 bool CombineTo(SDOperand O, SDOperand N) { 299 Old = O; 300 New = N; 301 return true; 302 } 303 304 /// ShrinkDemandedConstant - Check to see if the specified operand of the 305 /// specified instruction is a constant integer. If so, check to see if there 306 /// are any bits set in the constant that are not demanded. If so, shrink the 307 /// constant and return true. 308 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 309 }; 310 311 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We 312 /// use this predicate to simplify operations downstream. Op and Mask are 313 /// known to be the same type. 314 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0) 315 const; 316 317 /// ComputeMaskedBits - Determine which of the bits specified in Mask are 318 /// known to be either zero or one and return them in the KnownZero/KnownOne 319 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit 320 /// processing. Targets can implement the computeMaskedBitsForTargetNode 321 /// method, to allow target nodes to be understood. 322 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, 323 uint64_t &KnownOne, unsigned Depth = 0) const; 324 325 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 326 /// DemandedMask bits of the result of Op are ever used downstream. If we can 327 /// use this information to simplify Op, create a new simplified DAG node and 328 /// return true, returning the original and new nodes in Old and New. 329 /// Otherwise, analyze the expression and return a mask of KnownOne and 330 /// KnownZero bits for the expression (used to simplify the caller). 331 /// The KnownZero/One bits may only be accurate for those bits in the 332 /// DemandedMask. 333 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 334 uint64_t &KnownZero, uint64_t &KnownOne, 335 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 336 337 //===--------------------------------------------------------------------===// 338 // TargetLowering Configuration Methods - These methods should be invoked by 339 // the derived class constructor to configure this object for the target. 340 // 341 342protected: 343 344 /// setShiftAmountType - Describe the type that should be used for shift 345 /// amounts. This type defaults to the pointer type. 346 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 347 348 /// setSetCCResultType - Describe the type that shoudl be used as the result 349 /// of a setcc operation. This defaults to the pointer type. 350 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 351 352 /// setSetCCResultContents - Specify how the target extends the result of a 353 /// setcc operation in a register. 354 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 355 356 /// setSchedulingPreference - Specify the target scheduling preference. 357 void setSchedulingPreference(SchedPreference Pref) { 358 SchedPreferenceInfo = Pref; 359 } 360 361 /// setShiftAmountFlavor - Describe how the target handles out of range shift 362 /// amounts. 363 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 364 ShiftAmtHandling = OORSA; 365 } 366 367 /// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to 368 /// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or 369 /// the non _ versions. Defaults to false. 370 void setUseUnderscoreSetJmpLongJmp(bool Val) { 371 UseUnderscoreSetJmpLongJmp = Val; 372 } 373 374 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 375 /// specifies the register that llvm.savestack/llvm.restorestack should save 376 /// and restore. 377 void setStackPointerRegisterToSaveRestore(unsigned R) { 378 StackPointerRegisterToSaveRestore = R; 379 } 380 381 /// setSetCCIxExpensive - This is a short term hack for targets that codegen 382 /// setcc as a conditional branch. This encourages the code generator to fold 383 /// setcc operations into other operations if possible. 384 void setSetCCIsExpensive() { SetCCIsExpensive = true; } 385 386 /// setIntDivIsCheap - Tells the code generator that integer divide is 387 /// expensive, and if possible, should be replaced by an alternate sequence 388 /// of instructions not containing an integer divide. 389 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 390 391 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 392 /// srl/add/sra for a signed divide by power of two, and let the target handle 393 /// it. 394 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 395 396 /// addRegisterClass - Add the specified register class as an available 397 /// regclass for the specified value type. This indicates the selector can 398 /// handle values of that class natively. 399 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 400 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 401 RegClassForVT[VT] = RC; 402 } 403 404 /// computeRegisterProperties - Once all of the register classes are added, 405 /// this allows us to compute derived properties we expose. 406 void computeRegisterProperties(); 407 408 /// setOperationAction - Indicate that the specified operation does not work 409 /// with the specified type and indicate what to do about it. 410 void setOperationAction(unsigned Op, MVT::ValueType VT, 411 LegalizeAction Action) { 412 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 413 "Table isn't big enough!"); 414 OpActions[Op] &= ~(3ULL << VT*2); 415 OpActions[Op] |= Action << VT*2; 416 } 417 418 /// addLegalFPImmediate - Indicate that this target can instruction select 419 /// the specified FP immediate natively. 420 void addLegalFPImmediate(double Imm) { 421 LegalFPImmediates.push_back(Imm); 422 } 423 424public: 425 426 //===--------------------------------------------------------------------===// 427 // Lowering methods - These methods must be implemented by targets so that 428 // the SelectionDAGLowering code knows how to lower these. 429 // 430 431 /// LowerArguments - This hook must be implemented to indicate how we should 432 /// lower the arguments for the specified function, into the specified DAG. 433 virtual std::vector<SDOperand> 434 LowerArguments(Function &F, SelectionDAG &DAG) = 0; 435 436 /// LowerCallTo - This hook lowers an abstract call to a function into an 437 /// actual call. This returns a pair of operands. The first element is the 438 /// return value for the function (if RetTy is not VoidTy). The second 439 /// element is the outgoing token chain. 440 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy; 441 virtual std::pair<SDOperand, SDOperand> 442 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 443 unsigned CallingConv, bool isTailCall, SDOperand Callee, 444 ArgListTy &Args, SelectionDAG &DAG) = 0; 445 446 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or 447 /// llvm.frameaddress (depending on the value of the first argument). The 448 /// return values are the result pointer and the resultant token chain. If 449 /// not implemented, both of these intrinsics will return null. 450 virtual std::pair<SDOperand, SDOperand> 451 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 452 SelectionDAG &DAG); 453 454 /// LowerOperation - This callback is invoked for operations that are 455 /// unsupported by the target, which are registered to use 'custom' lowering, 456 /// and whose defined values are all legal. 457 /// If the target has no operations that require custom lowering, it need not 458 /// implement this. The default implementation of this aborts. 459 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 460 461 /// CustomPromoteOperation - This callback is invoked for operations that are 462 /// unsupported by the target, are registered to use 'custom' lowering, and 463 /// whose type needs to be promoted. 464 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 465 466 /// getTargetNodeName() - This method returns the name of a target specific 467 /// DAG node. 468 virtual const char *getTargetNodeName(unsigned Opcode) const; 469 470 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 471 /// Mask are known to be either zero or one and return them in the 472 /// KnownZero/KnownOne bitsets. 473 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 474 uint64_t Mask, 475 uint64_t &KnownZero, 476 uint64_t &KnownOne, 477 unsigned Depth = 0) const; 478 479 //===--------------------------------------------------------------------===// 480 // Inline Asm Support hooks 481 // 482 483 enum ConstraintType { 484 C_RegisterClass, // Constraint represents one or more registers. 485 C_Other, // Something else. 486 C_Unknown // Unsupported constraint. 487 // INTEGER, ADDRESS, MEMORY? 488 }; 489 490 /// getConstraintType - Given a constraint letter, return the type of 491 /// constraint it is for this target. 492 virtual ConstraintType getConstraintType(char ConstraintLetter) const; 493 494 /// getRegForInlineAsmConstraint - Given a constraint letter or register 495 /// name (e.g. "r" or "edx"), return a list of registers that can be used to 496 /// satisfy the constraint. This should only be used for physregs and 497 /// C_RegisterClass constraints. 498 virtual std::vector<unsigned> 499 getRegForInlineAsmConstraint(const std::string &Constraint) const; 500 501 /// isOperandValidForConstraint - Return true if the specified SDOperand is 502 /// valid for the specified target constraint letter. 503 virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); 504 505 //===--------------------------------------------------------------------===// 506 // Scheduler hooks 507 // 508 509 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 510 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 511 // instructions are special in various ways, which require special support to 512 // insert. The specified MachineInstr is created but not inserted into any 513 // basic blocks, and the scheduler passes ownership of it to this method. 514 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 515 MachineBasicBlock *MBB); 516 517private: 518 TargetMachine &TM; 519 const TargetData &TD; 520 521 /// IsLittleEndian - True if this is a little endian target. 522 /// 523 bool IsLittleEndian; 524 525 /// PointerTy - The type to use for pointers, usually i32 or i64. 526 /// 527 MVT::ValueType PointerTy; 528 529 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 530 /// PointerTy is. 531 MVT::ValueType ShiftAmountTy; 532 533 OutOfRangeShiftAmount ShiftAmtHandling; 534 535 /// SetCCIsExpensive - This is a short term hack for targets that codegen 536 /// setcc as a conditional branch. This encourages the code generator to fold 537 /// setcc operations into other operations if possible. 538 bool SetCCIsExpensive; 539 540 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 541 /// constants into a sequence of muls, adds, and shifts. This is a hack until 542 /// a real cost model is in place. If we ever optimize for size, this will be 543 /// set to true unconditionally. 544 bool IntDivIsCheap; 545 546 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 547 /// srl/add/sra for a signed divide by power of two, and let the target handle 548 /// it. 549 bool Pow2DivIsCheap; 550 551 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 552 /// PointerTy. 553 MVT::ValueType SetCCResultTy; 554 555 /// SetCCResultContents - Information about the contents of the high-bits in 556 /// the result of a setcc comparison operation. 557 SetCCResultValue SetCCResultContents; 558 559 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 560 /// total cycles or lowest register usage. 561 SchedPreference SchedPreferenceInfo; 562 563 /// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and 564 /// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false. 565 bool UseUnderscoreSetJmpLongJmp; 566 567 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 568 /// specifies the register that llvm.savestack/llvm.restorestack should save 569 /// and restore. 570 unsigned StackPointerRegisterToSaveRestore; 571 572 /// RegClassForVT - This indicates the default register class to use for 573 /// each ValueType the target supports natively. 574 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 575 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE]; 576 577 /// TransformToType - For any value types we are promoting or expanding, this 578 /// contains the value type that we are changing to. For Expanded types, this 579 /// contains one step of the expand (e.g. i64 -> i32), even if there are 580 /// multiple steps required (e.g. i64 -> i16). For types natively supported 581 /// by the system, this holds the same type (e.g. i32 -> i32). 582 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 583 584 /// OpActions - For each operation and each value type, keep a LegalizeAction 585 /// that indicates how instruction selection should deal with the operation. 586 /// Most operations are Legal (aka, supported natively by the target), but 587 /// operations that are not should be described. Note that operations on 588 /// non-legal value types are not described here. 589 uint64_t OpActions[128]; 590 591 ValueTypeActionImpl ValueTypeActions; 592 593 std::vector<double> LegalFPImmediates; 594 595 std::vector<std::pair<MVT::ValueType, 596 TargetRegisterClass*> > AvailableRegClasses; 597 598protected: 599 /// When lowering %llvm.memset this field specifies the maximum number of 600 /// store operations that may be substituted for the call to memset. Targets 601 /// must set this value based on the cost threshold for that target. Targets 602 /// should assume that the memset will be done using as many of the largest 603 /// store operations first, followed by smaller ones, if necessary, per 604 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 605 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 606 /// store. This only applies to setting a constant array of a constant size. 607 /// @brief Specify maximum number of store instructions per memset call. 608 unsigned maxStoresPerMemset; 609 610 /// When lowering %llvm.memcpy this field specifies the maximum number of 611 /// store operations that may be substituted for a call to memcpy. Targets 612 /// must set this value based on the cost threshold for that target. Targets 613 /// should assume that the memcpy will be done using as many of the largest 614 /// store operations first, followed by smaller ones, if necessary, per 615 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 616 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 617 /// and one 1-byte store. This only applies to copying a constant array of 618 /// constant size. 619 /// @brief Specify maximum bytes of store instructions per memcpy call. 620 unsigned maxStoresPerMemcpy; 621 622 /// When lowering %llvm.memmove this field specifies the maximum number of 623 /// store instructions that may be substituted for a call to memmove. Targets 624 /// must set this value based on the cost threshold for that target. Targets 625 /// should assume that the memmove will be done using as many of the largest 626 /// store operations first, followed by smaller ones, if necessary, per 627 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 628 /// with 8-bit alignment would result in nine 1-byte stores. This only 629 /// applies to copying a constant array of constant size. 630 /// @brief Specify maximum bytes of store instructions per memmove call. 631 unsigned maxStoresPerMemmove; 632 633 /// This field specifies whether the target machine permits unaligned memory 634 /// accesses. This is used, for example, to determine the size of store 635 /// operations when copying small arrays and other similar tasks. 636 /// @brief Indicate whether the target permits unaligned memory accesses. 637 bool allowUnalignedMemoryAccesses; 638}; 639} // end llvm namespace 640 641#endif 642