TargetLowering.h revision 3ea3c2461932d96d3defa0a9aa93ffaf631bb19d
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/CodeGen/SelectionDAGNodes.h" 28#include "llvm/CodeGen/RuntimeLibcalls.h" 29#include "llvm/ADT/APFloat.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallSet.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/STLExtras.h" 34#include "llvm/Support/DebugLoc.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class AllocaInst; 42 class CallInst; 43 class Function; 44 class FastISel; 45 class MachineBasicBlock; 46 class MachineFunction; 47 class MachineFrameInfo; 48 class MachineInstr; 49 class MachineModuleInfo; 50 class DwarfWriter; 51 class SDNode; 52 class SDValue; 53 class SelectionDAG; 54 class TargetData; 55 class TargetMachine; 56 class TargetRegisterClass; 57 class TargetSubtarget; 58 class TargetLoweringObjectFile; 59 class Value; 60 61 // FIXME: should this be here? 62 namespace TLSModel { 63 enum Model { 64 GeneralDynamic, 65 LocalDynamic, 66 InitialExec, 67 LocalExec 68 }; 69 } 70 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 71 72 73//===----------------------------------------------------------------------===// 74/// TargetLowering - This class defines information used to lower LLVM code to 75/// legal SelectionDAG operators that the target instruction selector can accept 76/// natively. 77/// 78/// This class also defines callbacks that targets must implement to lower 79/// target-specific constructs to SelectionDAG operators. 80/// 81class TargetLowering { 82 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 83 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 84public: 85 /// LegalizeAction - This enum indicates whether operations are valid for a 86 /// target, and if not, what action should be used to make them valid. 87 enum LegalizeAction { 88 Legal, // The target natively supports this operation. 89 Promote, // This operation should be executed in a larger type. 90 Expand, // Try to expand this to other ops, otherwise use a libcall. 91 Custom // Use the LowerOperation hook to implement custom lowering. 92 }; 93 94 enum BooleanContent { // How the target represents true/false values. 95 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 96 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 97 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 98 }; 99 100 enum SchedPreference { 101 SchedulingForLatency, // Scheduling for shortest total latency. 102 SchedulingForRegPressure // Scheduling for lowest register pressure. 103 }; 104 105 /// NOTE: The constructor takes ownership of TLOF. 106 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF); 107 virtual ~TargetLowering(); 108 109 TargetMachine &getTargetMachine() const { return TM; } 110 const TargetData *getTargetData() const { return TD; } 111 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 112 113 bool isBigEndian() const { return !IsLittleEndian; } 114 bool isLittleEndian() const { return IsLittleEndian; } 115 MVT getPointerTy() const { return PointerTy; } 116 MVT getShiftAmountTy() const { return ShiftAmountTy; } 117 118 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 119 /// codegen. 120 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 121 122 /// isSelectExpensive - Return true if the select operation is expensive for 123 /// this target. 124 bool isSelectExpensive() const { return SelectIsExpensive; } 125 126 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 127 /// a sequence of several shifts, adds, and multiplies for this target. 128 bool isIntDivCheap() const { return IntDivIsCheap; } 129 130 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 131 /// srl/add/sra. 132 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 133 134 /// getSetCCResultType - Return the ValueType of the result of SETCC 135 /// operations. Also used to obtain the target's preferred type for 136 /// the condition operand of SELECT and BRCOND nodes. In the case of 137 /// BRCOND the argument passed is MVT::Other since there are no other 138 /// operands to get a type hint from. 139 virtual 140 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 141 142 /// getBooleanContents - For targets without i1 registers, this gives the 143 /// nature of the high-bits of boolean values held in types wider than i1. 144 /// "Boolean values" are special true/false values produced by nodes like 145 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 146 /// Not to be confused with general values promoted from i1. 147 BooleanContent getBooleanContents() const { return BooleanContents;} 148 149 /// getSchedulingPreference - Return target scheduling preference. 150 SchedPreference getSchedulingPreference() const { 151 return SchedPreferenceInfo; 152 } 153 154 /// getRegClassFor - Return the register class that should be used for the 155 /// specified value type. This may only be called on legal types. 156 TargetRegisterClass *getRegClassFor(EVT VT) const { 157 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 158 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 159 assert(RC && "This value type is not natively supported!"); 160 return RC; 161 } 162 163 /// isTypeLegal - Return true if the target has native support for the 164 /// specified value type. This means that it has a register that directly 165 /// holds it without promotions or expansions. 166 bool isTypeLegal(EVT VT) const { 167 assert(!VT.isSimple() || 168 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 169 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 170 } 171 172 class ValueTypeActionImpl { 173 /// ValueTypeActions - This is a bitvector that contains two bits for each 174 /// value type, where the two bits correspond to the LegalizeAction enum. 175 /// This can be queried with "getTypeAction(VT)". 176 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2 177 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2]; 178 public: 179 ValueTypeActionImpl() { 180 ValueTypeActions[0] = ValueTypeActions[1] = 0; 181 ValueTypeActions[2] = ValueTypeActions[3] = 0; 182 } 183 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 184 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 185 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 186 ValueTypeActions[2] = RHS.ValueTypeActions[2]; 187 ValueTypeActions[3] = RHS.ValueTypeActions[3]; 188 } 189 190 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 191 if (VT.isExtended()) { 192 if (VT.isVector()) { 193 return VT.isPow2VectorType() ? Expand : Promote; 194 } 195 if (VT.isInteger()) 196 // First promote to a power-of-two size, then expand if necessary. 197 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote; 198 assert(0 && "Unsupported extended type!"); 199 return Legal; 200 } 201 unsigned I = VT.getSimpleVT().SimpleTy; 202 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 203 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 204 } 205 void setTypeAction(EVT VT, LegalizeAction Action) { 206 unsigned I = VT.getSimpleVT().SimpleTy; 207 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 208 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 209 } 210 }; 211 212 const ValueTypeActionImpl &getValueTypeActions() const { 213 return ValueTypeActions; 214 } 215 216 /// getTypeAction - Return how we should legalize values of this type, either 217 /// it is already legal (return 'Legal') or we need to promote it to a larger 218 /// type (return 'Promote'), or we need to expand it into multiple registers 219 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 220 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 221 return ValueTypeActions.getTypeAction(Context, VT); 222 } 223 224 /// getTypeToTransformTo - For types supported by the target, this is an 225 /// identity function. For types that must be promoted to larger types, this 226 /// returns the larger type to promote to. For integer types that are larger 227 /// than the largest integer register, this contains one step in the expansion 228 /// to get to the smaller register. For illegal floating point types, this 229 /// returns the integer type to transform to. 230 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 231 if (VT.isSimple()) { 232 assert((unsigned)VT.getSimpleVT().SimpleTy < 233 array_lengthof(TransformToType)); 234 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 235 assert(getTypeAction(Context, NVT) != Promote && 236 "Promote may not follow Expand or Promote"); 237 return NVT; 238 } 239 240 if (VT.isVector()) { 241 EVT NVT = VT.getPow2VectorType(Context); 242 if (NVT == VT) { 243 // Vector length is a power of 2 - split to half the size. 244 unsigned NumElts = VT.getVectorNumElements(); 245 EVT EltVT = VT.getVectorElementType(); 246 return (NumElts == 1) ? 247 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 248 } 249 // Promote to a power of two size, avoiding multi-step promotion. 250 return getTypeAction(Context, NVT) == Promote ? 251 getTypeToTransformTo(Context, NVT) : NVT; 252 } else if (VT.isInteger()) { 253 EVT NVT = VT.getRoundIntegerType(Context); 254 if (NVT == VT) 255 // Size is a power of two - expand to half the size. 256 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 257 else 258 // Promote to a power of two size, avoiding multi-step promotion. 259 return getTypeAction(Context, NVT) == Promote ? 260 getTypeToTransformTo(Context, NVT) : NVT; 261 } 262 assert(0 && "Unsupported extended type!"); 263 return MVT(MVT::Other); // Not reached 264 } 265 266 /// getTypeToExpandTo - For types supported by the target, this is an 267 /// identity function. For types that must be expanded (i.e. integer types 268 /// that are larger than the largest integer register or illegal floating 269 /// point types), this returns the largest legal type it will be expanded to. 270 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 271 assert(!VT.isVector()); 272 while (true) { 273 switch (getTypeAction(Context, VT)) { 274 case Legal: 275 return VT; 276 case Expand: 277 VT = getTypeToTransformTo(Context, VT); 278 break; 279 default: 280 assert(false && "Type is not legal nor is it to be expanded!"); 281 return VT; 282 } 283 } 284 return VT; 285 } 286 287 /// getVectorTypeBreakdown - Vector types are broken down into some number of 288 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 289 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 290 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 291 /// 292 /// This method returns the number of registers needed, and the VT for each 293 /// register. It also returns the VT and quantity of the intermediate values 294 /// before they are promoted/expanded. 295 /// 296 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 297 EVT &IntermediateVT, 298 unsigned &NumIntermediates, 299 EVT &RegisterVT) const; 300 301 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 302 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 303 /// this is the case, it returns true and store the intrinsic 304 /// information into the IntrinsicInfo that was passed to the function. 305 typedef struct IntrinsicInfo { 306 unsigned opc; // target opcode 307 EVT memVT; // memory VT 308 const Value* ptrVal; // value representing memory location 309 int offset; // offset off of ptrVal 310 unsigned align; // alignment 311 bool vol; // is volatile? 312 bool readMem; // reads memory? 313 bool writeMem; // writes memory? 314 } IntrinisicInfo; 315 316 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 317 CallInst &I, unsigned Intrinsic) { 318 return false; 319 } 320 321 /// getWidenVectorType: given a vector type, returns the type to widen to 322 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 323 /// If there is no vector type that we want to widen to, returns MVT::Other 324 /// When and were to widen is target dependent based on the cost of 325 /// scalarizing vs using the wider vector type. 326 virtual EVT getWidenVectorType(EVT VT) const; 327 328 /// isFPImmLegal - Returns true if the target can instruction select the 329 /// specified FP immediate natively. If false, the legalizer will materialize 330 /// the FP immediate as a load from a constant pool. 331 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const { 332 return false; 333 } 334 335 /// isShuffleMaskLegal - Targets can use this to indicate that they only 336 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 337 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 338 /// are assumed to be legal. 339 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 340 EVT VT) const { 341 return true; 342 } 343 344 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 345 /// used by Targets can use this to indicate if there is a suitable 346 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 347 /// pool entry. 348 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 349 EVT VT) const { 350 return false; 351 } 352 353 /// getOperationAction - Return how this operation should be treated: either 354 /// it is legal, needs to be promoted to a larger size, needs to be 355 /// expanded to some other code sequence, or the target has a custom expander 356 /// for it. 357 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 358 if (VT.isExtended()) return Expand; 359 assert(Op < array_lengthof(OpActions[0]) && 360 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 && 361 "Table isn't big enough!"); 362 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 363 unsigned J = I & 31; 364 I = I >> 5; 365 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3); 366 } 367 368 /// isOperationLegalOrCustom - Return true if the specified operation is 369 /// legal on this target or can be made legal with custom lowering. This 370 /// is used to help guide high-level lowering decisions. 371 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 372 return (VT == MVT::Other || isTypeLegal(VT)) && 373 (getOperationAction(Op, VT) == Legal || 374 getOperationAction(Op, VT) == Custom); 375 } 376 377 /// isOperationLegal - Return true if the specified operation is legal on this 378 /// target. 379 bool isOperationLegal(unsigned Op, EVT VT) const { 380 return (VT == MVT::Other || isTypeLegal(VT)) && 381 getOperationAction(Op, VT) == Legal; 382 } 383 384 /// getLoadExtAction - Return how this load with extension should be treated: 385 /// either it is legal, needs to be promoted to a larger size, needs to be 386 /// expanded to some other code sequence, or the target has a custom expander 387 /// for it. 388 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const { 389 assert(LType < array_lengthof(LoadExtActions) && 390 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 && 391 "Table isn't big enough!"); 392 return (LegalizeAction)((LoadExtActions[LType] >> 393 (2*VT.getSimpleVT().SimpleTy)) & 3); 394 } 395 396 /// isLoadExtLegal - Return true if the specified load with extension is legal 397 /// on this target. 398 bool isLoadExtLegal(unsigned LType, EVT VT) const { 399 return VT.isSimple() && 400 (getLoadExtAction(LType, VT) == Legal || 401 getLoadExtAction(LType, VT) == Custom); 402 } 403 404 /// getTruncStoreAction - Return how this store with truncation should be 405 /// treated: either it is legal, needs to be promoted to a larger size, needs 406 /// to be expanded to some other code sequence, or the target has a custom 407 /// expander for it. 408 LegalizeAction getTruncStoreAction(EVT ValVT, 409 EVT MemVT) const { 410 assert((unsigned)ValVT.getSimpleVT().SimpleTy < 411 array_lengthof(TruncStoreActions) && 412 (unsigned)MemVT.getSimpleVT().SimpleTy < 413 sizeof(TruncStoreActions[0])*4 && 414 "Table isn't big enough!"); 415 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >> 416 (2*MemVT.getSimpleVT().SimpleTy)) & 3); 417 } 418 419 /// isTruncStoreLegal - Return true if the specified store with truncation is 420 /// legal on this target. 421 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 422 return isTypeLegal(ValVT) && MemVT.isSimple() && 423 (getTruncStoreAction(ValVT, MemVT) == Legal || 424 getTruncStoreAction(ValVT, MemVT) == Custom); 425 } 426 427 /// getIndexedLoadAction - Return how the indexed load should be treated: 428 /// either it is legal, needs to be promoted to a larger size, needs to be 429 /// expanded to some other code sequence, or the target has a custom expander 430 /// for it. 431 LegalizeAction 432 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 433 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) && 434 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 435 "Table isn't big enough!"); 436 return (LegalizeAction)((IndexedModeActions[ 437 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode])); 438 } 439 440 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 441 /// on this target. 442 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 443 return VT.isSimple() && 444 (getIndexedLoadAction(IdxMode, VT) == Legal || 445 getIndexedLoadAction(IdxMode, VT) == Custom); 446 } 447 448 /// getIndexedStoreAction - Return how the indexed store should be treated: 449 /// either it is legal, needs to be promoted to a larger size, needs to be 450 /// expanded to some other code sequence, or the target has a custom expander 451 /// for it. 452 LegalizeAction 453 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 454 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) && 455 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 456 "Table isn't big enough!"); 457 return (LegalizeAction)((IndexedModeActions[ 458 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode])); 459 } 460 461 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 462 /// on this target. 463 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 464 return VT.isSimple() && 465 (getIndexedStoreAction(IdxMode, VT) == Legal || 466 getIndexedStoreAction(IdxMode, VT) == Custom); 467 } 468 469 /// getConvertAction - Return how the conversion should be treated: 470 /// either it is legal, needs to be promoted to a larger size, needs to be 471 /// expanded to some other code sequence, or the target has a custom expander 472 /// for it. 473 LegalizeAction 474 getConvertAction(EVT FromVT, EVT ToVT) const { 475 assert((unsigned)FromVT.getSimpleVT().SimpleTy < 476 array_lengthof(ConvertActions) && 477 (unsigned)ToVT.getSimpleVT().SimpleTy < 478 sizeof(ConvertActions[0])*4 && 479 "Table isn't big enough!"); 480 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >> 481 (2*ToVT.getSimpleVT().SimpleTy)) & 3); 482 } 483 484 /// isConvertLegal - Return true if the specified conversion is legal 485 /// on this target. 486 bool isConvertLegal(EVT FromVT, EVT ToVT) const { 487 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 488 (getConvertAction(FromVT, ToVT) == Legal || 489 getConvertAction(FromVT, ToVT) == Custom); 490 } 491 492 /// getCondCodeAction - Return how the condition code should be treated: 493 /// either it is legal, needs to be expanded to some other code sequence, 494 /// or the target has a custom expander for it. 495 LegalizeAction 496 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 497 assert((unsigned)CC < array_lengthof(CondCodeActions) && 498 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 499 "Table isn't big enough!"); 500 LegalizeAction Action = (LegalizeAction) 501 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 502 assert(Action != Promote && "Can't promote condition code!"); 503 return Action; 504 } 505 506 /// isCondCodeLegal - Return true if the specified condition code is legal 507 /// on this target. 508 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 509 return getCondCodeAction(CC, VT) == Legal || 510 getCondCodeAction(CC, VT) == Custom; 511 } 512 513 514 /// getTypeToPromoteTo - If the action for this operation is to promote, this 515 /// method returns the ValueType to promote to. 516 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 517 assert(getOperationAction(Op, VT) == Promote && 518 "This operation isn't promoted!"); 519 520 // See if this has an explicit type specified. 521 std::map<std::pair<unsigned, MVT::SimpleValueType>, 522 MVT::SimpleValueType>::const_iterator PTTI = 523 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 524 if (PTTI != PromoteToType.end()) return PTTI->second; 525 526 assert((VT.isInteger() || VT.isFloatingPoint()) && 527 "Cannot autopromote this type, add it with AddPromotedToType."); 528 529 EVT NVT = VT; 530 do { 531 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 532 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 533 "Didn't find type to promote to!"); 534 } while (!isTypeLegal(NVT) || 535 getOperationAction(Op, NVT) == Promote); 536 return NVT; 537 } 538 539 /// getValueType - Return the EVT corresponding to this LLVM type. 540 /// This is fixed by the LLVM operations except for the pointer size. If 541 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 542 /// counterpart (e.g. structs), otherwise it will assert. 543 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 544 EVT VT = EVT::getEVT(Ty, AllowUnknown); 545 return VT == MVT:: iPTR ? PointerTy : VT; 546 } 547 548 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 549 /// function arguments in the caller parameter area. This is the actual 550 /// alignment, not its logarithm. 551 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 552 553 /// getRegisterType - Return the type of registers that this ValueType will 554 /// eventually require. 555 EVT getRegisterType(MVT VT) const { 556 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 557 return RegisterTypeForVT[VT.SimpleTy]; 558 } 559 560 /// getRegisterType - Return the type of registers that this ValueType will 561 /// eventually require. 562 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 563 if (VT.isSimple()) { 564 assert((unsigned)VT.getSimpleVT().SimpleTy < 565 array_lengthof(RegisterTypeForVT)); 566 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 567 } 568 if (VT.isVector()) { 569 EVT VT1, RegisterVT; 570 unsigned NumIntermediates; 571 (void)getVectorTypeBreakdown(Context, VT, VT1, 572 NumIntermediates, RegisterVT); 573 return RegisterVT; 574 } 575 if (VT.isInteger()) { 576 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 577 } 578 assert(0 && "Unsupported extended type!"); 579 return EVT(MVT::Other); // Not reached 580 } 581 582 /// getNumRegisters - Return the number of registers that this ValueType will 583 /// eventually require. This is one for any types promoted to live in larger 584 /// registers, but may be more than one for types (like i64) that are split 585 /// into pieces. For types like i140, which are first promoted then expanded, 586 /// it is the number of registers needed to hold all the bits of the original 587 /// type. For an i140 on a 32 bit machine this means 5 registers. 588 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 589 if (VT.isSimple()) { 590 assert((unsigned)VT.getSimpleVT().SimpleTy < 591 array_lengthof(NumRegistersForVT)); 592 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 593 } 594 if (VT.isVector()) { 595 EVT VT1, VT2; 596 unsigned NumIntermediates; 597 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 598 } 599 if (VT.isInteger()) { 600 unsigned BitWidth = VT.getSizeInBits(); 601 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 602 return (BitWidth + RegWidth - 1) / RegWidth; 603 } 604 assert(0 && "Unsupported extended type!"); 605 return 0; // Not reached 606 } 607 608 /// ShouldShrinkFPConstant - If true, then instruction selection should 609 /// seek to shrink the FP constant of the specified type to a smaller type 610 /// in order to save space and / or reduce runtime. 611 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 612 613 /// hasTargetDAGCombine - If true, the target has custom DAG combine 614 /// transformations that it can perform for the specified node. 615 bool hasTargetDAGCombine(ISD::NodeType NT) const { 616 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 617 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 618 } 619 620 /// This function returns the maximum number of store operations permitted 621 /// to replace a call to llvm.memset. The value is set by the target at the 622 /// performance threshold for such a replacement. 623 /// @brief Get maximum # of store operations permitted for llvm.memset 624 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 625 626 /// This function returns the maximum number of store operations permitted 627 /// to replace a call to llvm.memcpy. The value is set by the target at the 628 /// performance threshold for such a replacement. 629 /// @brief Get maximum # of store operations permitted for llvm.memcpy 630 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 631 632 /// This function returns the maximum number of store operations permitted 633 /// to replace a call to llvm.memmove. The value is set by the target at the 634 /// performance threshold for such a replacement. 635 /// @brief Get maximum # of store operations permitted for llvm.memmove 636 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 637 638 /// This function returns true if the target allows unaligned memory accesses. 639 /// of the specified type. This is used, for example, in situations where an 640 /// array copy/move/set is converted to a sequence of store operations. It's 641 /// use helps to ensure that such replacements don't generate code that causes 642 /// an alignment error (trap) on the target machine. 643 /// @brief Determine if the target supports unaligned memory accesses. 644 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 645 return false; 646 } 647 648 /// This function returns true if the target would benefit from code placement 649 /// optimization. 650 /// @brief Determine if the target should perform code placement optimization. 651 bool shouldOptimizeCodePlacement() const { 652 return benefitFromCodePlacementOpt; 653 } 654 655 /// getOptimalMemOpType - Returns the target specific optimal type for load 656 /// and store operations as a result of memset, memcpy, and memmove lowering. 657 /// It returns EVT::iAny if SelectionDAG should be responsible for 658 /// determining it. 659 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, 660 bool isSrcConst, bool isSrcStr, 661 SelectionDAG &DAG) const { 662 return MVT::iAny; 663 } 664 665 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 666 /// to implement llvm.setjmp. 667 bool usesUnderscoreSetJmp() const { 668 return UseUnderscoreSetJmp; 669 } 670 671 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 672 /// to implement llvm.longjmp. 673 bool usesUnderscoreLongJmp() const { 674 return UseUnderscoreLongJmp; 675 } 676 677 /// getStackPointerRegisterToSaveRestore - If a physical register, this 678 /// specifies the register that llvm.savestack/llvm.restorestack should save 679 /// and restore. 680 unsigned getStackPointerRegisterToSaveRestore() const { 681 return StackPointerRegisterToSaveRestore; 682 } 683 684 /// getExceptionAddressRegister - If a physical register, this returns 685 /// the register that receives the exception address on entry to a landing 686 /// pad. 687 unsigned getExceptionAddressRegister() const { 688 return ExceptionPointerRegister; 689 } 690 691 /// getExceptionSelectorRegister - If a physical register, this returns 692 /// the register that receives the exception typeid on entry to a landing 693 /// pad. 694 unsigned getExceptionSelectorRegister() const { 695 return ExceptionSelectorRegister; 696 } 697 698 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 699 /// set, the default is 200) 700 unsigned getJumpBufSize() const { 701 return JumpBufSize; 702 } 703 704 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 705 /// (if never set, the default is 0) 706 unsigned getJumpBufAlignment() const { 707 return JumpBufAlignment; 708 } 709 710 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 711 /// limit. Any block whose size is greater should not be predicated. 712 unsigned getIfCvtBlockSizeLimit() const { 713 return IfCvtBlockSizeLimit; 714 } 715 716 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 717 /// block to be considered for duplication. Any block whose size is greater 718 /// should not be duplicated to facilitate its predication. 719 unsigned getIfCvtDupBlockSizeLimit() const { 720 return IfCvtDupBlockSizeLimit; 721 } 722 723 /// getPrefLoopAlignment - return the preferred loop alignment. 724 /// 725 unsigned getPrefLoopAlignment() const { 726 return PrefLoopAlignment; 727 } 728 729 /// getPreIndexedAddressParts - returns true by value, base pointer and 730 /// offset pointer and addressing mode by reference if the node's address 731 /// can be legally represented as pre-indexed load / store address. 732 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 733 SDValue &Offset, 734 ISD::MemIndexedMode &AM, 735 SelectionDAG &DAG) const { 736 return false; 737 } 738 739 /// getPostIndexedAddressParts - returns true by value, base pointer and 740 /// offset pointer and addressing mode by reference if this node can be 741 /// combined with a load / store to form a post-indexed load / store. 742 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 743 SDValue &Base, SDValue &Offset, 744 ISD::MemIndexedMode &AM, 745 SelectionDAG &DAG) const { 746 return false; 747 } 748 749 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 750 /// jumptable. 751 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 752 SelectionDAG &DAG) const; 753 754 /// isOffsetFoldingLegal - Return true if folding a constant offset 755 /// with the given GlobalAddress is legal. It is frequently not legal in 756 /// PIC relocation models. 757 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 758 759 /// getFunctionAlignment - Return the Log2 alignment of this function. 760 virtual unsigned getFunctionAlignment(const Function *) const = 0; 761 762 //===--------------------------------------------------------------------===// 763 // TargetLowering Optimization Methods 764 // 765 766 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 767 /// SDValues for returning information from TargetLowering to its clients 768 /// that want to combine 769 struct TargetLoweringOpt { 770 SelectionDAG &DAG; 771 SDValue Old; 772 SDValue New; 773 774 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 775 776 bool CombineTo(SDValue O, SDValue N) { 777 Old = O; 778 New = N; 779 return true; 780 } 781 782 /// ShrinkDemandedConstant - Check to see if the specified operand of the 783 /// specified instruction is a constant integer. If so, check to see if 784 /// there are any bits set in the constant that are not demanded. If so, 785 /// shrink the constant and return true. 786 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 787 788 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 789 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 790 /// cast, but it could be generalized for targets with other types of 791 /// implicit widening casts. 792 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 793 DebugLoc dl); 794 }; 795 796 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 797 /// DemandedMask bits of the result of Op are ever used downstream. If we can 798 /// use this information to simplify Op, create a new simplified DAG node and 799 /// return true, returning the original and new nodes in Old and New. 800 /// Otherwise, analyze the expression and return a mask of KnownOne and 801 /// KnownZero bits for the expression (used to simplify the caller). 802 /// The KnownZero/One bits may only be accurate for those bits in the 803 /// DemandedMask. 804 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 805 APInt &KnownZero, APInt &KnownOne, 806 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 807 808 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 809 /// Mask are known to be either zero or one and return them in the 810 /// KnownZero/KnownOne bitsets. 811 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 812 const APInt &Mask, 813 APInt &KnownZero, 814 APInt &KnownOne, 815 const SelectionDAG &DAG, 816 unsigned Depth = 0) const; 817 818 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 819 /// targets that want to expose additional information about sign bits to the 820 /// DAG Combiner. 821 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 822 unsigned Depth = 0) const; 823 824 struct DAGCombinerInfo { 825 void *DC; // The DAG Combiner object. 826 bool BeforeLegalize; 827 bool BeforeLegalizeOps; 828 bool CalledByLegalizer; 829 public: 830 SelectionDAG &DAG; 831 832 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 833 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 834 CalledByLegalizer(cl), DAG(dag) {} 835 836 bool isBeforeLegalize() const { return BeforeLegalize; } 837 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 838 bool isCalledByLegalizer() const { return CalledByLegalizer; } 839 840 void AddToWorklist(SDNode *N); 841 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 842 bool AddTo = true); 843 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 844 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 845 846 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 847 }; 848 849 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 850 /// and cc. If it is unable to simplify it, return a null SDValue. 851 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 852 ISD::CondCode Cond, bool foldBooleans, 853 DAGCombinerInfo &DCI, DebugLoc dl) const; 854 855 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 856 /// node is a GlobalAddress + offset. 857 virtual bool 858 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 859 860 /// PerformDAGCombine - This method will be invoked for all target nodes and 861 /// for any target-independent nodes that the target has registered with 862 /// invoke it for. 863 /// 864 /// The semantics are as follows: 865 /// Return Value: 866 /// SDValue.Val == 0 - No change was made 867 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 868 /// otherwise - N should be replaced by the returned Operand. 869 /// 870 /// In addition, methods provided by DAGCombinerInfo may be used to perform 871 /// more complex transformations. 872 /// 873 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 874 875 //===--------------------------------------------------------------------===// 876 // TargetLowering Configuration Methods - These methods should be invoked by 877 // the derived class constructor to configure this object for the target. 878 // 879 880protected: 881 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 882 /// GOT for PC-relative code. 883 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 884 885 /// setShiftAmountType - Describe the type that should be used for shift 886 /// amounts. This type defaults to the pointer type. 887 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 888 889 /// setBooleanContents - Specify how the target extends the result of a 890 /// boolean value from i1 to a wider type. See getBooleanContents. 891 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 892 893 /// setSchedulingPreference - Specify the target scheduling preference. 894 void setSchedulingPreference(SchedPreference Pref) { 895 SchedPreferenceInfo = Pref; 896 } 897 898 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 899 /// use _setjmp to implement llvm.setjmp or the non _ version. 900 /// Defaults to false. 901 void setUseUnderscoreSetJmp(bool Val) { 902 UseUnderscoreSetJmp = Val; 903 } 904 905 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 906 /// use _longjmp to implement llvm.longjmp or the non _ version. 907 /// Defaults to false. 908 void setUseUnderscoreLongJmp(bool Val) { 909 UseUnderscoreLongJmp = Val; 910 } 911 912 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 913 /// specifies the register that llvm.savestack/llvm.restorestack should save 914 /// and restore. 915 void setStackPointerRegisterToSaveRestore(unsigned R) { 916 StackPointerRegisterToSaveRestore = R; 917 } 918 919 /// setExceptionPointerRegister - If set to a physical register, this sets 920 /// the register that receives the exception address on entry to a landing 921 /// pad. 922 void setExceptionPointerRegister(unsigned R) { 923 ExceptionPointerRegister = R; 924 } 925 926 /// setExceptionSelectorRegister - If set to a physical register, this sets 927 /// the register that receives the exception typeid on entry to a landing 928 /// pad. 929 void setExceptionSelectorRegister(unsigned R) { 930 ExceptionSelectorRegister = R; 931 } 932 933 /// SelectIsExpensive - Tells the code generator not to expand operations 934 /// into sequences that use the select operations if possible. 935 void setSelectIsExpensive() { SelectIsExpensive = true; } 936 937 /// setIntDivIsCheap - Tells the code generator that integer divide is 938 /// expensive, and if possible, should be replaced by an alternate sequence 939 /// of instructions not containing an integer divide. 940 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 941 942 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 943 /// srl/add/sra for a signed divide by power of two, and let the target handle 944 /// it. 945 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 946 947 /// addRegisterClass - Add the specified register class as an available 948 /// regclass for the specified value type. This indicates the selector can 949 /// handle values of that class natively. 950 void addRegisterClass(EVT VT, TargetRegisterClass *RC) { 951 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 952 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 953 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 954 } 955 956 /// computeRegisterProperties - Once all of the register classes are added, 957 /// this allows us to compute derived properties we expose. 958 void computeRegisterProperties(); 959 960 /// setOperationAction - Indicate that the specified operation does not work 961 /// with the specified type and indicate what to do about it. 962 void setOperationAction(unsigned Op, MVT VT, 963 LegalizeAction Action) { 964 unsigned I = (unsigned)VT.SimpleTy; 965 unsigned J = I & 31; 966 I = I >> 5; 967 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2)); 968 OpActions[I][Op] |= (uint64_t)Action << (J*2); 969 } 970 971 /// setLoadExtAction - Indicate that the specified load with extension does 972 /// not work with the with specified type and indicate what to do about it. 973 void setLoadExtAction(unsigned ExtType, MVT VT, 974 LegalizeAction Action) { 975 assert((unsigned)VT.SimpleTy*2 < 63 && 976 ExtType < array_lengthof(LoadExtActions) && 977 "Table isn't big enough!"); 978 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 979 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2; 980 } 981 982 /// setTruncStoreAction - Indicate that the specified truncating store does 983 /// not work with the with specified type and indicate what to do about it. 984 void setTruncStoreAction(MVT ValVT, MVT MemVT, 985 LegalizeAction Action) { 986 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) && 987 (unsigned)MemVT.SimpleTy*2 < 63 && 988 "Table isn't big enough!"); 989 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2); 990 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2; 991 } 992 993 /// setIndexedLoadAction - Indicate that the specified indexed load does or 994 /// does not work with the with specified type and indicate what to do abort 995 /// it. NOTE: All indexed mode loads are initialized to Expand in 996 /// TargetLowering.cpp 997 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 998 LegalizeAction Action) { 999 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1000 IdxMode < array_lengthof(IndexedModeActions[0][0]) && 1001 "Table isn't big enough!"); 1002 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action; 1003 } 1004 1005 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1006 /// does not work with the with specified type and indicate what to do about 1007 /// it. NOTE: All indexed mode stores are initialized to Expand in 1008 /// TargetLowering.cpp 1009 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1010 LegalizeAction Action) { 1011 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1012 IdxMode < array_lengthof(IndexedModeActions[0][1] ) && 1013 "Table isn't big enough!"); 1014 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action; 1015 } 1016 1017 /// setConvertAction - Indicate that the specified conversion does or does 1018 /// not work with the with specified type and indicate what to do about it. 1019 void setConvertAction(MVT FromVT, MVT ToVT, 1020 LegalizeAction Action) { 1021 assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) && 1022 (unsigned)ToVT.SimpleTy < MVT::LAST_VALUETYPE && 1023 "Table isn't big enough!"); 1024 ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2); 1025 ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2; 1026 } 1027 1028 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1029 /// supported on the target and indicate what to do about it. 1030 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1031 LegalizeAction Action) { 1032 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1033 (unsigned)CC < array_lengthof(CondCodeActions) && 1034 "Table isn't big enough!"); 1035 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1036 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1037 } 1038 1039 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1040 /// promotion code defaults to trying a larger integer/fp until it can find 1041 /// one that works. If that default is insufficient, this method can be used 1042 /// by the target to override the default. 1043 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1044 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1045 } 1046 1047 /// setTargetDAGCombine - Targets should invoke this method for each target 1048 /// independent node that they want to provide a custom DAG combiner for by 1049 /// implementing the PerformDAGCombine virtual method. 1050 void setTargetDAGCombine(ISD::NodeType NT) { 1051 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1052 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1053 } 1054 1055 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1056 /// bytes); default is 200 1057 void setJumpBufSize(unsigned Size) { 1058 JumpBufSize = Size; 1059 } 1060 1061 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1062 /// alignment (in bytes); default is 0 1063 void setJumpBufAlignment(unsigned Align) { 1064 JumpBufAlignment = Align; 1065 } 1066 1067 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1068 /// limit (in number of instructions); default is 2. 1069 void setIfCvtBlockSizeLimit(unsigned Limit) { 1070 IfCvtBlockSizeLimit = Limit; 1071 } 1072 1073 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1074 /// of instructions) to be considered for code duplication during 1075 /// if-conversion; default is 2. 1076 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1077 IfCvtDupBlockSizeLimit = Limit; 1078 } 1079 1080 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1081 /// alignment is zero, it means the target does not care about loop alignment. 1082 void setPrefLoopAlignment(unsigned Align) { 1083 PrefLoopAlignment = Align; 1084 } 1085 1086public: 1087 1088 virtual const TargetSubtarget *getSubtarget() { 1089 assert(0 && "Not Implemented"); 1090 return NULL; // this is here to silence compiler errors 1091 } 1092 1093 //===--------------------------------------------------------------------===// 1094 // Lowering methods - These methods must be implemented by targets so that 1095 // the SelectionDAGLowering code knows how to lower these. 1096 // 1097 1098 /// LowerFormalArguments - This hook must be implemented to lower the 1099 /// incoming (formal) arguments, described by the Ins array, into the 1100 /// specified DAG. The implementation should fill in the InVals array 1101 /// with legal-type argument values, and return the resulting token 1102 /// chain value. 1103 /// 1104 virtual SDValue 1105 LowerFormalArguments(SDValue Chain, 1106 CallingConv::ID CallConv, bool isVarArg, 1107 const SmallVectorImpl<ISD::InputArg> &Ins, 1108 DebugLoc dl, SelectionDAG &DAG, 1109 SmallVectorImpl<SDValue> &InVals) { 1110 assert(0 && "Not Implemented"); 1111 return SDValue(); // this is here to silence compiler errors 1112 } 1113 1114 /// LowerCallTo - This function lowers an abstract call to a function into an 1115 /// actual call. This returns a pair of operands. The first element is the 1116 /// return value for the function (if RetTy is not VoidTy). The second 1117 /// element is the outgoing token chain. It calls LowerCall to do the actual 1118 /// lowering. 1119 struct ArgListEntry { 1120 SDValue Node; 1121 const Type* Ty; 1122 bool isSExt : 1; 1123 bool isZExt : 1; 1124 bool isInReg : 1; 1125 bool isSRet : 1; 1126 bool isNest : 1; 1127 bool isByVal : 1; 1128 uint16_t Alignment; 1129 1130 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1131 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1132 }; 1133 typedef std::vector<ArgListEntry> ArgListTy; 1134 std::pair<SDValue, SDValue> 1135 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1136 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1137 CallingConv::ID CallConv, bool isTailCall, 1138 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1139 SelectionDAG &DAG, DebugLoc dl, unsigned Order); 1140 1141 /// LowerCall - This hook must be implemented to lower calls into the 1142 /// the specified DAG. The outgoing arguments to the call are described 1143 /// by the Outs array, and the values to be returned by the call are 1144 /// described by the Ins array. The implementation should fill in the 1145 /// InVals array with legal-type return values from the call, and return 1146 /// the resulting token chain value. 1147 /// 1148 /// The isTailCall flag here is normative. If it is true, the 1149 /// implementation must emit a tail call. The 1150 /// IsEligibleForTailCallOptimization hook should be used to catch 1151 /// cases that cannot be handled. 1152 /// 1153 virtual SDValue 1154 LowerCall(SDValue Chain, SDValue Callee, 1155 CallingConv::ID CallConv, bool isVarArg, bool isTailCall, 1156 const SmallVectorImpl<ISD::OutputArg> &Outs, 1157 const SmallVectorImpl<ISD::InputArg> &Ins, 1158 DebugLoc dl, SelectionDAG &DAG, 1159 SmallVectorImpl<SDValue> &InVals) { 1160 assert(0 && "Not Implemented"); 1161 return SDValue(); // this is here to silence compiler errors 1162 } 1163 1164 /// CanLowerReturn - This hook should be implemented to check whether the 1165 /// return values described by the Outs array can fit into the return 1166 /// registers. If false is returned, an sret-demotion is performed. 1167 /// 1168 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1169 const SmallVectorImpl<EVT> &OutTys, 1170 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1171 SelectionDAG &DAG) 1172 { 1173 // Return true by default to get preexisting behavior. 1174 return true; 1175 } 1176 /// LowerReturn - This hook must be implemented to lower outgoing 1177 /// return values, described by the Outs array, into the specified 1178 /// DAG. The implementation should return the resulting token chain 1179 /// value. 1180 /// 1181 virtual SDValue 1182 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1183 const SmallVectorImpl<ISD::OutputArg> &Outs, 1184 DebugLoc dl, SelectionDAG &DAG) { 1185 assert(0 && "Not Implemented"); 1186 return SDValue(); // this is here to silence compiler errors 1187 } 1188 1189 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1190 /// memcpy. This can be used by targets to provide code sequences for cases 1191 /// that don't fit the target's parameters for simple loads/stores and can be 1192 /// more efficient than using a library call. This function can return a null 1193 /// SDValue if the target declines to use custom code and a different 1194 /// lowering strategy should be used. 1195 /// 1196 /// If AlwaysInline is true, the size is constant and the target should not 1197 /// emit any calls and is strongly encouraged to attempt to emit inline code 1198 /// even if it is beyond the usual threshold because this intrinsic is being 1199 /// expanded in a place where calls are not feasible (e.g. within the prologue 1200 /// for another call). If the target chooses to decline an AlwaysInline 1201 /// request here, legalize will resort to using simple loads and stores. 1202 virtual SDValue 1203 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1204 SDValue Chain, 1205 SDValue Op1, SDValue Op2, 1206 SDValue Op3, unsigned Align, 1207 bool AlwaysInline, 1208 const Value *DstSV, uint64_t DstOff, 1209 const Value *SrcSV, uint64_t SrcOff) { 1210 return SDValue(); 1211 } 1212 1213 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1214 /// memmove. This can be used by targets to provide code sequences for cases 1215 /// that don't fit the target's parameters for simple loads/stores and can be 1216 /// more efficient than using a library call. This function can return a null 1217 /// SDValue if the target declines to use custom code and a different 1218 /// lowering strategy should be used. 1219 virtual SDValue 1220 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, 1221 SDValue Chain, 1222 SDValue Op1, SDValue Op2, 1223 SDValue Op3, unsigned Align, 1224 const Value *DstSV, uint64_t DstOff, 1225 const Value *SrcSV, uint64_t SrcOff) { 1226 return SDValue(); 1227 } 1228 1229 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1230 /// memset. This can be used by targets to provide code sequences for cases 1231 /// that don't fit the target's parameters for simple stores and can be more 1232 /// efficient than using a library call. This function can return a null 1233 /// SDValue if the target declines to use custom code and a different 1234 /// lowering strategy should be used. 1235 virtual SDValue 1236 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 1237 SDValue Chain, 1238 SDValue Op1, SDValue Op2, 1239 SDValue Op3, unsigned Align, 1240 const Value *DstSV, uint64_t DstOff) { 1241 return SDValue(); 1242 } 1243 1244 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1245 /// to legalize nodes with an illegal operand type but legal result types. 1246 /// It replaces the LowerOperation callback in the type Legalizer. 1247 /// The reason we can not do away with LowerOperation entirely is that 1248 /// LegalizeDAG isn't yet ready to use this callback. 1249 /// TODO: Consider merging with ReplaceNodeResults. 1250 1251 /// The target places new result values for the node in Results (their number 1252 /// and types must exactly match those of the original return values of 1253 /// the node), or leaves Results empty, which indicates that the node is not 1254 /// to be custom lowered after all. 1255 /// The default implementation calls LowerOperation. 1256 virtual void LowerOperationWrapper(SDNode *N, 1257 SmallVectorImpl<SDValue> &Results, 1258 SelectionDAG &DAG); 1259 1260 /// LowerOperation - This callback is invoked for operations that are 1261 /// unsupported by the target, which are registered to use 'custom' lowering, 1262 /// and whose defined values are all legal. 1263 /// If the target has no operations that require custom lowering, it need not 1264 /// implement this. The default implementation of this aborts. 1265 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1266 1267 /// ReplaceNodeResults - This callback is invoked when a node result type is 1268 /// illegal for the target, and the operation was registered to use 'custom' 1269 /// lowering for that result type. The target places new result values for 1270 /// the node in Results (their number and types must exactly match those of 1271 /// the original return values of the node), or leaves Results empty, which 1272 /// indicates that the node is not to be custom lowered after all. 1273 /// 1274 /// If the target has no operations that require custom lowering, it need not 1275 /// implement this. The default implementation aborts. 1276 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1277 SelectionDAG &DAG) { 1278 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1279 } 1280 1281 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1282 /// tail call optimization. Targets which want to do tail call optimization 1283 /// should override this function. 1284 virtual bool 1285 IsEligibleForTailCallOptimization(SDValue Callee, 1286 CallingConv::ID CalleeCC, 1287 bool isVarArg, 1288 const SmallVectorImpl<ISD::InputArg> &Ins, 1289 SelectionDAG& DAG) const { 1290 // Conservative default: no calls are eligible. 1291 return false; 1292 } 1293 1294 /// getTargetNodeName() - This method returns the name of a target specific 1295 /// DAG node. 1296 virtual const char *getTargetNodeName(unsigned Opcode) const; 1297 1298 /// createFastISel - This method returns a target specific FastISel object, 1299 /// or null if the target does not support "fast" ISel. 1300 virtual FastISel * 1301 createFastISel(MachineFunction &, 1302 MachineModuleInfo *, DwarfWriter *, 1303 DenseMap<const Value *, unsigned> &, 1304 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1305 DenseMap<const AllocaInst *, int> & 1306#ifndef NDEBUG 1307 , SmallSet<Instruction*, 8> &CatchInfoLost 1308#endif 1309 ) { 1310 return 0; 1311 } 1312 1313 //===--------------------------------------------------------------------===// 1314 // Inline Asm Support hooks 1315 // 1316 1317 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1318 /// call to be explicit llvm code if it wants to. This is useful for 1319 /// turning simple inline asms into LLVM intrinsics, which gives the 1320 /// compiler more information about the behavior of the code. 1321 virtual bool ExpandInlineAsm(CallInst *CI) const { 1322 return false; 1323 } 1324 1325 enum ConstraintType { 1326 C_Register, // Constraint represents specific register(s). 1327 C_RegisterClass, // Constraint represents any of register(s) in class. 1328 C_Memory, // Memory constraint. 1329 C_Other, // Something else. 1330 C_Unknown // Unsupported constraint. 1331 }; 1332 1333 /// AsmOperandInfo - This contains information for each constraint that we are 1334 /// lowering. 1335 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1336 /// ConstraintCode - This contains the actual string for the code, like "m". 1337 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1338 /// most closely matches the operand. 1339 std::string ConstraintCode; 1340 1341 /// ConstraintType - Information about the constraint code, e.g. Register, 1342 /// RegisterClass, Memory, Other, Unknown. 1343 TargetLowering::ConstraintType ConstraintType; 1344 1345 /// CallOperandval - If this is the result output operand or a 1346 /// clobber, this is null, otherwise it is the incoming operand to the 1347 /// CallInst. This gets modified as the asm is processed. 1348 Value *CallOperandVal; 1349 1350 /// ConstraintVT - The ValueType for the operand value. 1351 EVT ConstraintVT; 1352 1353 /// isMatchingInputConstraint - Return true of this is an input operand that 1354 /// is a matching constraint like "4". 1355 bool isMatchingInputConstraint() const; 1356 1357 /// getMatchedOperand - If this is an input matching constraint, this method 1358 /// returns the output operand it matches. 1359 unsigned getMatchedOperand() const; 1360 1361 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1362 : InlineAsm::ConstraintInfo(info), 1363 ConstraintType(TargetLowering::C_Unknown), 1364 CallOperandVal(0), ConstraintVT(MVT::Other) { 1365 } 1366 }; 1367 1368 /// ComputeConstraintToUse - Determines the constraint code and constraint 1369 /// type to use for the specific AsmOperandInfo, setting 1370 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1371 /// being passed in is available, it can be passed in as Op, otherwise an 1372 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1373 /// constraint of the inline asm instruction being processed is 'm'. 1374 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1375 SDValue Op, 1376 bool hasMemory, 1377 SelectionDAG *DAG = 0) const; 1378 1379 /// getConstraintType - Given a constraint, return the type of constraint it 1380 /// is for this target. 1381 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1382 1383 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1384 /// return a list of registers that can be used to satisfy the constraint. 1385 /// This should only be used for C_RegisterClass constraints. 1386 virtual std::vector<unsigned> 1387 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1388 EVT VT) const; 1389 1390 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1391 /// {edx}), return the register number and the register class for the 1392 /// register. 1393 /// 1394 /// Given a register class constraint, like 'r', if this corresponds directly 1395 /// to an LLVM register class, return a register of 0 and the register class 1396 /// pointer. 1397 /// 1398 /// This should only be used for C_Register constraints. On error, 1399 /// this returns a register number of 0 and a null register class pointer.. 1400 virtual std::pair<unsigned, const TargetRegisterClass*> 1401 getRegForInlineAsmConstraint(const std::string &Constraint, 1402 EVT VT) const; 1403 1404 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1405 /// with another that has more specific requirements based on the type of the 1406 /// corresponding operand. This returns null if there is no replacement to 1407 /// make. 1408 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1409 1410 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1411 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1412 /// it means one of the asm constraint of the inline asm instruction being 1413 /// processed is 'm'. 1414 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1415 bool hasMemory, 1416 std::vector<SDValue> &Ops, 1417 SelectionDAG &DAG) const; 1418 1419 //===--------------------------------------------------------------------===// 1420 // Instruction Emitting Hooks 1421 // 1422 1423 // EmitInstrWithCustomInserter - This method should be implemented by targets 1424 // that mark instructions with the 'usesCustomInserter' flag. These 1425 // instructions are special in various ways, which require special support to 1426 // insert. The specified MachineInstr is created but not inserted into any 1427 // basic blocks, and this method is called to expand it into a sequence of 1428 // instructions, potentially also creating new basic blocks and control flow. 1429 // When new basic blocks are inserted and the edges from MBB to its successors 1430 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the 1431 // DenseMap. 1432 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1433 MachineBasicBlock *MBB, 1434 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 1435 1436 //===--------------------------------------------------------------------===// 1437 // Addressing mode description hooks (used by LSR etc). 1438 // 1439 1440 /// AddrMode - This represents an addressing mode of: 1441 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1442 /// If BaseGV is null, there is no BaseGV. 1443 /// If BaseOffs is zero, there is no base offset. 1444 /// If HasBaseReg is false, there is no base register. 1445 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1446 /// no scale. 1447 /// 1448 struct AddrMode { 1449 GlobalValue *BaseGV; 1450 int64_t BaseOffs; 1451 bool HasBaseReg; 1452 int64_t Scale; 1453 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1454 }; 1455 1456 /// isLegalAddressingMode - Return true if the addressing mode represented by 1457 /// AM is legal for this target, for a load/store of the specified type. 1458 /// The type may be VoidTy, in which case only return true if the addressing 1459 /// mode is legal for a load/store of any legal type. 1460 /// TODO: Handle pre/postinc as well. 1461 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1462 1463 /// isTruncateFree - Return true if it's free to truncate a value of 1464 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1465 /// register EAX to i16 by referencing its sub-register AX. 1466 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1467 return false; 1468 } 1469 1470 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1471 return false; 1472 } 1473 1474 /// isZExtFree - Return true if any actual instruction that defines a 1475 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 1476 /// register. This does not necessarily include registers defined in 1477 /// unknown ways, such as incoming arguments, or copies from unknown 1478 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1479 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1480 /// all instructions that define 32-bit values implicit zero-extend the 1481 /// result out to 64 bits. 1482 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1483 return false; 1484 } 1485 1486 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1487 return false; 1488 } 1489 1490 /// isNarrowingProfitable - Return true if it's profitable to narrow 1491 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1492 /// from i32 to i8 but not from i32 to i16. 1493 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1494 return false; 1495 } 1496 1497 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1498 /// icmp immediate, that is the target has icmp instructions which can compare 1499 /// a register against the immediate without having to materialize the 1500 /// immediate into a register. 1501 virtual bool isLegalICmpImmediate(int64_t Imm) const { 1502 return true; 1503 } 1504 1505 //===--------------------------------------------------------------------===// 1506 // Div utility functions 1507 // 1508 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1509 std::vector<SDNode*>* Created) const; 1510 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1511 std::vector<SDNode*>* Created) const; 1512 1513 1514 //===--------------------------------------------------------------------===// 1515 // Runtime Library hooks 1516 // 1517 1518 /// setLibcallName - Rename the default libcall routine name for the specified 1519 /// libcall. 1520 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1521 LibcallRoutineNames[Call] = Name; 1522 } 1523 1524 /// getLibcallName - Get the libcall routine name for the specified libcall. 1525 /// 1526 const char *getLibcallName(RTLIB::Libcall Call) const { 1527 return LibcallRoutineNames[Call]; 1528 } 1529 1530 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1531 /// result of the comparison libcall against zero. 1532 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1533 CmpLibcallCCs[Call] = CC; 1534 } 1535 1536 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1537 /// the comparison libcall against zero. 1538 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1539 return CmpLibcallCCs[Call]; 1540 } 1541 1542 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1543 /// specified libcall. 1544 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1545 LibcallCallingConvs[Call] = CC; 1546 } 1547 1548 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1549 /// specified libcall. 1550 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1551 return LibcallCallingConvs[Call]; 1552 } 1553 1554private: 1555 TargetMachine &TM; 1556 const TargetData *TD; 1557 TargetLoweringObjectFile &TLOF; 1558 1559 /// PointerTy - The type to use for pointers, usually i32 or i64. 1560 /// 1561 MVT PointerTy; 1562 1563 /// IsLittleEndian - True if this is a little endian target. 1564 /// 1565 bool IsLittleEndian; 1566 1567 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1568 /// 1569 bool UsesGlobalOffsetTable; 1570 1571 /// SelectIsExpensive - Tells the code generator not to expand operations 1572 /// into sequences that use the select operations if possible. 1573 bool SelectIsExpensive; 1574 1575 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1576 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1577 /// a real cost model is in place. If we ever optimize for size, this will be 1578 /// set to true unconditionally. 1579 bool IntDivIsCheap; 1580 1581 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1582 /// srl/add/sra for a signed divide by power of two, and let the target handle 1583 /// it. 1584 bool Pow2DivIsCheap; 1585 1586 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1587 /// llvm.setjmp. Defaults to false. 1588 bool UseUnderscoreSetJmp; 1589 1590 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1591 /// llvm.longjmp. Defaults to false. 1592 bool UseUnderscoreLongJmp; 1593 1594 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1595 /// PointerTy is. 1596 MVT ShiftAmountTy; 1597 1598 /// BooleanContents - Information about the contents of the high-bits in 1599 /// boolean values held in a type wider than i1. See getBooleanContents. 1600 BooleanContent BooleanContents; 1601 1602 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1603 /// total cycles or lowest register usage. 1604 SchedPreference SchedPreferenceInfo; 1605 1606 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1607 unsigned JumpBufSize; 1608 1609 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1610 /// buffers 1611 unsigned JumpBufAlignment; 1612 1613 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1614 /// if-converted. 1615 unsigned IfCvtBlockSizeLimit; 1616 1617 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1618 /// duplicated during if-conversion. 1619 unsigned IfCvtDupBlockSizeLimit; 1620 1621 /// PrefLoopAlignment - The perferred loop alignment. 1622 /// 1623 unsigned PrefLoopAlignment; 1624 1625 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1626 /// specifies the register that llvm.savestack/llvm.restorestack should save 1627 /// and restore. 1628 unsigned StackPointerRegisterToSaveRestore; 1629 1630 /// ExceptionPointerRegister - If set to a physical register, this specifies 1631 /// the register that receives the exception address on entry to a landing 1632 /// pad. 1633 unsigned ExceptionPointerRegister; 1634 1635 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1636 /// the register that receives the exception typeid on entry to a landing 1637 /// pad. 1638 unsigned ExceptionSelectorRegister; 1639 1640 /// RegClassForVT - This indicates the default register class to use for 1641 /// each ValueType the target supports natively. 1642 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1643 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1644 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1645 1646 /// TransformToType - For any value types we are promoting or expanding, this 1647 /// contains the value type that we are changing to. For Expanded types, this 1648 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1649 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1650 /// by the system, this holds the same type (e.g. i32 -> i32). 1651 EVT TransformToType[MVT::LAST_VALUETYPE]; 1652 1653 /// OpActions - For each operation and each value type, keep a LegalizeAction 1654 /// that indicates how instruction selection should deal with the operation. 1655 /// Most operations are Legal (aka, supported natively by the target), but 1656 /// operations that are not should be described. Note that operations on 1657 /// non-legal value types are not described here. 1658 /// This array is accessed using VT.getSimpleVT(), so it is subject to 1659 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits. 1660 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END]; 1661 1662 /// LoadExtActions - For each load of load extension type and each value type, 1663 /// keep a LegalizeAction that indicates how instruction selection should deal 1664 /// with the load. 1665 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1666 1667 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1668 /// indicates how instruction selection should deal with the store. 1669 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1670 1671 /// IndexedModeActions - For each indexed mode and each value type, 1672 /// keep a pair of LegalizeAction that indicates how instruction 1673 /// selection should deal with the load / store. The first 1674 /// dimension is now the value_type for the reference. The second 1675 /// dimension is the load [0] vs. store[1]. The third dimension 1676 /// represents the various modes for load store. 1677 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE]; 1678 1679 /// ConvertActions - For each conversion from source type to destination type, 1680 /// keep a LegalizeAction that indicates how instruction selection should 1681 /// deal with the conversion. 1682 /// Currently, this is used only for floating->floating conversions 1683 /// (FP_EXTEND and FP_ROUND). 1684 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1685 1686 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1687 /// LegalizeAction that indicates how instruction selection should 1688 /// deal with the condition code. 1689 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1690 1691 ValueTypeActionImpl ValueTypeActions; 1692 1693 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1694 1695 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1696 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1697 /// which sets a bit in this array. 1698 unsigned char 1699 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1700 1701 /// PromoteToType - For operations that must be promoted to a specific type, 1702 /// this holds the destination type. This map should be sparse, so don't hold 1703 /// it as an array. 1704 /// 1705 /// Targets add entries to this map with AddPromotedToType(..), clients access 1706 /// this with getTypeToPromoteTo(..). 1707 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1708 PromoteToType; 1709 1710 /// LibcallRoutineNames - Stores the name each libcall. 1711 /// 1712 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1713 1714 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1715 /// of each of the comparison libcall against zero. 1716 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1717 1718 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1719 /// libcall. 1720 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1721 1722protected: 1723 /// When lowering \@llvm.memset this field specifies the maximum number of 1724 /// store operations that may be substituted for the call to memset. Targets 1725 /// must set this value based on the cost threshold for that target. Targets 1726 /// should assume that the memset will be done using as many of the largest 1727 /// store operations first, followed by smaller ones, if necessary, per 1728 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1729 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1730 /// store. This only applies to setting a constant array of a constant size. 1731 /// @brief Specify maximum number of store instructions per memset call. 1732 unsigned maxStoresPerMemset; 1733 1734 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1735 /// store operations that may be substituted for a call to memcpy. Targets 1736 /// must set this value based on the cost threshold for that target. Targets 1737 /// should assume that the memcpy will be done using as many of the largest 1738 /// store operations first, followed by smaller ones, if necessary, per 1739 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1740 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1741 /// and one 1-byte store. This only applies to copying a constant array of 1742 /// constant size. 1743 /// @brief Specify maximum bytes of store instructions per memcpy call. 1744 unsigned maxStoresPerMemcpy; 1745 1746 /// When lowering \@llvm.memmove this field specifies the maximum number of 1747 /// store instructions that may be substituted for a call to memmove. Targets 1748 /// must set this value based on the cost threshold for that target. Targets 1749 /// should assume that the memmove will be done using as many of the largest 1750 /// store operations first, followed by smaller ones, if necessary, per 1751 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1752 /// with 8-bit alignment would result in nine 1-byte stores. This only 1753 /// applies to copying a constant array of constant size. 1754 /// @brief Specify maximum bytes of store instructions per memmove call. 1755 unsigned maxStoresPerMemmove; 1756 1757 /// This field specifies whether the target can benefit from code placement 1758 /// optimization. 1759 bool benefitFromCodePlacementOpt; 1760}; 1761} // end llvm namespace 1762 1763#endif 1764