TargetLowering.h revision 456ca048af35163b9f52187e92a23ee0a9f059e8
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/ADT/DenseMap.h" 26#include "llvm/CodeGen/DAGCombine.h" 27#include "llvm/CodeGen/RuntimeLibcalls.h" 28#include "llvm/CodeGen/SelectionDAGNodes.h" 29#include "llvm/IR/Attributes.h" 30#include "llvm/IR/CallingConv.h" 31#include "llvm/IR/InlineAsm.h" 32#include "llvm/Support/CallSite.h" 33#include "llvm/Support/DebugLoc.h" 34#include "llvm/Target/TargetCallingConv.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class CallInst; 42 class CCState; 43 class FastISel; 44 class FunctionLoweringInfo; 45 class ImmutableCallSite; 46 class IntrinsicInst; 47 class MachineBasicBlock; 48 class MachineFunction; 49 class MachineInstr; 50 class MachineJumpTableInfo; 51 class MCContext; 52 class MCExpr; 53 template<typename T> class SmallVectorImpl; 54 class DataLayout; 55 class TargetRegisterClass; 56 class TargetLibraryInfo; 57 class TargetLoweringObjectFile; 58 class Value; 59 60 namespace Sched { 61 enum Preference { 62 None, // No preference 63 Source, // Follow source order. 64 RegPressure, // Scheduling for lowest register pressure. 65 Hybrid, // Scheduling for both latency and register pressure. 66 ILP, // Scheduling for ILP in low register pressure mode. 67 VLIW // Scheduling for VLIW targets. 68 }; 69 } 70 71/// TargetLoweringBase - This base class for TargetLowering contains the 72/// SelectionDAG-independent parts that can be used from the rest of CodeGen. 73class TargetLoweringBase { 74 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 75 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 76 77public: 78 /// LegalizeAction - This enum indicates whether operations are valid for a 79 /// target, and if not, what action should be used to make them valid. 80 enum LegalizeAction { 81 Legal, // The target natively supports this operation. 82 Promote, // This operation should be executed in a larger type. 83 Expand, // Try to expand this to other ops, otherwise use a libcall. 84 Custom // Use the LowerOperation hook to implement custom lowering. 85 }; 86 87 /// LegalizeTypeAction - This enum indicates whether a types are legal for a 88 /// target, and if not, what action should be used to make them valid. 89 enum LegalizeTypeAction { 90 TypeLegal, // The target natively supports this type. 91 TypePromoteInteger, // Replace this integer with a larger one. 92 TypeExpandInteger, // Split this integer into two of half the size. 93 TypeSoftenFloat, // Convert this float to a same size integer type. 94 TypeExpandFloat, // Split this float into two of half the size. 95 TypeScalarizeVector, // Replace this one-element vector with its element. 96 TypeSplitVector, // Split this vector into two of half the size. 97 TypeWidenVector // This vector should be widened into a larger vector. 98 }; 99 100 /// LegalizeKind holds the legalization kind that needs to happen to EVT 101 /// in order to type-legalize it. 102 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; 103 104 enum BooleanContent { // How the target represents true/false values. 105 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 106 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 107 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 108 }; 109 110 enum SelectSupportKind { 111 ScalarValSelect, // The target supports scalar selects (ex: cmov). 112 ScalarCondVectorVal, // The target supports selects with a scalar condition 113 // and vector values (ex: cmov). 114 VectorMaskSelect // The target supports vector selects with a vector 115 // mask (ex: x86 blends). 116 }; 117 118 static ISD::NodeType getExtendForContent(BooleanContent Content) { 119 switch (Content) { 120 case UndefinedBooleanContent: 121 // Extend by adding rubbish bits. 122 return ISD::ANY_EXTEND; 123 case ZeroOrOneBooleanContent: 124 // Extend by adding zero bits. 125 return ISD::ZERO_EXTEND; 126 case ZeroOrNegativeOneBooleanContent: 127 // Extend by copying the sign bit. 128 return ISD::SIGN_EXTEND; 129 } 130 llvm_unreachable("Invalid content kind"); 131 } 132 133 /// NOTE: The constructor takes ownership of TLOF. 134 explicit TargetLoweringBase(const TargetMachine &TM, 135 const TargetLoweringObjectFile *TLOF); 136 virtual ~TargetLoweringBase(); 137 138protected: 139 /// \brief Initialize all of the actions to default values. 140 void initActions(); 141 142public: 143 const TargetMachine &getTargetMachine() const { return TM; } 144 const DataLayout *getDataLayout() const { return TD; } 145 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 146 147 bool isBigEndian() const { return !IsLittleEndian; } 148 bool isLittleEndian() const { return IsLittleEndian; } 149 // Return the pointer type for the given address space, defaults to 150 // the pointer type from the data layout. 151 // FIXME: The default needs to be removed once all the code is updated. 152 virtual MVT getPointerTy(uint32_t AS = 0) const { return PointerTy; } 153 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const; 154 155 EVT getShiftAmountTy(EVT LHSTy) const; 156 157 /// isSelectExpensive - Return true if the select operation is expensive for 158 /// this target. 159 bool isSelectExpensive() const { return SelectIsExpensive; } 160 161 virtual bool isSelectSupported(SelectSupportKind kind) const { return true; } 162 163 /// shouldSplitVectorElementType - Return true if a vector of the given type 164 /// should be split (TypeSplitVector) instead of promoted 165 /// (TypePromoteInteger) during type legalization. 166 virtual bool shouldSplitVectorElementType(EVT VT) const { return false; } 167 168 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 169 /// a sequence of several shifts, adds, and multiplies for this target. 170 bool isIntDivCheap() const { return IntDivIsCheap; } 171 172 /// isSlowDivBypassed - Returns true if target has indicated at least one 173 /// type should be bypassed. 174 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); } 175 176 /// getBypassSlowDivTypes - Returns map of slow types for division or 177 /// remainder with corresponding fast types 178 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const { 179 return BypassSlowDivWidths; 180 } 181 182 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 183 /// srl/add/sra. 184 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 185 186 /// isJumpExpensive() - Return true if Flow Control is an expensive operation 187 /// that should be avoided. 188 bool isJumpExpensive() const { return JumpIsExpensive; } 189 190 /// isPredictableSelectExpensive - Return true if selects are only cheaper 191 /// than branches if the branch is unlikely to be predicted right. 192 bool isPredictableSelectExpensive() const { 193 return PredictableSelectIsExpensive; 194 } 195 196 /// getSetCCResultType - Return the ValueType of the result of SETCC 197 /// operations. Also used to obtain the target's preferred type for 198 /// the condition operand of SELECT and BRCOND nodes. In the case of 199 /// BRCOND the argument passed is MVT::Other since there are no other 200 /// operands to get a type hint from. 201 virtual EVT getSetCCResultType(EVT VT) const; 202 203 /// getCmpLibcallReturnType - Return the ValueType for comparison 204 /// libcalls. Comparions libcalls include floating point comparion calls, 205 /// and Ordered/Unordered check calls on floating point numbers. 206 virtual 207 MVT::SimpleValueType getCmpLibcallReturnType() const; 208 209 /// getBooleanContents - For targets without i1 registers, this gives the 210 /// nature of the high-bits of boolean values held in types wider than i1. 211 /// "Boolean values" are special true/false values produced by nodes like 212 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 213 /// Not to be confused with general values promoted from i1. 214 /// Some cpus distinguish between vectors of boolean and scalars; the isVec 215 /// parameter selects between the two kinds. For example on X86 a scalar 216 /// boolean should be zero extended from i1, while the elements of a vector 217 /// of booleans should be sign extended from i1. 218 BooleanContent getBooleanContents(bool isVec) const { 219 return isVec ? BooleanVectorContents : BooleanContents; 220 } 221 222 /// getSchedulingPreference - Return target scheduling preference. 223 Sched::Preference getSchedulingPreference() const { 224 return SchedPreferenceInfo; 225 } 226 227 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 228 /// different scheduling heuristics for different nodes. This function returns 229 /// the preference (or none) for the given node. 230 virtual Sched::Preference getSchedulingPreference(SDNode *) const { 231 return Sched::None; 232 } 233 234 /// getRegClassFor - Return the register class that should be used for the 235 /// specified value type. 236 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { 237 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 238 assert(RC && "This value type is not natively supported!"); 239 return RC; 240 } 241 242 /// getRepRegClassFor - Return the 'representative' register class for the 243 /// specified value type. The 'representative' register class is the largest 244 /// legal super-reg register class for the register class of the value type. 245 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 246 /// while the rep register class is GR64 on x86_64. 247 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { 248 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; 249 return RC; 250 } 251 252 /// getRepRegClassCostFor - Return the cost of the 'representative' register 253 /// class for the specified value type. 254 virtual uint8_t getRepRegClassCostFor(MVT VT) const { 255 return RepRegClassCostForVT[VT.SimpleTy]; 256 } 257 258 /// isTypeLegal - Return true if the target has native support for the 259 /// specified value type. This means that it has a register that directly 260 /// holds it without promotions or expansions. 261 bool isTypeLegal(EVT VT) const { 262 assert(!VT.isSimple() || 263 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 264 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 265 } 266 267 class ValueTypeActionImpl { 268 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum 269 /// that indicates how instruction selection should deal with the type. 270 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 271 272 public: 273 ValueTypeActionImpl() { 274 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 275 } 276 277 LegalizeTypeAction getTypeAction(MVT VT) const { 278 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; 279 } 280 281 void setTypeAction(MVT VT, LegalizeTypeAction Action) { 282 unsigned I = VT.SimpleTy; 283 ValueTypeActions[I] = Action; 284 } 285 }; 286 287 const ValueTypeActionImpl &getValueTypeActions() const { 288 return ValueTypeActions; 289 } 290 291 /// getTypeAction - Return how we should legalize values of this type, either 292 /// it is already legal (return 'Legal') or we need to promote it to a larger 293 /// type (return 'Promote'), or we need to expand it into multiple registers 294 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 295 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { 296 return getTypeConversion(Context, VT).first; 297 } 298 LegalizeTypeAction getTypeAction(MVT VT) const { 299 return ValueTypeActions.getTypeAction(VT); 300 } 301 302 /// getTypeToTransformTo - For types supported by the target, this is an 303 /// identity function. For types that must be promoted to larger types, this 304 /// returns the larger type to promote to. For integer types that are larger 305 /// than the largest integer register, this contains one step in the expansion 306 /// to get to the smaller register. For illegal floating point types, this 307 /// returns the integer type to transform to. 308 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 309 return getTypeConversion(Context, VT).second; 310 } 311 312 /// getTypeToExpandTo - For types supported by the target, this is an 313 /// identity function. For types that must be expanded (i.e. integer types 314 /// that are larger than the largest integer register or illegal floating 315 /// point types), this returns the largest legal type it will be expanded to. 316 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 317 assert(!VT.isVector()); 318 while (true) { 319 switch (getTypeAction(Context, VT)) { 320 case TypeLegal: 321 return VT; 322 case TypeExpandInteger: 323 VT = getTypeToTransformTo(Context, VT); 324 break; 325 default: 326 llvm_unreachable("Type is not legal nor is it to be expanded!"); 327 } 328 } 329 } 330 331 /// getVectorTypeBreakdown - Vector types are broken down into some number of 332 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 333 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 334 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 335 /// 336 /// This method returns the number of registers needed, and the VT for each 337 /// register. It also returns the VT and quantity of the intermediate values 338 /// before they are promoted/expanded. 339 /// 340 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 341 EVT &IntermediateVT, 342 unsigned &NumIntermediates, 343 MVT &RegisterVT) const; 344 345 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 346 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 347 /// this is the case, it returns true and store the intrinsic 348 /// information into the IntrinsicInfo that was passed to the function. 349 struct IntrinsicInfo { 350 unsigned opc; // target opcode 351 EVT memVT; // memory VT 352 const Value* ptrVal; // value representing memory location 353 int offset; // offset off of ptrVal 354 unsigned align; // alignment 355 bool vol; // is volatile? 356 bool readMem; // reads memory? 357 bool writeMem; // writes memory? 358 }; 359 360 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 361 unsigned /*Intrinsic*/) const { 362 return false; 363 } 364 365 /// isFPImmLegal - Returns true if the target can instruction select the 366 /// specified FP immediate natively. If false, the legalizer will materialize 367 /// the FP immediate as a load from a constant pool. 368 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const { 369 return false; 370 } 371 372 /// isShuffleMaskLegal - Targets can use this to indicate that they only 373 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 374 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 375 /// are assumed to be legal. 376 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 377 EVT /*VT*/) const { 378 return true; 379 } 380 381 /// canOpTrap - Returns true if the operation can trap for the value type. 382 /// VT must be a legal type. By default, we optimistically assume most 383 /// operations don't trap except for divide and remainder. 384 virtual bool canOpTrap(unsigned Op, EVT VT) const; 385 386 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 387 /// used by Targets can use this to indicate if there is a suitable 388 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 389 /// pool entry. 390 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 391 EVT /*VT*/) const { 392 return false; 393 } 394 395 /// getOperationAction - Return how this operation should be treated: either 396 /// it is legal, needs to be promoted to a larger size, needs to be 397 /// expanded to some other code sequence, or the target has a custom expander 398 /// for it. 399 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 400 if (VT.isExtended()) return Expand; 401 // If a target-specific SDNode requires legalization, require the target 402 // to provide custom legalization for it. 403 if (Op > array_lengthof(OpActions[0])) return Custom; 404 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 405 return (LegalizeAction)OpActions[I][Op]; 406 } 407 408 /// isOperationLegalOrCustom - Return true if the specified operation is 409 /// legal on this target or can be made legal with custom lowering. This 410 /// is used to help guide high-level lowering decisions. 411 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 412 return (VT == MVT::Other || isTypeLegal(VT)) && 413 (getOperationAction(Op, VT) == Legal || 414 getOperationAction(Op, VT) == Custom); 415 } 416 417 /// isOperationLegalOrPromote - Return true if the specified operation is 418 /// legal on this target or can be made legal using promotion. This 419 /// is used to help guide high-level lowering decisions. 420 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const { 421 return (VT == MVT::Other || isTypeLegal(VT)) && 422 (getOperationAction(Op, VT) == Legal || 423 getOperationAction(Op, VT) == Promote); 424 } 425 426 /// isOperationExpand - Return true if the specified operation is illegal on 427 /// this target or unlikely to be made legal with custom lowering. This is 428 /// used to help guide high-level lowering decisions. 429 bool isOperationExpand(unsigned Op, EVT VT) const { 430 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); 431 } 432 433 /// isOperationLegal - Return true if the specified operation is legal on this 434 /// target. 435 bool isOperationLegal(unsigned Op, EVT VT) const { 436 return (VT == MVT::Other || isTypeLegal(VT)) && 437 getOperationAction(Op, VT) == Legal; 438 } 439 440 /// getLoadExtAction - Return how this load with extension should be treated: 441 /// either it is legal, needs to be promoted to a larger size, needs to be 442 /// expanded to some other code sequence, or the target has a custom expander 443 /// for it. 444 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const { 445 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 446 "Table isn't big enough!"); 447 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType]; 448 } 449 450 /// isLoadExtLegal - Return true if the specified load with extension is legal 451 /// on this target. 452 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 453 return VT.isSimple() && 454 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal; 455 } 456 457 /// getTruncStoreAction - Return how this store with truncation should be 458 /// treated: either it is legal, needs to be promoted to a larger size, needs 459 /// to be expanded to some other code sequence, or the target has a custom 460 /// expander for it. 461 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const { 462 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 463 "Table isn't big enough!"); 464 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy] 465 [MemVT.SimpleTy]; 466 } 467 468 /// isTruncStoreLegal - Return true if the specified store with truncation is 469 /// legal on this target. 470 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 471 return isTypeLegal(ValVT) && MemVT.isSimple() && 472 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal; 473 } 474 475 /// getIndexedLoadAction - Return how the indexed load should be treated: 476 /// either it is legal, needs to be promoted to a larger size, needs to be 477 /// expanded to some other code sequence, or the target has a custom expander 478 /// for it. 479 LegalizeAction 480 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 481 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 482 "Table isn't big enough!"); 483 unsigned Ty = (unsigned)VT.SimpleTy; 484 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 485 } 486 487 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 488 /// on this target. 489 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 490 return VT.isSimple() && 491 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || 492 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); 493 } 494 495 /// getIndexedStoreAction - Return how the indexed store should be treated: 496 /// either it is legal, needs to be promoted to a larger size, needs to be 497 /// expanded to some other code sequence, or the target has a custom expander 498 /// for it. 499 LegalizeAction 500 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 501 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 502 "Table isn't big enough!"); 503 unsigned Ty = (unsigned)VT.SimpleTy; 504 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 505 } 506 507 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 508 /// on this target. 509 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 510 return VT.isSimple() && 511 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || 512 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); 513 } 514 515 /// getCondCodeAction - Return how the condition code should be treated: 516 /// either it is legal, needs to be expanded to some other code sequence, 517 /// or the target has a custom expander for it. 518 LegalizeAction 519 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 520 assert((unsigned)CC < array_lengthof(CondCodeActions) && 521 (unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 && 522 "Table isn't big enough!"); 523 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 524 /// value and the upper 27 bits index into the second dimension of the 525 /// array to select what 64bit value to use. 526 LegalizeAction Action = (LegalizeAction) 527 ((CondCodeActions[CC][VT.SimpleTy >> 5] >> (2*(VT.SimpleTy & 0x1F))) & 3); 528 assert(Action != Promote && "Can't promote condition code!"); 529 return Action; 530 } 531 532 /// isCondCodeLegal - Return true if the specified condition code is legal 533 /// on this target. 534 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 535 return 536 getCondCodeAction(CC, VT) == Legal || 537 getCondCodeAction(CC, VT) == Custom; 538 } 539 540 541 /// getTypeToPromoteTo - If the action for this operation is to promote, this 542 /// method returns the ValueType to promote to. 543 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 544 assert(getOperationAction(Op, VT) == Promote && 545 "This operation isn't promoted!"); 546 547 // See if this has an explicit type specified. 548 std::map<std::pair<unsigned, MVT::SimpleValueType>, 549 MVT::SimpleValueType>::const_iterator PTTI = 550 PromoteToType.find(std::make_pair(Op, VT.SimpleTy)); 551 if (PTTI != PromoteToType.end()) return PTTI->second; 552 553 assert((VT.isInteger() || VT.isFloatingPoint()) && 554 "Cannot autopromote this type, add it with AddPromotedToType."); 555 556 MVT NVT = VT; 557 do { 558 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1); 559 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 560 "Didn't find type to promote to!"); 561 } while (!isTypeLegal(NVT) || 562 getOperationAction(Op, NVT) == Promote); 563 return NVT; 564 } 565 566 /// getValueType - Return the EVT corresponding to this LLVM type. 567 /// This is fixed by the LLVM operations except for the pointer size. If 568 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 569 /// counterpart (e.g. structs), otherwise it will assert. 570 EVT getValueType(Type *Ty, bool AllowUnknown = false) const { 571 // Lower scalar pointers to native pointer types. 572 if (Ty->isPointerTy()) return PointerTy; 573 574 if (Ty->isVectorTy()) { 575 VectorType *VTy = cast<VectorType>(Ty); 576 Type *Elm = VTy->getElementType(); 577 // Lower vectors of pointers to native pointer types. 578 if (Elm->isPointerTy()) 579 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext()); 580 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), 581 VTy->getNumElements()); 582 } 583 return EVT::getEVT(Ty, AllowUnknown); 584 } 585 586 /// Return the MVT corresponding to this LLVM type. See getValueType. 587 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const { 588 return getValueType(Ty, AllowUnknown).getSimpleVT(); 589 } 590 591 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 592 /// function arguments in the caller parameter area. This is the actual 593 /// alignment, not its logarithm. 594 virtual unsigned getByValTypeAlignment(Type *Ty) const; 595 596 /// getRegisterType - Return the type of registers that this ValueType will 597 /// eventually require. 598 MVT getRegisterType(MVT VT) const { 599 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 600 return RegisterTypeForVT[VT.SimpleTy]; 601 } 602 603 /// getRegisterType - Return the type of registers that this ValueType will 604 /// eventually require. 605 MVT getRegisterType(LLVMContext &Context, EVT VT) const { 606 if (VT.isSimple()) { 607 assert((unsigned)VT.getSimpleVT().SimpleTy < 608 array_lengthof(RegisterTypeForVT)); 609 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 610 } 611 if (VT.isVector()) { 612 EVT VT1; 613 MVT RegisterVT; 614 unsigned NumIntermediates; 615 (void)getVectorTypeBreakdown(Context, VT, VT1, 616 NumIntermediates, RegisterVT); 617 return RegisterVT; 618 } 619 if (VT.isInteger()) { 620 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 621 } 622 llvm_unreachable("Unsupported extended type!"); 623 } 624 625 /// getNumRegisters - Return the number of registers that this ValueType will 626 /// eventually require. This is one for any types promoted to live in larger 627 /// registers, but may be more than one for types (like i64) that are split 628 /// into pieces. For types like i140, which are first promoted then expanded, 629 /// it is the number of registers needed to hold all the bits of the original 630 /// type. For an i140 on a 32 bit machine this means 5 registers. 631 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 632 if (VT.isSimple()) { 633 assert((unsigned)VT.getSimpleVT().SimpleTy < 634 array_lengthof(NumRegistersForVT)); 635 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 636 } 637 if (VT.isVector()) { 638 EVT VT1; 639 MVT VT2; 640 unsigned NumIntermediates; 641 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 642 } 643 if (VT.isInteger()) { 644 unsigned BitWidth = VT.getSizeInBits(); 645 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 646 return (BitWidth + RegWidth - 1) / RegWidth; 647 } 648 llvm_unreachable("Unsupported extended type!"); 649 } 650 651 /// ShouldShrinkFPConstant - If true, then instruction selection should 652 /// seek to shrink the FP constant of the specified type to a smaller type 653 /// in order to save space and / or reduce runtime. 654 virtual bool ShouldShrinkFPConstant(EVT) const { return true; } 655 656 /// hasTargetDAGCombine - If true, the target has custom DAG combine 657 /// transformations that it can perform for the specified node. 658 bool hasTargetDAGCombine(ISD::NodeType NT) const { 659 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 660 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 661 } 662 663 /// This function returns the maximum number of store operations permitted 664 /// to replace a call to llvm.memset. The value is set by the target at the 665 /// performance threshold for such a replacement. If OptSize is true, 666 /// return the limit for functions that have OptSize attribute. 667 /// @brief Get maximum # of store operations permitted for llvm.memset 668 unsigned getMaxStoresPerMemset(bool OptSize) const { 669 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset; 670 } 671 672 /// This function returns the maximum number of store operations permitted 673 /// to replace a call to llvm.memcpy. The value is set by the target at the 674 /// performance threshold for such a replacement. If OptSize is true, 675 /// return the limit for functions that have OptSize attribute. 676 /// @brief Get maximum # of store operations permitted for llvm.memcpy 677 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 678 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy; 679 } 680 681 /// This function returns the maximum number of store operations permitted 682 /// to replace a call to llvm.memmove. The value is set by the target at the 683 /// performance threshold for such a replacement. If OptSize is true, 684 /// return the limit for functions that have OptSize attribute. 685 /// @brief Get maximum # of store operations permitted for llvm.memmove 686 unsigned getMaxStoresPerMemmove(bool OptSize) const { 687 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove; 688 } 689 690 /// This function returns true if the target allows unaligned memory accesses. 691 /// of the specified type. If true, it also returns whether the unaligned 692 /// memory access is "fast" in the second argument by reference. This is used, 693 /// for example, in situations where an array copy/move/set is converted to a 694 /// sequence of store operations. It's use helps to ensure that such 695 /// replacements don't generate code that causes an alignment error (trap) on 696 /// the target machine. 697 /// @brief Determine if the target supports unaligned memory accesses. 698 virtual bool allowsUnalignedMemoryAccesses(EVT, bool *Fast = 0) const { 699 return false; 700 } 701 702 /// getOptimalMemOpType - Returns the target specific optimal type for load 703 /// and store operations as a result of memset, memcpy, and memmove 704 /// lowering. If DstAlign is zero that means it's safe to destination 705 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 706 /// means there isn't a need to check it against alignment requirement, 707 /// probably because the source does not need to be loaded. If 'IsMemset' is 708 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 709 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 710 /// source is constant so it does not need to be loaded. 711 /// It returns EVT::Other if the type should be determined using generic 712 /// target-independent logic. 713 virtual EVT getOptimalMemOpType(uint64_t /*Size*/, 714 unsigned /*DstAlign*/, unsigned /*SrcAlign*/, 715 bool /*IsMemset*/, 716 bool /*ZeroMemset*/, 717 bool /*MemcpyStrSrc*/, 718 MachineFunction &/*MF*/) const { 719 return MVT::Other; 720 } 721 722 /// isSafeMemOpType - Returns true if it's safe to use load / store of the 723 /// specified type to expand memcpy / memset inline. This is mostly true 724 /// for all types except for some special cases. For example, on X86 725 /// targets without SSE2 f64 load / store are done with fldl / fstpl which 726 /// also does type conversion. Note the specified type doesn't have to be 727 /// legal as the hook is used before type legalization. 728 virtual bool isSafeMemOpType(MVT VT) const { 729 return true; 730 } 731 732 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 733 /// to implement llvm.setjmp. 734 bool usesUnderscoreSetJmp() const { 735 return UseUnderscoreSetJmp; 736 } 737 738 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 739 /// to implement llvm.longjmp. 740 bool usesUnderscoreLongJmp() const { 741 return UseUnderscoreLongJmp; 742 } 743 744 /// supportJumpTables - return whether the target can generate code for 745 /// jump tables. 746 bool supportJumpTables() const { 747 return SupportJumpTables; 748 } 749 750 /// getMinimumJumpTableEntries - return integer threshold on number of 751 /// blocks to use jump tables rather than if sequence. 752 int getMinimumJumpTableEntries() const { 753 return MinimumJumpTableEntries; 754 } 755 756 /// getStackPointerRegisterToSaveRestore - If a physical register, this 757 /// specifies the register that llvm.savestack/llvm.restorestack should save 758 /// and restore. 759 unsigned getStackPointerRegisterToSaveRestore() const { 760 return StackPointerRegisterToSaveRestore; 761 } 762 763 /// getExceptionPointerRegister - If a physical register, this returns 764 /// the register that receives the exception address on entry to a landing 765 /// pad. 766 unsigned getExceptionPointerRegister() const { 767 return ExceptionPointerRegister; 768 } 769 770 /// getExceptionSelectorRegister - If a physical register, this returns 771 /// the register that receives the exception typeid on entry to a landing 772 /// pad. 773 unsigned getExceptionSelectorRegister() const { 774 return ExceptionSelectorRegister; 775 } 776 777 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 778 /// set, the default is 200) 779 unsigned getJumpBufSize() const { 780 return JumpBufSize; 781 } 782 783 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 784 /// (if never set, the default is 0) 785 unsigned getJumpBufAlignment() const { 786 return JumpBufAlignment; 787 } 788 789 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 790 /// argument. 791 unsigned getMinStackArgumentAlignment() const { 792 return MinStackArgumentAlignment; 793 } 794 795 /// getMinFunctionAlignment - return the minimum function alignment. 796 /// 797 unsigned getMinFunctionAlignment() const { 798 return MinFunctionAlignment; 799 } 800 801 /// getPrefFunctionAlignment - return the preferred function alignment. 802 /// 803 unsigned getPrefFunctionAlignment() const { 804 return PrefFunctionAlignment; 805 } 806 807 /// getPrefLoopAlignment - return the preferred loop alignment. 808 /// 809 unsigned getPrefLoopAlignment() const { 810 return PrefLoopAlignment; 811 } 812 813 /// getShouldFoldAtomicFences - return whether the combiner should fold 814 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 815 /// 816 bool getShouldFoldAtomicFences() const { 817 return ShouldFoldAtomicFences; 818 } 819 820 /// getInsertFencesFor - return whether the DAG builder should automatically 821 /// insert fences and reduce ordering for atomics. 822 /// 823 bool getInsertFencesForAtomic() const { 824 return InsertFencesForAtomic; 825 } 826 827 /// getStackCookieLocation - Return true if the target stores stack 828 /// protector cookies at a fixed offset in some non-standard address 829 /// space, and populates the address space and offset as 830 /// appropriate. 831 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/, 832 unsigned &/*Offset*/) const { 833 return false; 834 } 835 836 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be 837 /// used for loads / stores from the global. 838 virtual unsigned getMaximalGlobalOffset() const { 839 return 0; 840 } 841 842 //===--------------------------------------------------------------------===// 843 /// \name Helpers for TargetTransformInfo implementations 844 /// @{ 845 846 /// Get the ISD node that corresponds to the Instruction class opcode. 847 int InstructionOpcodeToISD(unsigned Opcode) const; 848 849 /// Estimate the cost of type-legalization and the legalized type. 850 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const; 851 852 /// @} 853 854 //===--------------------------------------------------------------------===// 855 // TargetLowering Configuration Methods - These methods should be invoked by 856 // the derived class constructor to configure this object for the target. 857 // 858 859 /// \brief Reset the operation actions based on target options. 860 virtual void resetOperationActions() {} 861 862protected: 863 /// setBooleanContents - Specify how the target extends the result of a 864 /// boolean value from i1 to a wider type. See getBooleanContents. 865 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 866 /// setBooleanVectorContents - Specify how the target extends the result 867 /// of a vector boolean value from a vector of i1 to a wider type. See 868 /// getBooleanContents. 869 void setBooleanVectorContents(BooleanContent Ty) { 870 BooleanVectorContents = Ty; 871 } 872 873 /// setSchedulingPreference - Specify the target scheduling preference. 874 void setSchedulingPreference(Sched::Preference Pref) { 875 SchedPreferenceInfo = Pref; 876 } 877 878 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 879 /// use _setjmp to implement llvm.setjmp or the non _ version. 880 /// Defaults to false. 881 void setUseUnderscoreSetJmp(bool Val) { 882 UseUnderscoreSetJmp = Val; 883 } 884 885 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 886 /// use _longjmp to implement llvm.longjmp or the non _ version. 887 /// Defaults to false. 888 void setUseUnderscoreLongJmp(bool Val) { 889 UseUnderscoreLongJmp = Val; 890 } 891 892 /// setSupportJumpTables - Indicate whether the target can generate code for 893 /// jump tables. 894 void setSupportJumpTables(bool Val) { 895 SupportJumpTables = Val; 896 } 897 898 /// setMinimumJumpTableEntries - Indicate the number of blocks to generate 899 /// jump tables rather than if sequence. 900 void setMinimumJumpTableEntries(int Val) { 901 MinimumJumpTableEntries = Val; 902 } 903 904 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 905 /// specifies the register that llvm.savestack/llvm.restorestack should save 906 /// and restore. 907 void setStackPointerRegisterToSaveRestore(unsigned R) { 908 StackPointerRegisterToSaveRestore = R; 909 } 910 911 /// setExceptionPointerRegister - If set to a physical register, this sets 912 /// the register that receives the exception address on entry to a landing 913 /// pad. 914 void setExceptionPointerRegister(unsigned R) { 915 ExceptionPointerRegister = R; 916 } 917 918 /// setExceptionSelectorRegister - If set to a physical register, this sets 919 /// the register that receives the exception typeid on entry to a landing 920 /// pad. 921 void setExceptionSelectorRegister(unsigned R) { 922 ExceptionSelectorRegister = R; 923 } 924 925 /// SelectIsExpensive - Tells the code generator not to expand operations 926 /// into sequences that use the select operations if possible. 927 void setSelectIsExpensive(bool isExpensive = true) { 928 SelectIsExpensive = isExpensive; 929 } 930 931 /// JumpIsExpensive - Tells the code generator not to expand sequence of 932 /// operations into a separate sequences that increases the amount of 933 /// flow control. 934 void setJumpIsExpensive(bool isExpensive = true) { 935 JumpIsExpensive = isExpensive; 936 } 937 938 /// setIntDivIsCheap - Tells the code generator that integer divide is 939 /// expensive, and if possible, should be replaced by an alternate sequence 940 /// of instructions not containing an integer divide. 941 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 942 943 /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass. 944 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { 945 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; 946 } 947 948 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 949 /// srl/add/sra for a signed divide by power of two, and let the target handle 950 /// it. 951 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 952 953 /// addRegisterClass - Add the specified register class as an available 954 /// regclass for the specified value type. This indicates the selector can 955 /// handle values of that class natively. 956 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { 957 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); 958 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 959 RegClassForVT[VT.SimpleTy] = RC; 960 } 961 962 /// clearRegisterClasses - Remove all register classes. 963 void clearRegisterClasses() { 964 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*)); 965 966 AvailableRegClasses.clear(); 967 } 968 969 /// \brief Remove all operation actions. 970 void clearOperationActions() { 971 } 972 973 /// findRepresentativeClass - Return the largest legal super-reg register class 974 /// of the register class for the specified type and its associated "cost". 975 virtual std::pair<const TargetRegisterClass*, uint8_t> 976 findRepresentativeClass(MVT VT) const; 977 978 /// computeRegisterProperties - Once all of the register classes are added, 979 /// this allows us to compute derived properties we expose. 980 void computeRegisterProperties(); 981 982 /// setOperationAction - Indicate that the specified operation does not work 983 /// with the specified type and indicate what to do about it. 984 void setOperationAction(unsigned Op, MVT VT, 985 LegalizeAction Action) { 986 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 987 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 988 } 989 990 /// setLoadExtAction - Indicate that the specified load with extension does 991 /// not work with the specified type and indicate what to do about it. 992 void setLoadExtAction(unsigned ExtType, MVT VT, 993 LegalizeAction Action) { 994 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 995 "Table isn't big enough!"); 996 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 997 } 998 999 /// setTruncStoreAction - Indicate that the specified truncating store does 1000 /// not work with the specified type and indicate what to do about it. 1001 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1002 LegalizeAction Action) { 1003 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 1004 "Table isn't big enough!"); 1005 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 1006 } 1007 1008 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1009 /// does not work with the specified type and indicate what to do abort 1010 /// it. NOTE: All indexed mode loads are initialized to Expand in 1011 /// TargetLowering.cpp 1012 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1013 LegalizeAction Action) { 1014 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1015 (unsigned)Action < 0xf && "Table isn't big enough!"); 1016 // Load action are kept in the upper half. 1017 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1018 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1019 } 1020 1021 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1022 /// does not work with the specified type and indicate what to do about 1023 /// it. NOTE: All indexed mode stores are initialized to Expand in 1024 /// TargetLowering.cpp 1025 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1026 LegalizeAction Action) { 1027 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1028 (unsigned)Action < 0xf && "Table isn't big enough!"); 1029 // Store action are kept in the lower half. 1030 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1031 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1032 } 1033 1034 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1035 /// supported on the target and indicate what to do about it. 1036 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1037 LegalizeAction Action) { 1038 assert(VT < MVT::LAST_VALUETYPE && 1039 (unsigned)CC < array_lengthof(CondCodeActions) && 1040 "Table isn't big enough!"); 1041 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 1042 /// value and the upper 27 bits index into the second dimension of the 1043 /// array to select what 64bit value to use. 1044 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1045 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2); 1046 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1047 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2; 1048 } 1049 1050 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1051 /// promotion code defaults to trying a larger integer/fp until it can find 1052 /// one that works. If that default is insufficient, this method can be used 1053 /// by the target to override the default. 1054 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1055 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1056 } 1057 1058 /// setTargetDAGCombine - Targets should invoke this method for each target 1059 /// independent node that they want to provide a custom DAG combiner for by 1060 /// implementing the PerformDAGCombine virtual method. 1061 void setTargetDAGCombine(ISD::NodeType NT) { 1062 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1063 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1064 } 1065 1066 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1067 /// bytes); default is 200 1068 void setJumpBufSize(unsigned Size) { 1069 JumpBufSize = Size; 1070 } 1071 1072 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1073 /// alignment (in bytes); default is 0 1074 void setJumpBufAlignment(unsigned Align) { 1075 JumpBufAlignment = Align; 1076 } 1077 1078 /// setMinFunctionAlignment - Set the target's minimum function alignment (in 1079 /// log2(bytes)) 1080 void setMinFunctionAlignment(unsigned Align) { 1081 MinFunctionAlignment = Align; 1082 } 1083 1084 /// setPrefFunctionAlignment - Set the target's preferred function alignment. 1085 /// This should be set if there is a performance benefit to 1086 /// higher-than-minimum alignment (in log2(bytes)) 1087 void setPrefFunctionAlignment(unsigned Align) { 1088 PrefFunctionAlignment = Align; 1089 } 1090 1091 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1092 /// alignment is zero, it means the target does not care about loop alignment. 1093 /// The alignment is specified in log2(bytes). 1094 void setPrefLoopAlignment(unsigned Align) { 1095 PrefLoopAlignment = Align; 1096 } 1097 1098 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1099 /// argument (in log2(bytes)). 1100 void setMinStackArgumentAlignment(unsigned Align) { 1101 MinStackArgumentAlignment = Align; 1102 } 1103 1104 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1105 /// atomic operation intrinsics includes locking. Default is false. 1106 void setShouldFoldAtomicFences(bool fold) { 1107 ShouldFoldAtomicFences = fold; 1108 } 1109 1110 /// setInsertFencesForAtomic - Set if the DAG builder should 1111 /// automatically insert fences and reduce the order of atomic memory 1112 /// operations to Monotonic. 1113 void setInsertFencesForAtomic(bool fence) { 1114 InsertFencesForAtomic = fence; 1115 } 1116 1117public: 1118 //===--------------------------------------------------------------------===// 1119 // Addressing mode description hooks (used by LSR etc). 1120 // 1121 1122 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the 1123 /// same BB as Load/Store instructions reading the address. This allows as 1124 /// much computation as possible to be done in the address mode for that 1125 /// operand. This hook lets targets also pass back when this should be done 1126 /// on intrinsics which load/store. 1127 virtual bool GetAddrModeArguments(IntrinsicInst *I, 1128 SmallVectorImpl<Value*> &Ops, 1129 Type *&AccessTy) const { 1130 return false; 1131 } 1132 1133 /// AddrMode - This represents an addressing mode of: 1134 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1135 /// If BaseGV is null, there is no BaseGV. 1136 /// If BaseOffs is zero, there is no base offset. 1137 /// If HasBaseReg is false, there is no base register. 1138 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1139 /// no scale. 1140 /// 1141 struct AddrMode { 1142 GlobalValue *BaseGV; 1143 int64_t BaseOffs; 1144 bool HasBaseReg; 1145 int64_t Scale; 1146 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1147 }; 1148 1149 /// isLegalAddressingMode - Return true if the addressing mode represented by 1150 /// AM is legal for this target, for a load/store of the specified type. 1151 /// The type may be VoidTy, in which case only return true if the addressing 1152 /// mode is legal for a load/store of any legal type. 1153 /// TODO: Handle pre/postinc as well. 1154 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 1155 1156 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1157 /// icmp immediate, that is the target has icmp instructions which can compare 1158 /// a register against the immediate without having to materialize the 1159 /// immediate into a register. 1160 virtual bool isLegalICmpImmediate(int64_t) const { 1161 return true; 1162 } 1163 1164 /// isLegalAddImmediate - Return true if the specified immediate is legal 1165 /// add immediate, that is the target has add instructions which can add 1166 /// a register with the immediate without having to materialize the 1167 /// immediate into a register. 1168 virtual bool isLegalAddImmediate(int64_t) const { 1169 return true; 1170 } 1171 1172 /// isTruncateFree - Return true if it's free to truncate a value of 1173 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1174 /// register EAX to i16 by referencing its sub-register AX. 1175 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1176 return false; 1177 } 1178 1179 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const { 1180 return false; 1181 } 1182 1183 /// isZExtFree - Return true if any actual instruction that defines a 1184 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1185 /// register. This does not necessarily include registers defined in 1186 /// unknown ways, such as incoming arguments, or copies from unknown 1187 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1188 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1189 /// all instructions that define 32-bit values implicit zero-extend the 1190 /// result out to 64 bits. 1191 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1192 return false; 1193 } 1194 1195 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const { 1196 return false; 1197 } 1198 1199 /// isZExtFree - Return true if zero-extending the specific node Val to type 1200 /// VT2 is free (either because it's implicitly zero-extended such as ARM 1201 /// ldrb / ldrh or because it's folded such as X86 zero-extending loads). 1202 virtual bool isZExtFree(SDValue Val, EVT VT2) const { 1203 return isZExtFree(Val.getValueType(), VT2); 1204 } 1205 1206 /// isFNegFree - Return true if an fneg operation is free to the point where 1207 /// it is never worthwhile to replace it with a bitwise operation. 1208 virtual bool isFNegFree(EVT) const { 1209 return false; 1210 } 1211 1212 /// isFAbsFree - Return true if an fneg operation is free to the point where 1213 /// it is never worthwhile to replace it with a bitwise operation. 1214 virtual bool isFAbsFree(EVT) const { 1215 return false; 1216 } 1217 1218 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 1219 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 1220 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 1221 /// is expanded to mul + add. 1222 virtual bool isFMAFasterThanMulAndAdd(EVT) const { 1223 return false; 1224 } 1225 1226 /// isNarrowingProfitable - Return true if it's profitable to narrow 1227 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1228 /// from i32 to i8 but not from i32 to i16. 1229 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { 1230 return false; 1231 } 1232 1233 //===--------------------------------------------------------------------===// 1234 // Runtime Library hooks 1235 // 1236 1237 /// setLibcallName - Rename the default libcall routine name for the specified 1238 /// libcall. 1239 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1240 LibcallRoutineNames[Call] = Name; 1241 } 1242 1243 /// getLibcallName - Get the libcall routine name for the specified libcall. 1244 /// 1245 const char *getLibcallName(RTLIB::Libcall Call) const { 1246 return LibcallRoutineNames[Call]; 1247 } 1248 1249 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1250 /// result of the comparison libcall against zero. 1251 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1252 CmpLibcallCCs[Call] = CC; 1253 } 1254 1255 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1256 /// the comparison libcall against zero. 1257 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1258 return CmpLibcallCCs[Call]; 1259 } 1260 1261 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1262 /// specified libcall. 1263 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1264 LibcallCallingConvs[Call] = CC; 1265 } 1266 1267 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1268 /// specified libcall. 1269 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1270 return LibcallCallingConvs[Call]; 1271 } 1272 1273private: 1274 const TargetMachine &TM; 1275 const DataLayout *TD; 1276 const TargetLoweringObjectFile &TLOF; 1277 1278 /// PointerTy - The type to use for pointers for the default address space, 1279 /// usually i32 or i64. 1280 /// 1281 MVT PointerTy; 1282 1283 /// IsLittleEndian - True if this is a little endian target. 1284 /// 1285 bool IsLittleEndian; 1286 1287 /// SelectIsExpensive - Tells the code generator not to expand operations 1288 /// into sequences that use the select operations if possible. 1289 bool SelectIsExpensive; 1290 1291 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1292 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1293 /// a real cost model is in place. If we ever optimize for size, this will be 1294 /// set to true unconditionally. 1295 bool IntDivIsCheap; 1296 1297 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or 1298 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the 1299 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned 1300 /// integer div/rem when the operands are positive and less than 256. 1301 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths; 1302 1303 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1304 /// srl/add/sra for a signed divide by power of two, and let the target handle 1305 /// it. 1306 bool Pow2DivIsCheap; 1307 1308 /// JumpIsExpensive - Tells the code generator that it shouldn't generate 1309 /// extra flow control instructions and should attempt to combine flow 1310 /// control instructions via predication. 1311 bool JumpIsExpensive; 1312 1313 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1314 /// llvm.setjmp. Defaults to false. 1315 bool UseUnderscoreSetJmp; 1316 1317 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1318 /// llvm.longjmp. Defaults to false. 1319 bool UseUnderscoreLongJmp; 1320 1321 /// SupportJumpTables - Whether the target can generate code for jumptables. 1322 /// If it's not true, then each jumptable must be lowered into if-then-else's. 1323 bool SupportJumpTables; 1324 1325 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables. 1326 int MinimumJumpTableEntries; 1327 1328 /// BooleanContents - Information about the contents of the high-bits in 1329 /// boolean values held in a type wider than i1. See getBooleanContents. 1330 BooleanContent BooleanContents; 1331 /// BooleanVectorContents - Information about the contents of the high-bits 1332 /// in boolean vector values when the element type is wider than i1. See 1333 /// getBooleanContents. 1334 BooleanContent BooleanVectorContents; 1335 1336 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1337 /// total cycles or lowest register usage. 1338 Sched::Preference SchedPreferenceInfo; 1339 1340 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1341 unsigned JumpBufSize; 1342 1343 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1344 /// buffers 1345 unsigned JumpBufAlignment; 1346 1347 /// MinStackArgumentAlignment - The minimum alignment that any argument 1348 /// on the stack needs to have. 1349 /// 1350 unsigned MinStackArgumentAlignment; 1351 1352 /// MinFunctionAlignment - The minimum function alignment (used when 1353 /// optimizing for size, and to prevent explicitly provided alignment 1354 /// from leading to incorrect code). 1355 /// 1356 unsigned MinFunctionAlignment; 1357 1358 /// PrefFunctionAlignment - The preferred function alignment (used when 1359 /// alignment unspecified and optimizing for speed). 1360 /// 1361 unsigned PrefFunctionAlignment; 1362 1363 /// PrefLoopAlignment - The preferred loop alignment. 1364 /// 1365 unsigned PrefLoopAlignment; 1366 1367 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1368 /// be folded into the enclosed atomic intrinsic instruction by the 1369 /// combiner. 1370 bool ShouldFoldAtomicFences; 1371 1372 /// InsertFencesForAtomic - Whether the DAG builder should automatically 1373 /// insert fences and reduce ordering for atomics. (This will be set for 1374 /// for most architectures with weak memory ordering.) 1375 bool InsertFencesForAtomic; 1376 1377 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1378 /// specifies the register that llvm.savestack/llvm.restorestack should save 1379 /// and restore. 1380 unsigned StackPointerRegisterToSaveRestore; 1381 1382 /// ExceptionPointerRegister - If set to a physical register, this specifies 1383 /// the register that receives the exception address on entry to a landing 1384 /// pad. 1385 unsigned ExceptionPointerRegister; 1386 1387 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1388 /// the register that receives the exception typeid on entry to a landing 1389 /// pad. 1390 unsigned ExceptionSelectorRegister; 1391 1392 /// RegClassForVT - This indicates the default register class to use for 1393 /// each ValueType the target supports natively. 1394 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1395 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1396 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1397 1398 /// RepRegClassForVT - This indicates the "representative" register class to 1399 /// use for each ValueType the target supports natively. This information is 1400 /// used by the scheduler to track register pressure. By default, the 1401 /// representative register class is the largest legal super-reg register 1402 /// class of the register class of the specified type. e.g. On x86, i8, i16, 1403 /// and i32's representative class would be GR32. 1404 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1405 1406 /// RepRegClassCostForVT - This indicates the "cost" of the "representative" 1407 /// register class for each ValueType. The cost is used by the scheduler to 1408 /// approximate register pressure. 1409 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1410 1411 /// TransformToType - For any value types we are promoting or expanding, this 1412 /// contains the value type that we are changing to. For Expanded types, this 1413 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1414 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1415 /// by the system, this holds the same type (e.g. i32 -> i32). 1416 MVT TransformToType[MVT::LAST_VALUETYPE]; 1417 1418 /// OpActions - For each operation and each value type, keep a LegalizeAction 1419 /// that indicates how instruction selection should deal with the operation. 1420 /// Most operations are Legal (aka, supported natively by the target), but 1421 /// operations that are not should be described. Note that operations on 1422 /// non-legal value types are not described here. 1423 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1424 1425 /// LoadExtActions - For each load extension type and each value type, 1426 /// keep a LegalizeAction that indicates how instruction selection should deal 1427 /// with a load of a specific value type and extension type. 1428 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1429 1430 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1431 /// indicates whether a truncating store of a specific value type and 1432 /// truncating type is legal. 1433 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1434 1435 /// IndexedModeActions - For each indexed mode and each value type, 1436 /// keep a pair of LegalizeAction that indicates how instruction 1437 /// selection should deal with the load / store. The first dimension is the 1438 /// value_type for the reference. The second dimension represents the various 1439 /// modes for load store. 1440 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1441 1442 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1443 /// LegalizeAction that indicates how instruction selection should 1444 /// deal with the condition code. 1445 /// Because each CC action takes up 2 bits, we need to have the array size 1446 /// be large enough to fit all of the value types. This can be done by 1447 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one. 1448 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1]; 1449 1450 ValueTypeActionImpl ValueTypeActions; 1451 1452public: 1453 LegalizeKind 1454 getTypeConversion(LLVMContext &Context, EVT VT) const { 1455 // If this is a simple type, use the ComputeRegisterProp mechanism. 1456 if (VT.isSimple()) { 1457 MVT SVT = VT.getSimpleVT(); 1458 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 1459 MVT NVT = TransformToType[SVT.SimpleTy]; 1460 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 1461 1462 assert( 1463 (LA == TypeLegal || 1464 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) 1465 && "Promote may not follow Expand or Promote"); 1466 1467 if (LA == TypeSplitVector) 1468 return LegalizeKind(LA, EVT::getVectorVT(Context, 1469 SVT.getVectorElementType(), 1470 SVT.getVectorNumElements()/2)); 1471 if (LA == TypeScalarizeVector) 1472 return LegalizeKind(LA, SVT.getVectorElementType()); 1473 return LegalizeKind(LA, NVT); 1474 } 1475 1476 // Handle Extended Scalar Types. 1477 if (!VT.isVector()) { 1478 assert(VT.isInteger() && "Float types must be simple"); 1479 unsigned BitSize = VT.getSizeInBits(); 1480 // First promote to a power-of-two size, then expand if necessary. 1481 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1482 EVT NVT = VT.getRoundIntegerType(Context); 1483 assert(NVT != VT && "Unable to round integer VT"); 1484 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1485 // Avoid multi-step promotion. 1486 if (NextStep.first == TypePromoteInteger) return NextStep; 1487 // Return rounded integer type. 1488 return LegalizeKind(TypePromoteInteger, NVT); 1489 } 1490 1491 return LegalizeKind(TypeExpandInteger, 1492 EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); 1493 } 1494 1495 // Handle vector types. 1496 unsigned NumElts = VT.getVectorNumElements(); 1497 EVT EltVT = VT.getVectorElementType(); 1498 1499 // Vectors with only one element are always scalarized. 1500 if (NumElts == 1) 1501 return LegalizeKind(TypeScalarizeVector, EltVT); 1502 1503 // Try to widen vector elements until a legal type is found. 1504 if (EltVT.isInteger()) { 1505 // Vectors with a number of elements that is not a power of two are always 1506 // widened, for example <3 x float> -> <4 x float>. 1507 if (!VT.isPow2VectorType()) { 1508 NumElts = (unsigned)NextPowerOf2(NumElts); 1509 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1510 return LegalizeKind(TypeWidenVector, NVT); 1511 } 1512 1513 // Examine the element type. 1514 LegalizeKind LK = getTypeConversion(Context, EltVT); 1515 1516 // If type is to be expanded, split the vector. 1517 // <4 x i140> -> <2 x i140> 1518 if (LK.first == TypeExpandInteger) 1519 return LegalizeKind(TypeSplitVector, 1520 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1521 1522 // Promote the integer element types until a legal vector type is found 1523 // or until the element integer type is too big. If a legal type was not 1524 // found, fallback to the usual mechanism of widening/splitting the 1525 // vector. 1526 EVT OldEltVT = EltVT; 1527 while (1) { 1528 // Increase the bitwidth of the element to the next pow-of-two 1529 // (which is greater than 8 bits). 1530 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() 1531 ).getRoundIntegerType(Context); 1532 1533 // Stop trying when getting a non-simple element type. 1534 // Note that vector elements may be greater than legal vector element 1535 // types. Example: X86 XMM registers hold 64bit element on 32bit systems. 1536 if (!EltVT.isSimple()) break; 1537 1538 // Build a new vector type and check if it is legal. 1539 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1540 // Found a legal promoted vector type. 1541 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1542 return LegalizeKind(TypePromoteInteger, 1543 EVT::getVectorVT(Context, EltVT, NumElts)); 1544 } 1545 1546 // Reset the type to the unexpanded type if we did not find a legal vector 1547 // type with a promoted vector element type. 1548 EltVT = OldEltVT; 1549 } 1550 1551 // Try to widen the vector until a legal type is found. 1552 // If there is no wider legal type, split the vector. 1553 while (1) { 1554 // Round up to the next power of 2. 1555 NumElts = (unsigned)NextPowerOf2(NumElts); 1556 1557 // If there is no simple vector type with this many elements then there 1558 // cannot be a larger legal vector type. Note that this assumes that 1559 // there are no skipped intermediate vector types in the simple types. 1560 if (!EltVT.isSimple()) break; 1561 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1562 if (LargerVector == MVT()) break; 1563 1564 // If this type is legal then widen the vector. 1565 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1566 return LegalizeKind(TypeWidenVector, LargerVector); 1567 } 1568 1569 // Widen odd vectors to next power of two. 1570 if (!VT.isPow2VectorType()) { 1571 EVT NVT = VT.getPow2VectorType(Context); 1572 return LegalizeKind(TypeWidenVector, NVT); 1573 } 1574 1575 // Vectors with illegal element types are expanded. 1576 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1577 return LegalizeKind(TypeSplitVector, NVT); 1578 } 1579 1580private: 1581 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses; 1582 1583 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1584 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1585 /// which sets a bit in this array. 1586 unsigned char 1587 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1588 1589 /// PromoteToType - For operations that must be promoted to a specific type, 1590 /// this holds the destination type. This map should be sparse, so don't hold 1591 /// it as an array. 1592 /// 1593 /// Targets add entries to this map with AddPromotedToType(..), clients access 1594 /// this with getTypeToPromoteTo(..). 1595 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1596 PromoteToType; 1597 1598 /// LibcallRoutineNames - Stores the name each libcall. 1599 /// 1600 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1601 1602 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1603 /// of each of the comparison libcall against zero. 1604 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1605 1606 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1607 /// libcall. 1608 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1609 1610protected: 1611 /// When lowering \@llvm.memset this field specifies the maximum number of 1612 /// store operations that may be substituted for the call to memset. Targets 1613 /// must set this value based on the cost threshold for that target. Targets 1614 /// should assume that the memset will be done using as many of the largest 1615 /// store operations first, followed by smaller ones, if necessary, per 1616 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1617 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1618 /// store. This only applies to setting a constant array of a constant size. 1619 /// @brief Specify maximum number of store instructions per memset call. 1620 unsigned MaxStoresPerMemset; 1621 1622 /// Maximum number of stores operations that may be substituted for the call 1623 /// to memset, used for functions with OptSize attribute. 1624 unsigned MaxStoresPerMemsetOptSize; 1625 1626 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1627 /// store operations that may be substituted for a call to memcpy. Targets 1628 /// must set this value based on the cost threshold for that target. Targets 1629 /// should assume that the memcpy will be done using as many of the largest 1630 /// store operations first, followed by smaller ones, if necessary, per 1631 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1632 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1633 /// and one 1-byte store. This only applies to copying a constant array of 1634 /// constant size. 1635 /// @brief Specify maximum bytes of store instructions per memcpy call. 1636 unsigned MaxStoresPerMemcpy; 1637 1638 /// Maximum number of store operations that may be substituted for a call 1639 /// to memcpy, used for functions with OptSize attribute. 1640 unsigned MaxStoresPerMemcpyOptSize; 1641 1642 /// When lowering \@llvm.memmove this field specifies the maximum number of 1643 /// store instructions that may be substituted for a call to memmove. Targets 1644 /// must set this value based on the cost threshold for that target. Targets 1645 /// should assume that the memmove will be done using as many of the largest 1646 /// store operations first, followed by smaller ones, if necessary, per 1647 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1648 /// with 8-bit alignment would result in nine 1-byte stores. This only 1649 /// applies to copying a constant array of constant size. 1650 /// @brief Specify maximum bytes of store instructions per memmove call. 1651 unsigned MaxStoresPerMemmove; 1652 1653 /// Maximum number of store instructions that may be substituted for a call 1654 /// to memmove, used for functions with OpSize attribute. 1655 unsigned MaxStoresPerMemmoveOptSize; 1656 1657 /// PredictableSelectIsExpensive - Tells the code generator that select is 1658 /// more expensive than a branch if the branch is usually predicted right. 1659 bool PredictableSelectIsExpensive; 1660 1661protected: 1662 /// isLegalRC - Return true if the value types that can be represented by the 1663 /// specified register class are all legal. 1664 bool isLegalRC(const TargetRegisterClass *RC) const; 1665}; 1666 1667//===----------------------------------------------------------------------===// 1668/// TargetLowering - This class defines information used to lower LLVM code to 1669/// legal SelectionDAG operators that the target instruction selector can accept 1670/// natively. 1671/// 1672/// This class also defines callbacks that targets must implement to lower 1673/// target-specific constructs to SelectionDAG operators. 1674/// 1675class TargetLowering : public TargetLoweringBase { 1676 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION; 1677 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION; 1678 1679public: 1680 /// NOTE: The constructor takes ownership of TLOF. 1681 explicit TargetLowering(const TargetMachine &TM, 1682 const TargetLoweringObjectFile *TLOF); 1683 1684 /// getPreIndexedAddressParts - returns true by value, base pointer and 1685 /// offset pointer and addressing mode by reference if the node's address 1686 /// can be legally represented as pre-indexed load / store address. 1687 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, 1688 SDValue &/*Offset*/, 1689 ISD::MemIndexedMode &/*AM*/, 1690 SelectionDAG &/*DAG*/) const { 1691 return false; 1692 } 1693 1694 /// getPostIndexedAddressParts - returns true by value, base pointer and 1695 /// offset pointer and addressing mode by reference if this node can be 1696 /// combined with a load / store to form a post-indexed load / store. 1697 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, 1698 SDValue &/*Base*/, SDValue &/*Offset*/, 1699 ISD::MemIndexedMode &/*AM*/, 1700 SelectionDAG &/*DAG*/) const { 1701 return false; 1702 } 1703 1704 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 1705 /// current function. The returned value is a member of the 1706 /// MachineJumpTableInfo::JTEntryKind enum. 1707 virtual unsigned getJumpTableEncoding() const; 1708 1709 virtual const MCExpr * 1710 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/, 1711 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/, 1712 MCContext &/*Ctx*/) const { 1713 llvm_unreachable("Need to implement this hook if target has custom JTIs"); 1714 } 1715 1716 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1717 /// jumptable. 1718 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 1719 SelectionDAG &DAG) const; 1720 1721 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1722 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1723 /// MCExpr. 1724 virtual const MCExpr * 1725 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1726 unsigned JTI, MCContext &Ctx) const; 1727 1728 /// isOffsetFoldingLegal - Return true if folding a constant offset 1729 /// with the given GlobalAddress is legal. It is frequently not legal in 1730 /// PIC relocation models. 1731 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 1732 1733 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 1734 SDValue &Chain) const; 1735 1736 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, 1737 SDValue &NewLHS, SDValue &NewRHS, 1738 ISD::CondCode &CCCode, DebugLoc DL) const; 1739 1740 SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, 1741 const SDValue *Ops, unsigned NumOps, 1742 bool isSigned, DebugLoc dl) const; 1743 1744 //===--------------------------------------------------------------------===// 1745 // TargetLowering Optimization Methods 1746 // 1747 1748 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 1749 /// SDValues for returning information from TargetLowering to its clients 1750 /// that want to combine 1751 struct TargetLoweringOpt { 1752 SelectionDAG &DAG; 1753 bool LegalTys; 1754 bool LegalOps; 1755 SDValue Old; 1756 SDValue New; 1757 1758 explicit TargetLoweringOpt(SelectionDAG &InDAG, 1759 bool LT, bool LO) : 1760 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 1761 1762 bool LegalTypes() const { return LegalTys; } 1763 bool LegalOperations() const { return LegalOps; } 1764 1765 bool CombineTo(SDValue O, SDValue N) { 1766 Old = O; 1767 New = N; 1768 return true; 1769 } 1770 1771 /// ShrinkDemandedConstant - Check to see if the specified operand of the 1772 /// specified instruction is a constant integer. If so, check to see if 1773 /// there are any bits set in the constant that are not demanded. If so, 1774 /// shrink the constant and return true. 1775 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 1776 1777 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1778 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1779 /// cast, but it could be generalized for targets with other types of 1780 /// implicit widening casts. 1781 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 1782 DebugLoc dl); 1783 }; 1784 1785 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1786 /// DemandedMask bits of the result of Op are ever used downstream. If we can 1787 /// use this information to simplify Op, create a new simplified DAG node and 1788 /// return true, returning the original and new nodes in Old and New. 1789 /// Otherwise, analyze the expression and return a mask of KnownOne and 1790 /// KnownZero bits for the expression (used to simplify the caller). 1791 /// The KnownZero/One bits may only be accurate for those bits in the 1792 /// DemandedMask. 1793 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 1794 APInt &KnownZero, APInt &KnownOne, 1795 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 1796 1797 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 1798 /// Mask are known to be either zero or one and return them in the 1799 /// KnownZero/KnownOne bitsets. 1800 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 1801 APInt &KnownZero, 1802 APInt &KnownOne, 1803 const SelectionDAG &DAG, 1804 unsigned Depth = 0) const; 1805 1806 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 1807 /// targets that want to expose additional information about sign bits to the 1808 /// DAG Combiner. 1809 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 1810 unsigned Depth = 0) const; 1811 1812 struct DAGCombinerInfo { 1813 void *DC; // The DAG Combiner object. 1814 CombineLevel Level; 1815 bool CalledByLegalizer; 1816 public: 1817 SelectionDAG &DAG; 1818 1819 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc) 1820 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {} 1821 1822 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } 1823 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } 1824 bool isAfterLegalizeVectorOps() const { 1825 return Level == AfterLegalizeDAG; 1826 } 1827 CombineLevel getDAGCombineLevel() { return Level; } 1828 bool isCalledByLegalizer() const { return CalledByLegalizer; } 1829 1830 void AddToWorklist(SDNode *N); 1831 void RemoveFromWorklist(SDNode *N); 1832 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 1833 bool AddTo = true); 1834 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 1835 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 1836 1837 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 1838 }; 1839 1840 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 1841 /// and cc. If it is unable to simplify it, return a null SDValue. 1842 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1843 ISD::CondCode Cond, bool foldBooleans, 1844 DAGCombinerInfo &DCI, DebugLoc dl) const; 1845 1846 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1847 /// node is a GlobalAddress + offset. 1848 virtual bool 1849 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 1850 1851 /// PerformDAGCombine - This method will be invoked for all target nodes and 1852 /// for any target-independent nodes that the target has registered with 1853 /// invoke it for. 1854 /// 1855 /// The semantics are as follows: 1856 /// Return Value: 1857 /// SDValue.Val == 0 - No change was made 1858 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 1859 /// otherwise - N should be replaced by the returned Operand. 1860 /// 1861 /// In addition, methods provided by DAGCombinerInfo may be used to perform 1862 /// more complex transformations. 1863 /// 1864 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 1865 1866 /// isTypeDesirableForOp - Return true if the target has native support for 1867 /// the specified value type and it is 'desirable' to use the type for the 1868 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 1869 /// instruction encodings are longer and some i16 instructions are slow. 1870 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { 1871 // By default, assume all legal types are desirable. 1872 return isTypeLegal(VT); 1873 } 1874 1875 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner 1876 /// to transform a floating point op of specified opcode to a equivalent op of 1877 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM. 1878 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, 1879 EVT /*VT*/) const { 1880 return false; 1881 } 1882 1883 /// IsDesirableToPromoteOp - This method query the target whether it is 1884 /// beneficial for dag combiner to promote the specified node. If true, it 1885 /// should return the desired promotion type by reference. 1886 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { 1887 return false; 1888 } 1889 1890 //===--------------------------------------------------------------------===// 1891 // Lowering methods - These methods must be implemented by targets so that 1892 // the SelectionDAGBuilder code knows how to lower these. 1893 // 1894 1895 /// LowerFormalArguments - This hook must be implemented to lower the 1896 /// incoming (formal) arguments, described by the Ins array, into the 1897 /// specified DAG. The implementation should fill in the InVals array 1898 /// with legal-type argument values, and return the resulting token 1899 /// chain value. 1900 /// 1901 virtual SDValue 1902 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1903 bool /*isVarArg*/, 1904 const SmallVectorImpl<ISD::InputArg> &/*Ins*/, 1905 DebugLoc /*dl*/, SelectionDAG &/*DAG*/, 1906 SmallVectorImpl<SDValue> &/*InVals*/) const { 1907 llvm_unreachable("Not Implemented"); 1908 } 1909 1910 struct ArgListEntry { 1911 SDValue Node; 1912 Type* Ty; 1913 bool isSExt : 1; 1914 bool isZExt : 1; 1915 bool isInReg : 1; 1916 bool isSRet : 1; 1917 bool isNest : 1; 1918 bool isByVal : 1; 1919 bool isReturned : 1; 1920 uint16_t Alignment; 1921 1922 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1923 isSRet(false), isNest(false), isByVal(false), isReturned(false), 1924 Alignment(0) { } 1925 }; 1926 typedef std::vector<ArgListEntry> ArgListTy; 1927 1928 /// CallLoweringInfo - This structure contains all information that is 1929 /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the 1930 /// SelectionDAG builder needs to lower a call, and targets will see this 1931 /// struct in their LowerCall implementation. 1932 struct CallLoweringInfo { 1933 SDValue Chain; 1934 Type *RetTy; 1935 bool RetSExt : 1; 1936 bool RetZExt : 1; 1937 bool IsVarArg : 1; 1938 bool IsInReg : 1; 1939 bool DoesNotReturn : 1; 1940 bool IsReturnValueUsed : 1; 1941 1942 // IsTailCall should be modified by implementations of 1943 // TargetLowering::LowerCall that perform tail call conversions. 1944 bool IsTailCall; 1945 1946 unsigned NumFixedArgs; 1947 CallingConv::ID CallConv; 1948 SDValue Callee; 1949 ArgListTy &Args; 1950 SelectionDAG &DAG; 1951 DebugLoc DL; 1952 ImmutableCallSite *CS; 1953 SmallVector<ISD::OutputArg, 32> Outs; 1954 SmallVector<SDValue, 32> OutVals; 1955 SmallVector<ISD::InputArg, 32> Ins; 1956 1957 1958 /// CallLoweringInfo - Constructs a call lowering context based on the 1959 /// ImmutableCallSite \p cs. 1960 CallLoweringInfo(SDValue chain, Type *retTy, 1961 FunctionType *FTy, bool isTailCall, SDValue callee, 1962 ArgListTy &args, SelectionDAG &dag, DebugLoc dl, 1963 ImmutableCallSite &cs) 1964 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)), 1965 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()), 1966 IsInReg(cs.paramHasAttr(0, Attribute::InReg)), 1967 DoesNotReturn(cs.doesNotReturn()), 1968 IsReturnValueUsed(!cs.getInstruction()->use_empty()), 1969 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()), 1970 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag), 1971 DL(dl), CS(&cs) {} 1972 1973 /// CallLoweringInfo - Constructs a call lowering context based on the 1974 /// provided call information. 1975 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt, 1976 bool isVarArg, bool isInReg, unsigned numFixedArgs, 1977 CallingConv::ID callConv, bool isTailCall, 1978 bool doesNotReturn, bool isReturnValueUsed, SDValue callee, 1979 ArgListTy &args, SelectionDAG &dag, DebugLoc dl) 1980 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt), 1981 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn), 1982 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall), 1983 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee), 1984 Args(args), DAG(dag), DL(dl), CS(NULL) {} 1985 }; 1986 1987 /// LowerCallTo - This function lowers an abstract call to a function into an 1988 /// actual call. This returns a pair of operands. The first element is the 1989 /// return value for the function (if RetTy is not VoidTy). The second 1990 /// element is the outgoing token chain. It calls LowerCall to do the actual 1991 /// lowering. 1992 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const; 1993 1994 /// LowerCall - This hook must be implemented to lower calls into the 1995 /// the specified DAG. The outgoing arguments to the call are described 1996 /// by the Outs array, and the values to be returned by the call are 1997 /// described by the Ins array. The implementation should fill in the 1998 /// InVals array with legal-type return values from the call, and return 1999 /// the resulting token chain value. 2000 virtual SDValue 2001 LowerCall(CallLoweringInfo &/*CLI*/, 2002 SmallVectorImpl<SDValue> &/*InVals*/) const { 2003 llvm_unreachable("Not Implemented"); 2004 } 2005 2006 /// HandleByVal - Target-specific cleanup for formal ByVal parameters. 2007 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {} 2008 2009 /// CanLowerReturn - This hook should be implemented to check whether the 2010 /// return values described by the Outs array can fit into the return 2011 /// registers. If false is returned, an sret-demotion is performed. 2012 /// 2013 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, 2014 MachineFunction &/*MF*/, bool /*isVarArg*/, 2015 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 2016 LLVMContext &/*Context*/) const 2017 { 2018 // Return true by default to get preexisting behavior. 2019 return true; 2020 } 2021 2022 /// LowerReturn - This hook must be implemented to lower outgoing 2023 /// return values, described by the Outs array, into the specified 2024 /// DAG. The implementation should return the resulting token chain 2025 /// value. 2026 /// 2027 virtual SDValue 2028 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 2029 bool /*isVarArg*/, 2030 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 2031 const SmallVectorImpl<SDValue> &/*OutVals*/, 2032 DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const { 2033 llvm_unreachable("Not Implemented"); 2034 } 2035 2036 /// isUsedByReturnOnly - Return true if result of the specified node is used 2037 /// by a return node only. It also compute and return the input chain for the 2038 /// tail call. 2039 /// This is used to determine whether it is possible 2040 /// to codegen a libcall as tail call at legalization time. 2041 virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const { 2042 return false; 2043 } 2044 2045 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the 2046 /// call instruction as a tail call. This is used by optimization passes to 2047 /// determine if it's profitable to duplicate return instructions to enable 2048 /// tailcall optimization. 2049 virtual bool mayBeEmittedAsTailCall(CallInst *) const { 2050 return false; 2051 } 2052 2053 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or 2054 /// sign extend a zeroext/signext integer argument or return value. 2055 /// FIXME: Most C calling convention requires the return type to be promoted, 2056 /// but this is not true all the time, e.g. i1 on x86-64. It is also not 2057 /// necessary for non-C calling conventions. The frontend should handle this 2058 /// and include all of the necessary information. 2059 virtual MVT getTypeForExtArgOrReturn(MVT VT, 2060 ISD::NodeType /*ExtendKind*/) const { 2061 MVT MinVT = getRegisterType(MVT::i32); 2062 return VT.bitsLT(MinVT) ? MinVT : VT; 2063 } 2064 2065 /// LowerOperationWrapper - This callback is invoked by the type legalizer 2066 /// to legalize nodes with an illegal operand type but legal result types. 2067 /// It replaces the LowerOperation callback in the type Legalizer. 2068 /// The reason we can not do away with LowerOperation entirely is that 2069 /// LegalizeDAG isn't yet ready to use this callback. 2070 /// TODO: Consider merging with ReplaceNodeResults. 2071 2072 /// The target places new result values for the node in Results (their number 2073 /// and types must exactly match those of the original return values of 2074 /// the node), or leaves Results empty, which indicates that the node is not 2075 /// to be custom lowered after all. 2076 /// The default implementation calls LowerOperation. 2077 virtual void LowerOperationWrapper(SDNode *N, 2078 SmallVectorImpl<SDValue> &Results, 2079 SelectionDAG &DAG) const; 2080 2081 /// LowerOperation - This callback is invoked for operations that are 2082 /// unsupported by the target, which are registered to use 'custom' lowering, 2083 /// and whose defined values are all legal. 2084 /// If the target has no operations that require custom lowering, it need not 2085 /// implement this. The default implementation of this aborts. 2086 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 2087 2088 /// ReplaceNodeResults - This callback is invoked when a node result type is 2089 /// illegal for the target, and the operation was registered to use 'custom' 2090 /// lowering for that result type. The target places new result values for 2091 /// the node in Results (their number and types must exactly match those of 2092 /// the original return values of the node), or leaves Results empty, which 2093 /// indicates that the node is not to be custom lowered after all. 2094 /// 2095 /// If the target has no operations that require custom lowering, it need not 2096 /// implement this. The default implementation aborts. 2097 virtual void ReplaceNodeResults(SDNode * /*N*/, 2098 SmallVectorImpl<SDValue> &/*Results*/, 2099 SelectionDAG &/*DAG*/) const { 2100 llvm_unreachable("ReplaceNodeResults not implemented for this target!"); 2101 } 2102 2103 /// getTargetNodeName() - This method returns the name of a target specific 2104 /// DAG node. 2105 virtual const char *getTargetNodeName(unsigned Opcode) const; 2106 2107 /// createFastISel - This method returns a target specific FastISel object, 2108 /// or null if the target does not support "fast" ISel. 2109 virtual FastISel *createFastISel(FunctionLoweringInfo &, 2110 const TargetLibraryInfo *) const { 2111 return 0; 2112 } 2113 2114 //===--------------------------------------------------------------------===// 2115 // Inline Asm Support hooks 2116 // 2117 2118 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 2119 /// call to be explicit llvm code if it wants to. This is useful for 2120 /// turning simple inline asms into LLVM intrinsics, which gives the 2121 /// compiler more information about the behavior of the code. 2122 virtual bool ExpandInlineAsm(CallInst *) const { 2123 return false; 2124 } 2125 2126 enum ConstraintType { 2127 C_Register, // Constraint represents specific register(s). 2128 C_RegisterClass, // Constraint represents any of register(s) in class. 2129 C_Memory, // Memory constraint. 2130 C_Other, // Something else. 2131 C_Unknown // Unsupported constraint. 2132 }; 2133 2134 enum ConstraintWeight { 2135 // Generic weights. 2136 CW_Invalid = -1, // No match. 2137 CW_Okay = 0, // Acceptable. 2138 CW_Good = 1, // Good weight. 2139 CW_Better = 2, // Better weight. 2140 CW_Best = 3, // Best weight. 2141 2142 // Well-known weights. 2143 CW_SpecificReg = CW_Okay, // Specific register operands. 2144 CW_Register = CW_Good, // Register operands. 2145 CW_Memory = CW_Better, // Memory operands. 2146 CW_Constant = CW_Best, // Constant operand. 2147 CW_Default = CW_Okay // Default or don't know type. 2148 }; 2149 2150 /// AsmOperandInfo - This contains information for each constraint that we are 2151 /// lowering. 2152 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 2153 /// ConstraintCode - This contains the actual string for the code, like "m". 2154 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 2155 /// most closely matches the operand. 2156 std::string ConstraintCode; 2157 2158 /// ConstraintType - Information about the constraint code, e.g. Register, 2159 /// RegisterClass, Memory, Other, Unknown. 2160 TargetLowering::ConstraintType ConstraintType; 2161 2162 /// CallOperandval - If this is the result output operand or a 2163 /// clobber, this is null, otherwise it is the incoming operand to the 2164 /// CallInst. This gets modified as the asm is processed. 2165 Value *CallOperandVal; 2166 2167 /// ConstraintVT - The ValueType for the operand value. 2168 MVT ConstraintVT; 2169 2170 /// isMatchingInputConstraint - Return true of this is an input operand that 2171 /// is a matching constraint like "4". 2172 bool isMatchingInputConstraint() const; 2173 2174 /// getMatchedOperand - If this is an input matching constraint, this method 2175 /// returns the output operand it matches. 2176 unsigned getMatchedOperand() const; 2177 2178 /// Copy constructor for copying from an AsmOperandInfo. 2179 AsmOperandInfo(const AsmOperandInfo &info) 2180 : InlineAsm::ConstraintInfo(info), 2181 ConstraintCode(info.ConstraintCode), 2182 ConstraintType(info.ConstraintType), 2183 CallOperandVal(info.CallOperandVal), 2184 ConstraintVT(info.ConstraintVT) { 2185 } 2186 2187 /// Copy constructor for copying from a ConstraintInfo. 2188 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 2189 : InlineAsm::ConstraintInfo(info), 2190 ConstraintType(TargetLowering::C_Unknown), 2191 CallOperandVal(0), ConstraintVT(MVT::Other) { 2192 } 2193 }; 2194 2195 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; 2196 2197 /// ParseConstraints - Split up the constraint string from the inline 2198 /// assembly value into the specific constraints and their prefixes, 2199 /// and also tie in the associated operand values. 2200 /// If this returns an empty vector, and if the constraint string itself 2201 /// isn't empty, there was an error parsing. 2202 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; 2203 2204 /// Examine constraint type and operand type and determine a weight value. 2205 /// The operand object must already have been set up with the operand type. 2206 virtual ConstraintWeight getMultipleConstraintMatchWeight( 2207 AsmOperandInfo &info, int maIndex) const; 2208 2209 /// Examine constraint string and operand type and determine a weight value. 2210 /// The operand object must already have been set up with the operand type. 2211 virtual ConstraintWeight getSingleConstraintMatchWeight( 2212 AsmOperandInfo &info, const char *constraint) const; 2213 2214 /// ComputeConstraintToUse - Determines the constraint code and constraint 2215 /// type to use for the specific AsmOperandInfo, setting 2216 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 2217 /// being passed in is available, it can be passed in as Op, otherwise an 2218 /// empty SDValue can be passed. 2219 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2220 SDValue Op, 2221 SelectionDAG *DAG = 0) const; 2222 2223 /// getConstraintType - Given a constraint, return the type of constraint it 2224 /// is for this target. 2225 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 2226 2227 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 2228 /// {edx}), return the register number and the register class for the 2229 /// register. 2230 /// 2231 /// Given a register class constraint, like 'r', if this corresponds directly 2232 /// to an LLVM register class, return a register of 0 and the register class 2233 /// pointer. 2234 /// 2235 /// This should only be used for C_Register constraints. On error, 2236 /// this returns a register number of 0 and a null register class pointer.. 2237 virtual std::pair<unsigned, const TargetRegisterClass*> 2238 getRegForInlineAsmConstraint(const std::string &Constraint, 2239 EVT VT) const; 2240 2241 /// LowerXConstraint - try to replace an X constraint, which matches anything, 2242 /// with another that has more specific requirements based on the type of the 2243 /// corresponding operand. This returns null if there is no replacement to 2244 /// make. 2245 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 2246 2247 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2248 /// vector. If it is invalid, don't add anything to Ops. 2249 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 2250 std::vector<SDValue> &Ops, 2251 SelectionDAG &DAG) const; 2252 2253 //===--------------------------------------------------------------------===// 2254 // Div utility functions 2255 // 2256 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 2257 SelectionDAG &DAG) const; 2258 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2259 std::vector<SDNode*> *Created) const; 2260 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2261 std::vector<SDNode*> *Created) const; 2262 2263 //===--------------------------------------------------------------------===// 2264 // Instruction Emitting Hooks 2265 // 2266 2267 // EmitInstrWithCustomInserter - This method should be implemented by targets 2268 // that mark instructions with the 'usesCustomInserter' flag. These 2269 // instructions are special in various ways, which require special support to 2270 // insert. The specified MachineInstr is created but not inserted into any 2271 // basic blocks, and this method is called to expand it into a sequence of 2272 // instructions, potentially also creating new basic blocks and control flow. 2273 virtual MachineBasicBlock * 2274 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 2275 2276 /// AdjustInstrPostInstrSelection - This method should be implemented by 2277 /// targets that mark instructions with the 'hasPostISelHook' flag. These 2278 /// instructions must be adjusted after instruction selection by target hooks. 2279 /// e.g. To fill in optional defs for ARM 's' setting instructions. 2280 virtual void 2281 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 2282}; 2283 2284/// GetReturnInfo - Given an LLVM IR type and return type attributes, 2285/// compute the return value EVTs and flags, and optionally also 2286/// the offsets, if the return value is being lowered to memory. 2287void GetReturnInfo(Type* ReturnType, AttributeSet attr, 2288 SmallVectorImpl<ISD::OutputArg> &Outs, 2289 const TargetLowering &TLI); 2290 2291} // end llvm namespace 2292 2293#endif 2294