TargetLowering.h revision 561e8c80f58b71414270105c6794dc18a5d68d79
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CodeGen/SelectionDAGNodes.h" 26#include "llvm/CodeGen/RuntimeLibcalls.h" 27#include "llvm/ADT/APFloat.h" 28#include "llvm/ADT/STLExtras.h" 29#include <map> 30#include <vector> 31 32namespace llvm { 33 class Value; 34 class Function; 35 class TargetMachine; 36 class TargetData; 37 class TargetRegisterClass; 38 class SDNode; 39 class SDOperand; 40 class SelectionDAG; 41 class MachineBasicBlock; 42 class MachineInstr; 43 class VectorType; 44 class TargetSubtarget; 45 46//===----------------------------------------------------------------------===// 47/// TargetLowering - This class defines information used to lower LLVM code to 48/// legal SelectionDAG operators that the target instruction selector can accept 49/// natively. 50/// 51/// This class also defines callbacks that targets must implement to lower 52/// target-specific constructs to SelectionDAG operators. 53/// 54class TargetLowering { 55public: 56 /// LegalizeAction - This enum indicates whether operations are valid for a 57 /// target, and if not, what action should be used to make them valid. 58 enum LegalizeAction { 59 Legal, // The target natively supports this operation. 60 Promote, // This operation should be executed in a larger type. 61 Expand, // Try to expand this to other ops, otherwise use a libcall. 62 Custom // Use the LowerOperation hook to implement custom lowering. 63 }; 64 65 enum OutOfRangeShiftAmount { 66 Undefined, // Oversized shift amounts are undefined (default). 67 Mask, // Shift amounts are auto masked (anded) to value size. 68 Extend // Oversized shift pulls in zeros or sign bits. 69 }; 70 71 enum SetCCResultValue { 72 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 73 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 74 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 75 }; 76 77 enum SchedPreference { 78 SchedulingForLatency, // Scheduling for shortest total latency. 79 SchedulingForRegPressure // Scheduling for lowest register pressure. 80 }; 81 82 explicit TargetLowering(TargetMachine &TM); 83 virtual ~TargetLowering(); 84 85 TargetMachine &getTargetMachine() const { return TM; } 86 const TargetData *getTargetData() const { return TD; } 87 88 bool isLittleEndian() const { return IsLittleEndian; } 89 MVT::ValueType getPointerTy() const { return PointerTy; } 90 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 91 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 92 93 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 94 /// codegen. 95 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 96 97 /// isSelectExpensive - Return true if the select operation is expensive for 98 /// this target. 99 bool isSelectExpensive() const { return SelectIsExpensive; } 100 101 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 102 /// a sequence of several shifts, adds, and multiplies for this target. 103 bool isIntDivCheap() const { return IntDivIsCheap; } 104 105 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 106 /// srl/add/sra. 107 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 108 109 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 110 /// 111 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 112 113 /// getSetCCResultContents - For targets without boolean registers, this flag 114 /// returns information about the contents of the high-bits in the setcc 115 /// result register. 116 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 117 118 /// getSchedulingPreference - Return target scheduling preference. 119 SchedPreference getSchedulingPreference() const { 120 return SchedPreferenceInfo; 121 } 122 123 /// getRegClassFor - Return the register class that should be used for the 124 /// specified value type. This may only be called on legal types. 125 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 126 assert(!MVT::isExtendedVT(VT)); 127 TargetRegisterClass *RC = RegClassForVT[VT]; 128 assert(RC && "This value type is not natively supported!"); 129 return RC; 130 } 131 132 /// isTypeLegal - Return true if the target has native support for the 133 /// specified value type. This means that it has a register that directly 134 /// holds it without promotions or expansions. 135 bool isTypeLegal(MVT::ValueType VT) const { 136 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; 137 } 138 139 class ValueTypeActionImpl { 140 /// ValueTypeActions - This is a bitvector that contains two bits for each 141 /// value type, where the two bits correspond to the LegalizeAction enum. 142 /// This can be queried with "getTypeAction(VT)". 143 uint32_t ValueTypeActions[2]; 144 public: 145 ValueTypeActionImpl() { 146 ValueTypeActions[0] = ValueTypeActions[1] = 0; 147 } 148 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 149 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 150 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 151 } 152 153 LegalizeAction getTypeAction(MVT::ValueType VT) const { 154 if (MVT::isExtendedVT(VT)) { 155 if (MVT::isVector(VT)) return Expand; 156 if (MVT::isInteger(VT)) 157 // First promote to a power-of-two size, then expand if necessary. 158 return VT == MVT::RoundIntegerType(VT) ? Expand : Promote; 159 assert(0 && "Unsupported extended type!"); 160 } 161 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 162 } 163 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 164 assert(!MVT::isExtendedVT(VT)); 165 assert(unsigned(VT >> 4) < array_lengthof(ValueTypeActions)); 166 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 167 } 168 }; 169 170 const ValueTypeActionImpl &getValueTypeActions() const { 171 return ValueTypeActions; 172 } 173 174 /// getTypeAction - Return how we should legalize values of this type, either 175 /// it is already legal (return 'Legal') or we need to promote it to a larger 176 /// type (return 'Promote'), or we need to expand it into multiple registers 177 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 178 LegalizeAction getTypeAction(MVT::ValueType VT) const { 179 return ValueTypeActions.getTypeAction(VT); 180 } 181 182 /// getTypeToTransformTo - For types supported by the target, this is an 183 /// identity function. For types that must be promoted to larger types, this 184 /// returns the larger type to promote to. For integer types that are larger 185 /// than the largest integer register, this contains one step in the expansion 186 /// to get to the smaller register. For illegal floating point types, this 187 /// returns the integer type to transform to. 188 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 189 if (!MVT::isExtendedVT(VT)) { 190 MVT::ValueType NVT = TransformToType[VT]; 191 assert(getTypeAction(NVT) != Promote && 192 "Promote may not follow Expand or Promote"); 193 return NVT; 194 } 195 196 if (MVT::isVector(VT)) 197 return MVT::getVectorType(MVT::getVectorElementType(VT), 198 MVT::getVectorNumElements(VT) / 2); 199 if (MVT::isInteger(VT)) { 200 MVT::ValueType NVT = MVT::RoundIntegerType(VT); 201 if (NVT == VT) 202 // Size is a power of two - expand to half the size. 203 return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2); 204 else 205 // Promote to a power of two size, avoiding multi-step promotion. 206 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 207 } 208 assert(0 && "Unsupported extended type!"); 209 } 210 211 /// getTypeToExpandTo - For types supported by the target, this is an 212 /// identity function. For types that must be expanded (i.e. integer types 213 /// that are larger than the largest integer register or illegal floating 214 /// point types), this returns the largest legal type it will be expanded to. 215 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 216 assert(!MVT::isVector(VT)); 217 while (true) { 218 switch (getTypeAction(VT)) { 219 case Legal: 220 return VT; 221 case Expand: 222 VT = getTypeToTransformTo(VT); 223 break; 224 default: 225 assert(false && "Type is not legal nor is it to be expanded!"); 226 return VT; 227 } 228 } 229 return VT; 230 } 231 232 /// getVectorTypeBreakdown - Vector types are broken down into some number of 233 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 234 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 235 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 236 /// 237 /// This method returns the number of registers needed, and the VT for each 238 /// register. It also returns the VT and quantity of the intermediate values 239 /// before they are promoted/expanded. 240 /// 241 unsigned getVectorTypeBreakdown(MVT::ValueType VT, 242 MVT::ValueType &IntermediateVT, 243 unsigned &NumIntermediates, 244 MVT::ValueType &RegisterVT) const; 245 246 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 247 legal_fpimm_iterator legal_fpimm_begin() const { 248 return LegalFPImmediates.begin(); 249 } 250 legal_fpimm_iterator legal_fpimm_end() const { 251 return LegalFPImmediates.end(); 252 } 253 254 /// isShuffleMaskLegal - Targets can use this to indicate that they only 255 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 256 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 257 /// are assumed to be legal. 258 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 259 return true; 260 } 261 262 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 263 /// used by Targets can use this to indicate if there is a suitable 264 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 265 /// pool entry. 266 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 267 MVT::ValueType EVT, 268 SelectionDAG &DAG) const { 269 return false; 270 } 271 272 /// getOperationAction - Return how this operation should be treated: either 273 /// it is legal, needs to be promoted to a larger size, needs to be 274 /// expanded to some other code sequence, or the target has a custom expander 275 /// for it. 276 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 277 if (MVT::isExtendedVT(VT)) return Expand; 278 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 279 } 280 281 /// isOperationLegal - Return true if the specified operation is legal on this 282 /// target. 283 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 284 return getOperationAction(Op, VT) == Legal || 285 getOperationAction(Op, VT) == Custom; 286 } 287 288 /// getLoadXAction - Return how this load with extension should be treated: 289 /// either it is legal, needs to be promoted to a larger size, needs to be 290 /// expanded to some other code sequence, or the target has a custom expander 291 /// for it. 292 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 293 if (MVT::isExtendedVT(VT)) return getTypeAction(VT); 294 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3); 295 } 296 297 /// isLoadXLegal - Return true if the specified load with extension is legal 298 /// on this target. 299 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 300 return getLoadXAction(LType, VT) == Legal || 301 getLoadXAction(LType, VT) == Custom; 302 } 303 304 /// getTruncStoreAction - Return how this store with truncation should be 305 /// treated: either it is legal, needs to be promoted to a larger size, needs 306 /// to be expanded to some other code sequence, or the target has a custom 307 /// expander for it. 308 LegalizeAction getTruncStoreAction(MVT::ValueType ValVT, 309 MVT::ValueType MemVT) const { 310 assert(ValVT < array_lengthof(TruncStoreActions) && 311 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!"); 312 return (LegalizeAction)((TruncStoreActions[ValVT] >> (2*MemVT)) & 3); 313 } 314 315 /// isTruncStoreLegal - Return true if the specified store with truncation is 316 /// legal on this target. 317 bool isTruncStoreLegal(MVT::ValueType ValVT, MVT::ValueType MemVT) const { 318 return getTruncStoreAction(ValVT, MemVT) == Legal || 319 getTruncStoreAction(ValVT, MemVT) == Custom; 320 } 321 322 /// getIndexedLoadAction - Return how the indexed load should be treated: 323 /// either it is legal, needs to be promoted to a larger size, needs to be 324 /// expanded to some other code sequence, or the target has a custom expander 325 /// for it. 326 LegalizeAction 327 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 328 if (MVT::isExtendedVT(VT)) return getTypeAction(VT); 329 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3); 330 } 331 332 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 333 /// on this target. 334 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 335 return getIndexedLoadAction(IdxMode, VT) == Legal || 336 getIndexedLoadAction(IdxMode, VT) == Custom; 337 } 338 339 /// getIndexedStoreAction - Return how the indexed store should be treated: 340 /// either it is legal, needs to be promoted to a larger size, needs to be 341 /// expanded to some other code sequence, or the target has a custom expander 342 /// for it. 343 LegalizeAction 344 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 345 if (MVT::isExtendedVT(VT)) return getTypeAction(VT); 346 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3); 347 } 348 349 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 350 /// on this target. 351 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 352 return getIndexedStoreAction(IdxMode, VT) == Legal || 353 getIndexedStoreAction(IdxMode, VT) == Custom; 354 } 355 356 /// getConvertAction - Return how the conversion should be treated: 357 /// either it is legal, needs to be promoted to a larger size, needs to be 358 /// expanded to some other code sequence, or the target has a custom expander 359 /// for it. 360 LegalizeAction 361 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 362 assert(FromVT < array_lengthof(ConvertActions) && 363 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!"); 364 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3); 365 } 366 367 /// isConvertLegal - Return true if the specified conversion is legal 368 /// on this target. 369 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const { 370 return getConvertAction(FromVT, ToVT) == Legal || 371 getConvertAction(FromVT, ToVT) == Custom; 372 } 373 374 /// getTypeToPromoteTo - If the action for this operation is to promote, this 375 /// method returns the ValueType to promote to. 376 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 377 assert(getOperationAction(Op, VT) == Promote && 378 "This operation isn't promoted!"); 379 380 // See if this has an explicit type specified. 381 std::map<std::pair<unsigned, MVT::ValueType>, 382 MVT::ValueType>::const_iterator PTTI = 383 PromoteToType.find(std::make_pair(Op, VT)); 384 if (PTTI != PromoteToType.end()) return PTTI->second; 385 386 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 387 "Cannot autopromote this type, add it with AddPromotedToType."); 388 389 MVT::ValueType NVT = VT; 390 do { 391 NVT = (MVT::ValueType)(NVT+1); 392 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 393 "Didn't find type to promote to!"); 394 } while (!isTypeLegal(NVT) || 395 getOperationAction(Op, NVT) == Promote); 396 return NVT; 397 } 398 399 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 400 /// This is fixed by the LLVM operations except for the pointer size. If 401 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 402 /// counterpart (e.g. structs), otherwise it will assert. 403 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const { 404 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown); 405 return VT == MVT::iPTR ? PointerTy : VT; 406 } 407 408 /// getRegisterType - Return the type of registers that this ValueType will 409 /// eventually require. 410 MVT::ValueType getRegisterType(MVT::ValueType VT) const { 411 if (!MVT::isExtendedVT(VT)) 412 return RegisterTypeForVT[VT]; 413 if (MVT::isVector(VT)) { 414 MVT::ValueType VT1, RegisterVT; 415 unsigned NumIntermediates; 416 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 417 return RegisterVT; 418 } 419 assert(0 && "Unsupported extended type!"); 420 } 421 422 /// getNumRegisters - Return the number of registers that this ValueType will 423 /// eventually require. This is one for any types promoted to live in larger 424 /// registers, but may be more than one for types (like i64) that are split 425 /// into pieces. 426 unsigned getNumRegisters(MVT::ValueType VT) const { 427 if (!MVT::isExtendedVT(VT)) 428 return NumRegistersForVT[VT]; 429 if (MVT::isVector(VT)) { 430 MVT::ValueType VT1, VT2; 431 unsigned NumIntermediates; 432 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 433 } 434 assert(0 && "Unsupported extended type!"); 435 } 436 437 /// hasTargetDAGCombine - If true, the target has custom DAG combine 438 /// transformations that it can perform for the specified node. 439 bool hasTargetDAGCombine(ISD::NodeType NT) const { 440 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 441 } 442 443 /// This function returns the maximum number of store operations permitted 444 /// to replace a call to llvm.memset. The value is set by the target at the 445 /// performance threshold for such a replacement. 446 /// @brief Get maximum # of store operations permitted for llvm.memset 447 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 448 449 /// This function returns the maximum number of store operations permitted 450 /// to replace a call to llvm.memcpy. The value is set by the target at the 451 /// performance threshold for such a replacement. 452 /// @brief Get maximum # of store operations permitted for llvm.memcpy 453 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 454 455 /// This function returns the maximum number of store operations permitted 456 /// to replace a call to llvm.memmove. The value is set by the target at the 457 /// performance threshold for such a replacement. 458 /// @brief Get maximum # of store operations permitted for llvm.memmove 459 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 460 461 /// This function returns true if the target allows unaligned memory accesses. 462 /// This is used, for example, in situations where an array copy/move/set is 463 /// converted to a sequence of store operations. It's use helps to ensure that 464 /// such replacements don't generate code that causes an alignment error 465 /// (trap) on the target machine. 466 /// @brief Determine if the target supports unaligned memory accesses. 467 bool allowsUnalignedMemoryAccesses() const { 468 return allowUnalignedMemoryAccesses; 469 } 470 471 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 472 /// to implement llvm.setjmp. 473 bool usesUnderscoreSetJmp() const { 474 return UseUnderscoreSetJmp; 475 } 476 477 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 478 /// to implement llvm.longjmp. 479 bool usesUnderscoreLongJmp() const { 480 return UseUnderscoreLongJmp; 481 } 482 483 /// getStackPointerRegisterToSaveRestore - If a physical register, this 484 /// specifies the register that llvm.savestack/llvm.restorestack should save 485 /// and restore. 486 unsigned getStackPointerRegisterToSaveRestore() const { 487 return StackPointerRegisterToSaveRestore; 488 } 489 490 /// getExceptionAddressRegister - If a physical register, this returns 491 /// the register that receives the exception address on entry to a landing 492 /// pad. 493 unsigned getExceptionAddressRegister() const { 494 return ExceptionPointerRegister; 495 } 496 497 /// getExceptionSelectorRegister - If a physical register, this returns 498 /// the register that receives the exception typeid on entry to a landing 499 /// pad. 500 unsigned getExceptionSelectorRegister() const { 501 return ExceptionSelectorRegister; 502 } 503 504 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 505 /// set, the default is 200) 506 unsigned getJumpBufSize() const { 507 return JumpBufSize; 508 } 509 510 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 511 /// (if never set, the default is 0) 512 unsigned getJumpBufAlignment() const { 513 return JumpBufAlignment; 514 } 515 516 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 517 /// limit. Any block whose size is greater should not be predicated. 518 virtual unsigned getIfCvtBlockSizeLimit() const { 519 return IfCvtBlockSizeLimit; 520 } 521 522 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 523 /// block to be considered for duplication. Any block whose size is greater 524 /// should not be duplicated to facilitate its predication. 525 virtual unsigned getIfCvtDupBlockSizeLimit() const { 526 return IfCvtDupBlockSizeLimit; 527 } 528 529 /// getPreIndexedAddressParts - returns true by value, base pointer and 530 /// offset pointer and addressing mode by reference if the node's address 531 /// can be legally represented as pre-indexed load / store address. 532 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 533 SDOperand &Offset, 534 ISD::MemIndexedMode &AM, 535 SelectionDAG &DAG) { 536 return false; 537 } 538 539 /// getPostIndexedAddressParts - returns true by value, base pointer and 540 /// offset pointer and addressing mode by reference if this node can be 541 /// combined with a load / store to form a post-indexed load / store. 542 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 543 SDOperand &Base, SDOperand &Offset, 544 ISD::MemIndexedMode &AM, 545 SelectionDAG &DAG) { 546 return false; 547 } 548 549 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 550 /// jumptable. 551 virtual SDOperand getPICJumpTableRelocBase(SDOperand Table, 552 SelectionDAG &DAG) const; 553 554 //===--------------------------------------------------------------------===// 555 // TargetLowering Optimization Methods 556 // 557 558 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 559 /// SDOperands for returning information from TargetLowering to its clients 560 /// that want to combine 561 struct TargetLoweringOpt { 562 SelectionDAG &DAG; 563 bool AfterLegalize; 564 SDOperand Old; 565 SDOperand New; 566 567 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool afterLegalize) 568 : DAG(InDAG), AfterLegalize(afterLegalize) {} 569 570 bool CombineTo(SDOperand O, SDOperand N) { 571 Old = O; 572 New = N; 573 return true; 574 } 575 576 /// ShrinkDemandedConstant - Check to see if the specified operand of the 577 /// specified instruction is a constant integer. If so, check to see if 578 /// there are any bits set in the constant that are not demanded. If so, 579 /// shrink the constant and return true. 580 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 581 }; 582 583 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 584 /// DemandedMask bits of the result of Op are ever used downstream. If we can 585 /// use this information to simplify Op, create a new simplified DAG node and 586 /// return true, returning the original and new nodes in Old and New. 587 /// Otherwise, analyze the expression and return a mask of KnownOne and 588 /// KnownZero bits for the expression (used to simplify the caller). 589 /// The KnownZero/One bits may only be accurate for those bits in the 590 /// DemandedMask. 591 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 592 uint64_t &KnownZero, uint64_t &KnownOne, 593 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 594 595 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 596 /// Mask are known to be either zero or one and return them in the 597 /// KnownZero/KnownOne bitsets. 598 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 599 uint64_t Mask, 600 uint64_t &KnownZero, 601 uint64_t &KnownOne, 602 const SelectionDAG &DAG, 603 unsigned Depth = 0) const; 604 605 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 606 /// targets that want to expose additional information about sign bits to the 607 /// DAG Combiner. 608 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 609 unsigned Depth = 0) const; 610 611 struct DAGCombinerInfo { 612 void *DC; // The DAG Combiner object. 613 bool BeforeLegalize; 614 bool CalledByLegalizer; 615 public: 616 SelectionDAG &DAG; 617 618 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 619 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 620 621 bool isBeforeLegalize() const { return BeforeLegalize; } 622 bool isCalledByLegalizer() const { return CalledByLegalizer; } 623 624 void AddToWorklist(SDNode *N); 625 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 626 SDOperand CombineTo(SDNode *N, SDOperand Res); 627 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 628 }; 629 630 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 631 /// and cc. If it is unable to simplify it, return a null SDOperand. 632 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 633 ISD::CondCode Cond, bool foldBooleans, 634 DAGCombinerInfo &DCI) const; 635 636 /// PerformDAGCombine - This method will be invoked for all target nodes and 637 /// for any target-independent nodes that the target has registered with 638 /// invoke it for. 639 /// 640 /// The semantics are as follows: 641 /// Return Value: 642 /// SDOperand.Val == 0 - No change was made 643 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 644 /// otherwise - N should be replaced by the returned Operand. 645 /// 646 /// In addition, methods provided by DAGCombinerInfo may be used to perform 647 /// more complex transformations. 648 /// 649 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 650 651 //===--------------------------------------------------------------------===// 652 // TargetLowering Configuration Methods - These methods should be invoked by 653 // the derived class constructor to configure this object for the target. 654 // 655 656protected: 657 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 658 /// GOT for PC-relative code. 659 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 660 661 /// setShiftAmountType - Describe the type that should be used for shift 662 /// amounts. This type defaults to the pointer type. 663 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 664 665 /// setSetCCResultType - Describe the type that shoudl be used as the result 666 /// of a setcc operation. This defaults to the pointer type. 667 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 668 669 /// setSetCCResultContents - Specify how the target extends the result of a 670 /// setcc operation in a register. 671 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 672 673 /// setSchedulingPreference - Specify the target scheduling preference. 674 void setSchedulingPreference(SchedPreference Pref) { 675 SchedPreferenceInfo = Pref; 676 } 677 678 /// setShiftAmountFlavor - Describe how the target handles out of range shift 679 /// amounts. 680 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 681 ShiftAmtHandling = OORSA; 682 } 683 684 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 685 /// use _setjmp to implement llvm.setjmp or the non _ version. 686 /// Defaults to false. 687 void setUseUnderscoreSetJmp(bool Val) { 688 UseUnderscoreSetJmp = Val; 689 } 690 691 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 692 /// use _longjmp to implement llvm.longjmp or the non _ version. 693 /// Defaults to false. 694 void setUseUnderscoreLongJmp(bool Val) { 695 UseUnderscoreLongJmp = Val; 696 } 697 698 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 699 /// specifies the register that llvm.savestack/llvm.restorestack should save 700 /// and restore. 701 void setStackPointerRegisterToSaveRestore(unsigned R) { 702 StackPointerRegisterToSaveRestore = R; 703 } 704 705 /// setExceptionPointerRegister - If set to a physical register, this sets 706 /// the register that receives the exception address on entry to a landing 707 /// pad. 708 void setExceptionPointerRegister(unsigned R) { 709 ExceptionPointerRegister = R; 710 } 711 712 /// setExceptionSelectorRegister - If set to a physical register, this sets 713 /// the register that receives the exception typeid on entry to a landing 714 /// pad. 715 void setExceptionSelectorRegister(unsigned R) { 716 ExceptionSelectorRegister = R; 717 } 718 719 /// SelectIsExpensive - Tells the code generator not to expand operations 720 /// into sequences that use the select operations if possible. 721 void setSelectIsExpensive() { SelectIsExpensive = true; } 722 723 /// setIntDivIsCheap - Tells the code generator that integer divide is 724 /// expensive, and if possible, should be replaced by an alternate sequence 725 /// of instructions not containing an integer divide. 726 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 727 728 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 729 /// srl/add/sra for a signed divide by power of two, and let the target handle 730 /// it. 731 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 732 733 /// addRegisterClass - Add the specified register class as an available 734 /// regclass for the specified value type. This indicates the selector can 735 /// handle values of that class natively. 736 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 737 assert(!MVT::isExtendedVT(VT)); 738 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 739 RegClassForVT[VT] = RC; 740 } 741 742 /// computeRegisterProperties - Once all of the register classes are added, 743 /// this allows us to compute derived properties we expose. 744 void computeRegisterProperties(); 745 746 /// setOperationAction - Indicate that the specified operation does not work 747 /// with the specified type and indicate what to do about it. 748 void setOperationAction(unsigned Op, MVT::ValueType VT, 749 LegalizeAction Action) { 750 assert(VT < sizeof(OpActions[0])*4 && Op < array_lengthof(OpActions) && 751 "Table isn't big enough!"); 752 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 753 OpActions[Op] |= (uint64_t)Action << VT*2; 754 } 755 756 /// setLoadXAction - Indicate that the specified load with extension does not 757 /// work with the with specified type and indicate what to do about it. 758 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 759 LegalizeAction Action) { 760 assert(VT < sizeof(LoadXActions[0])*4 && 761 ExtType < array_lengthof(LoadXActions) && 762 "Table isn't big enough!"); 763 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 764 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 765 } 766 767 /// setTruncStoreAction - Indicate that the specified truncating store does 768 /// not work with the with specified type and indicate what to do about it. 769 void setTruncStoreAction(MVT::ValueType ValVT, MVT::ValueType MemVT, 770 LegalizeAction Action) { 771 assert(ValVT < array_lengthof(TruncStoreActions) && 772 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!"); 773 TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2); 774 TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2; 775 } 776 777 /// setIndexedLoadAction - Indicate that the specified indexed load does or 778 /// does not work with the with specified type and indicate what to do abort 779 /// it. NOTE: All indexed mode loads are initialized to Expand in 780 /// TargetLowering.cpp 781 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 782 LegalizeAction Action) { 783 assert(VT < sizeof(IndexedModeActions[0])*4 && IdxMode < 784 array_lengthof(IndexedModeActions[0]) && 785 "Table isn't big enough!"); 786 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 787 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 788 } 789 790 /// setIndexedStoreAction - Indicate that the specified indexed store does or 791 /// does not work with the with specified type and indicate what to do about 792 /// it. NOTE: All indexed mode stores are initialized to Expand in 793 /// TargetLowering.cpp 794 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 795 LegalizeAction Action) { 796 assert(VT < sizeof(IndexedModeActions[1][0])*4 && 797 IdxMode < array_lengthof(IndexedModeActions[1]) && 798 "Table isn't big enough!"); 799 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 800 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 801 } 802 803 /// setConvertAction - Indicate that the specified conversion does or does 804 /// not work with the with specified type and indicate what to do about it. 805 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT, 806 LegalizeAction Action) { 807 assert(FromVT < array_lengthof(ConvertActions) && 808 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!"); 809 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2); 810 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2; 811 } 812 813 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 814 /// promotion code defaults to trying a larger integer/fp until it can find 815 /// one that works. If that default is insufficient, this method can be used 816 /// by the target to override the default. 817 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 818 MVT::ValueType DestVT) { 819 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 820 } 821 822 /// addLegalFPImmediate - Indicate that this target can instruction select 823 /// the specified FP immediate natively. 824 void addLegalFPImmediate(const APFloat& Imm) { 825 LegalFPImmediates.push_back(Imm); 826 } 827 828 /// setTargetDAGCombine - Targets should invoke this method for each target 829 /// independent node that they want to provide a custom DAG combiner for by 830 /// implementing the PerformDAGCombine virtual method. 831 void setTargetDAGCombine(ISD::NodeType NT) { 832 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 833 } 834 835 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 836 /// bytes); default is 200 837 void setJumpBufSize(unsigned Size) { 838 JumpBufSize = Size; 839 } 840 841 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 842 /// alignment (in bytes); default is 0 843 void setJumpBufAlignment(unsigned Align) { 844 JumpBufAlignment = Align; 845 } 846 847 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 848 /// limit (in number of instructions); default is 2. 849 void setIfCvtBlockSizeLimit(unsigned Limit) { 850 IfCvtBlockSizeLimit = Limit; 851 } 852 853 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 854 /// of instructions) to be considered for code duplication during 855 /// if-conversion; default is 2. 856 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 857 IfCvtDupBlockSizeLimit = Limit; 858 } 859 860public: 861 862 virtual const TargetSubtarget *getSubtarget() { 863 assert(0 && "Not Implemented"); 864 return NULL; // this is here to silence compiler errors 865 } 866 //===--------------------------------------------------------------------===// 867 // Lowering methods - These methods must be implemented by targets so that 868 // the SelectionDAGLowering code knows how to lower these. 869 // 870 871 /// LowerArguments - This hook must be implemented to indicate how we should 872 /// lower the arguments for the specified function, into the specified DAG. 873 virtual std::vector<SDOperand> 874 LowerArguments(Function &F, SelectionDAG &DAG); 875 876 /// LowerCallTo - This hook lowers an abstract call to a function into an 877 /// actual call. This returns a pair of operands. The first element is the 878 /// return value for the function (if RetTy is not VoidTy). The second 879 /// element is the outgoing token chain. 880 struct ArgListEntry { 881 SDOperand Node; 882 const Type* Ty; 883 bool isSExt; 884 bool isZExt; 885 bool isInReg; 886 bool isSRet; 887 bool isNest; 888 bool isByVal; 889 890 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 891 isSRet(false), isNest(false), isByVal(false) { } 892 }; 893 typedef std::vector<ArgListEntry> ArgListTy; 894 virtual std::pair<SDOperand, SDOperand> 895 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 896 bool isVarArg, unsigned CallingConv, bool isTailCall, 897 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 898 899 900 virtual SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG); 901 virtual SDOperand LowerMEMCPYCall(SDOperand Chain, SDOperand Dest, 902 SDOperand Source, SDOperand Count, 903 SelectionDAG &DAG); 904 virtual SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest, 905 SDOperand Source, unsigned Size, 906 unsigned Align, SelectionDAG &DAG) { 907 assert(0 && "Not Implemented"); 908 return SDOperand(); // this is here to silence compiler errors 909 } 910 911 912 /// LowerOperation - This callback is invoked for operations that are 913 /// unsupported by the target, which are registered to use 'custom' lowering, 914 /// and whose defined values are all legal. 915 /// If the target has no operations that require custom lowering, it need not 916 /// implement this. The default implementation of this aborts. 917 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 918 919 /// ExpandOperationResult - This callback is invoked for operations that are 920 /// unsupported by the target, which are registered to use 'custom' lowering, 921 /// and whose result type needs to be expanded. This must return a node whose 922 /// results precisely match the results of the input node. This typically 923 /// involves a MERGE_VALUES node and/or BUILD_PAIR. 924 /// 925 /// If the target has no operations that require custom lowering, it need not 926 /// implement this. The default implementation of this aborts. 927 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { 928 assert(0 && "ExpandOperationResult not implemented for this target!"); 929 return 0; 930 } 931 932 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 933 /// tail call optimization. Targets which want to do tail call optimization 934 /// should override this function. 935 virtual bool IsEligibleForTailCallOptimization(SDOperand Call, 936 SDOperand Ret, 937 SelectionDAG &DAG) const { 938 return false; 939 } 940 941 /// CustomPromoteOperation - This callback is invoked for operations that are 942 /// unsupported by the target, are registered to use 'custom' lowering, and 943 /// whose type needs to be promoted. 944 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 945 946 /// getTargetNodeName() - This method returns the name of a target specific 947 /// DAG node. 948 virtual const char *getTargetNodeName(unsigned Opcode) const; 949 950 //===--------------------------------------------------------------------===// 951 // Inline Asm Support hooks 952 // 953 954 enum ConstraintType { 955 C_Register, // Constraint represents a single register. 956 C_RegisterClass, // Constraint represents one or more registers. 957 C_Memory, // Memory constraint. 958 C_Other, // Something else. 959 C_Unknown // Unsupported constraint. 960 }; 961 962 /// getConstraintType - Given a constraint, return the type of constraint it 963 /// is for this target. 964 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 965 966 967 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 968 /// return a list of registers that can be used to satisfy the constraint. 969 /// This should only be used for C_RegisterClass constraints. 970 virtual std::vector<unsigned> 971 getRegClassForInlineAsmConstraint(const std::string &Constraint, 972 MVT::ValueType VT) const; 973 974 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 975 /// {edx}), return the register number and the register class for the 976 /// register. 977 /// 978 /// Given a register class constraint, like 'r', if this corresponds directly 979 /// to an LLVM register class, return a register of 0 and the register class 980 /// pointer. 981 /// 982 /// This should only be used for C_Register constraints. On error, 983 /// this returns a register number of 0 and a null register class pointer.. 984 virtual std::pair<unsigned, const TargetRegisterClass*> 985 getRegForInlineAsmConstraint(const std::string &Constraint, 986 MVT::ValueType VT) const; 987 988 989 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 990 /// vector. If it is invalid, don't add anything to Ops. 991 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter, 992 std::vector<SDOperand> &Ops, 993 SelectionDAG &DAG); 994 995 //===--------------------------------------------------------------------===// 996 // Scheduler hooks 997 // 998 999 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 1000 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1001 // instructions are special in various ways, which require special support to 1002 // insert. The specified MachineInstr is created but not inserted into any 1003 // basic blocks, and the scheduler passes ownership of it to this method. 1004 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 1005 MachineBasicBlock *MBB); 1006 1007 //===--------------------------------------------------------------------===// 1008 // Addressing mode description hooks (used by LSR etc). 1009 // 1010 1011 /// AddrMode - This represents an addressing mode of: 1012 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1013 /// If BaseGV is null, there is no BaseGV. 1014 /// If BaseOffs is zero, there is no base offset. 1015 /// If HasBaseReg is false, there is no base register. 1016 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1017 /// no scale. 1018 /// 1019 struct AddrMode { 1020 GlobalValue *BaseGV; 1021 int64_t BaseOffs; 1022 bool HasBaseReg; 1023 int64_t Scale; 1024 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1025 }; 1026 1027 /// isLegalAddressingMode - Return true if the addressing mode represented by 1028 /// AM is legal for this target, for a load/store of the specified type. 1029 /// TODO: Handle pre/postinc as well. 1030 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1031 1032 /// isTruncateFree - Return true if it's free to truncate a value of 1033 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1034 /// register EAX to i16 by referencing its sub-register AX. 1035 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1036 return false; 1037 } 1038 1039 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const { 1040 return false; 1041 } 1042 1043 //===--------------------------------------------------------------------===// 1044 // Div utility functions 1045 // 1046 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 1047 std::vector<SDNode*>* Created) const; 1048 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 1049 std::vector<SDNode*>* Created) const; 1050 1051 1052 //===--------------------------------------------------------------------===// 1053 // Runtime Library hooks 1054 // 1055 1056 /// setLibcallName - Rename the default libcall routine name for the specified 1057 /// libcall. 1058 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1059 LibcallRoutineNames[Call] = Name; 1060 } 1061 1062 /// getLibcallName - Get the libcall routine name for the specified libcall. 1063 /// 1064 const char *getLibcallName(RTLIB::Libcall Call) const { 1065 return LibcallRoutineNames[Call]; 1066 } 1067 1068 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1069 /// result of the comparison libcall against zero. 1070 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1071 CmpLibcallCCs[Call] = CC; 1072 } 1073 1074 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1075 /// the comparison libcall against zero. 1076 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1077 return CmpLibcallCCs[Call]; 1078 } 1079 1080private: 1081 TargetMachine &TM; 1082 const TargetData *TD; 1083 1084 /// IsLittleEndian - True if this is a little endian target. 1085 /// 1086 bool IsLittleEndian; 1087 1088 /// PointerTy - The type to use for pointers, usually i32 or i64. 1089 /// 1090 MVT::ValueType PointerTy; 1091 1092 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1093 /// 1094 bool UsesGlobalOffsetTable; 1095 1096 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1097 /// PointerTy is. 1098 MVT::ValueType ShiftAmountTy; 1099 1100 OutOfRangeShiftAmount ShiftAmtHandling; 1101 1102 /// SelectIsExpensive - Tells the code generator not to expand operations 1103 /// into sequences that use the select operations if possible. 1104 bool SelectIsExpensive; 1105 1106 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1107 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1108 /// a real cost model is in place. If we ever optimize for size, this will be 1109 /// set to true unconditionally. 1110 bool IntDivIsCheap; 1111 1112 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1113 /// srl/add/sra for a signed divide by power of two, and let the target handle 1114 /// it. 1115 bool Pow2DivIsCheap; 1116 1117 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 1118 /// PointerTy. 1119 MVT::ValueType SetCCResultTy; 1120 1121 /// SetCCResultContents - Information about the contents of the high-bits in 1122 /// the result of a setcc comparison operation. 1123 SetCCResultValue SetCCResultContents; 1124 1125 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1126 /// total cycles or lowest register usage. 1127 SchedPreference SchedPreferenceInfo; 1128 1129 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1130 /// llvm.setjmp. Defaults to false. 1131 bool UseUnderscoreSetJmp; 1132 1133 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1134 /// llvm.longjmp. Defaults to false. 1135 bool UseUnderscoreLongJmp; 1136 1137 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1138 unsigned JumpBufSize; 1139 1140 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1141 /// buffers 1142 unsigned JumpBufAlignment; 1143 1144 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1145 /// if-converted. 1146 unsigned IfCvtBlockSizeLimit; 1147 1148 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1149 /// duplicated during if-conversion. 1150 unsigned IfCvtDupBlockSizeLimit; 1151 1152 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1153 /// specifies the register that llvm.savestack/llvm.restorestack should save 1154 /// and restore. 1155 unsigned StackPointerRegisterToSaveRestore; 1156 1157 /// ExceptionPointerRegister - If set to a physical register, this specifies 1158 /// the register that receives the exception address on entry to a landing 1159 /// pad. 1160 unsigned ExceptionPointerRegister; 1161 1162 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1163 /// the register that receives the exception typeid on entry to a landing 1164 /// pad. 1165 unsigned ExceptionSelectorRegister; 1166 1167 /// RegClassForVT - This indicates the default register class to use for 1168 /// each ValueType the target supports natively. 1169 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1170 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1171 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1172 1173 /// TransformToType - For any value types we are promoting or expanding, this 1174 /// contains the value type that we are changing to. For Expanded types, this 1175 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1176 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1177 /// by the system, this holds the same type (e.g. i32 -> i32). 1178 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1179 1180 /// OpActions - For each operation and each value type, keep a LegalizeAction 1181 /// that indicates how instruction selection should deal with the operation. 1182 /// Most operations are Legal (aka, supported natively by the target), but 1183 /// operations that are not should be described. Note that operations on 1184 /// non-legal value types are not described here. 1185 uint64_t OpActions[156]; 1186 1187 /// LoadXActions - For each load of load extension type and each value type, 1188 /// keep a LegalizeAction that indicates how instruction selection should deal 1189 /// with the load. 1190 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1191 1192 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1193 /// indicates how instruction selection should deal with the store. 1194 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1195 1196 /// IndexedModeActions - For each indexed mode and each value type, keep a 1197 /// pair of LegalizeAction that indicates how instruction selection should 1198 /// deal with the load / store. 1199 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1200 1201 /// ConvertActions - For each conversion from source type to destination type, 1202 /// keep a LegalizeAction that indicates how instruction selection should 1203 /// deal with the conversion. 1204 /// Currently, this is used only for floating->floating conversions 1205 /// (FP_EXTEND and FP_ROUND). 1206 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1207 1208 ValueTypeActionImpl ValueTypeActions; 1209 1210 std::vector<APFloat> LegalFPImmediates; 1211 1212 std::vector<std::pair<MVT::ValueType, 1213 TargetRegisterClass*> > AvailableRegClasses; 1214 1215 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1216 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1217 /// which sets a bit in this array. 1218 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1219 1220 /// PromoteToType - For operations that must be promoted to a specific type, 1221 /// this holds the destination type. This map should be sparse, so don't hold 1222 /// it as an array. 1223 /// 1224 /// Targets add entries to this map with AddPromotedToType(..), clients access 1225 /// this with getTypeToPromoteTo(..). 1226 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1227 1228 /// LibcallRoutineNames - Stores the name each libcall. 1229 /// 1230 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1231 1232 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1233 /// of each of the comparison libcall against zero. 1234 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1235 1236protected: 1237 /// When lowering %llvm.memset this field specifies the maximum number of 1238 /// store operations that may be substituted for the call to memset. Targets 1239 /// must set this value based on the cost threshold for that target. Targets 1240 /// should assume that the memset will be done using as many of the largest 1241 /// store operations first, followed by smaller ones, if necessary, per 1242 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1243 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1244 /// store. This only applies to setting a constant array of a constant size. 1245 /// @brief Specify maximum number of store instructions per memset call. 1246 unsigned maxStoresPerMemset; 1247 1248 /// When lowering %llvm.memcpy this field specifies the maximum number of 1249 /// store operations that may be substituted for a call to memcpy. Targets 1250 /// must set this value based on the cost threshold for that target. Targets 1251 /// should assume that the memcpy will be done using as many of the largest 1252 /// store operations first, followed by smaller ones, if necessary, per 1253 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1254 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1255 /// and one 1-byte store. This only applies to copying a constant array of 1256 /// constant size. 1257 /// @brief Specify maximum bytes of store instructions per memcpy call. 1258 unsigned maxStoresPerMemcpy; 1259 1260 /// When lowering %llvm.memmove this field specifies the maximum number of 1261 /// store instructions that may be substituted for a call to memmove. Targets 1262 /// must set this value based on the cost threshold for that target. Targets 1263 /// should assume that the memmove will be done using as many of the largest 1264 /// store operations first, followed by smaller ones, if necessary, per 1265 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1266 /// with 8-bit alignment would result in nine 1-byte stores. This only 1267 /// applies to copying a constant array of constant size. 1268 /// @brief Specify maximum bytes of store instructions per memmove call. 1269 unsigned maxStoresPerMemmove; 1270 1271 /// This field specifies whether the target machine permits unaligned memory 1272 /// accesses. This is used, for example, to determine the size of store 1273 /// operations when copying small arrays and other similar tasks. 1274 /// @brief Indicate whether the target permits unaligned memory accesses. 1275 bool allowUnalignedMemoryAccesses; 1276}; 1277} // end llvm namespace 1278 1279#endif 1280