TargetLowering.h revision 74a4533a4290b7c6f1fe04a30ca13ec25c529e0a
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/ADT/DenseMap.h" 26#include "llvm/CodeGen/DAGCombine.h" 27#include "llvm/CodeGen/RuntimeLibcalls.h" 28#include "llvm/CodeGen/SelectionDAGNodes.h" 29#include "llvm/IR/Attributes.h" 30#include "llvm/IR/CallingConv.h" 31#include "llvm/IR/InlineAsm.h" 32#include "llvm/Support/CallSite.h" 33#include "llvm/Support/DebugLoc.h" 34#include "llvm/Target/TargetCallingConv.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class CallInst; 42 class CCState; 43 class FastISel; 44 class FunctionLoweringInfo; 45 class ImmutableCallSite; 46 class IntrinsicInst; 47 class MachineBasicBlock; 48 class MachineFunction; 49 class MachineInstr; 50 class MachineJumpTableInfo; 51 class MCContext; 52 class MCExpr; 53 template<typename T> class SmallVectorImpl; 54 class DataLayout; 55 class TargetRegisterClass; 56 class TargetLibraryInfo; 57 class TargetLoweringObjectFile; 58 class Value; 59 60 namespace Sched { 61 enum Preference { 62 None, // No preference 63 Source, // Follow source order. 64 RegPressure, // Scheduling for lowest register pressure. 65 Hybrid, // Scheduling for both latency and register pressure. 66 ILP, // Scheduling for ILP in low register pressure mode. 67 VLIW // Scheduling for VLIW targets. 68 }; 69 } 70 71/// TargetLoweringBase - This base class for TargetLowering contains the 72/// SelectionDAG-independent parts that can be used from the rest of CodeGen. 73class TargetLoweringBase { 74 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 75 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 76 77public: 78 /// LegalizeAction - This enum indicates whether operations are valid for a 79 /// target, and if not, what action should be used to make them valid. 80 enum LegalizeAction { 81 Legal, // The target natively supports this operation. 82 Promote, // This operation should be executed in a larger type. 83 Expand, // Try to expand this to other ops, otherwise use a libcall. 84 Custom // Use the LowerOperation hook to implement custom lowering. 85 }; 86 87 /// LegalizeTypeAction - This enum indicates whether a types are legal for a 88 /// target, and if not, what action should be used to make them valid. 89 enum LegalizeTypeAction { 90 TypeLegal, // The target natively supports this type. 91 TypePromoteInteger, // Replace this integer with a larger one. 92 TypeExpandInteger, // Split this integer into two of half the size. 93 TypeSoftenFloat, // Convert this float to a same size integer type. 94 TypeExpandFloat, // Split this float into two of half the size. 95 TypeScalarizeVector, // Replace this one-element vector with its element. 96 TypeSplitVector, // Split this vector into two of half the size. 97 TypeWidenVector // This vector should be widened into a larger vector. 98 }; 99 100 /// LegalizeKind holds the legalization kind that needs to happen to EVT 101 /// in order to type-legalize it. 102 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; 103 104 enum BooleanContent { // How the target represents true/false values. 105 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 106 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 107 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 108 }; 109 110 enum SelectSupportKind { 111 ScalarValSelect, // The target supports scalar selects (ex: cmov). 112 ScalarCondVectorVal, // The target supports selects with a scalar condition 113 // and vector values (ex: cmov). 114 VectorMaskSelect // The target supports vector selects with a vector 115 // mask (ex: x86 blends). 116 }; 117 118 static ISD::NodeType getExtendForContent(BooleanContent Content) { 119 switch (Content) { 120 case UndefinedBooleanContent: 121 // Extend by adding rubbish bits. 122 return ISD::ANY_EXTEND; 123 case ZeroOrOneBooleanContent: 124 // Extend by adding zero bits. 125 return ISD::ZERO_EXTEND; 126 case ZeroOrNegativeOneBooleanContent: 127 // Extend by copying the sign bit. 128 return ISD::SIGN_EXTEND; 129 } 130 llvm_unreachable("Invalid content kind"); 131 } 132 133 /// NOTE: The constructor takes ownership of TLOF. 134 explicit TargetLoweringBase(const TargetMachine &TM, 135 const TargetLoweringObjectFile *TLOF); 136 virtual ~TargetLoweringBase(); 137 138 const TargetMachine &getTargetMachine() const { return TM; } 139 const DataLayout *getDataLayout() const { return TD; } 140 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 141 142 bool isBigEndian() const { return !IsLittleEndian; } 143 bool isLittleEndian() const { return IsLittleEndian; } 144 // Return the pointer type for the given address space, defaults to 145 // the pointer type from the data layout. 146 // FIXME: The default needs to be removed once all the code is updated. 147 virtual MVT getPointerTy(uint32_t AS = 0) const { return PointerTy; } 148 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const; 149 150 EVT getShiftAmountTy(EVT LHSTy) const; 151 152 /// isSelectExpensive - Return true if the select operation is expensive for 153 /// this target. 154 bool isSelectExpensive() const { return SelectIsExpensive; } 155 156 virtual bool isSelectSupported(SelectSupportKind kind) const { return true; } 157 158 /// shouldSplitVectorElementType - Return true if a vector of the given type 159 /// should be split (TypeSplitVector) instead of promoted 160 /// (TypePromoteInteger) during type legalization. 161 virtual bool shouldSplitVectorElementType(EVT VT) const { return false; } 162 163 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 164 /// a sequence of several shifts, adds, and multiplies for this target. 165 bool isIntDivCheap() const { return IntDivIsCheap; } 166 167 /// isSlowDivBypassed - Returns true if target has indicated at least one 168 /// type should be bypassed. 169 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); } 170 171 /// getBypassSlowDivTypes - Returns map of slow types for division or 172 /// remainder with corresponding fast types 173 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const { 174 return BypassSlowDivWidths; 175 } 176 177 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 178 /// srl/add/sra. 179 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 180 181 /// isJumpExpensive() - Return true if Flow Control is an expensive operation 182 /// that should be avoided. 183 bool isJumpExpensive() const { return JumpIsExpensive; } 184 185 /// isPredictableSelectExpensive - Return true if selects are only cheaper 186 /// than branches if the branch is unlikely to be predicted right. 187 bool isPredictableSelectExpensive() const { 188 return PredictableSelectIsExpensive; 189 } 190 191 /// getSetCCResultType - Return the ValueType of the result of SETCC 192 /// operations. Also used to obtain the target's preferred type for 193 /// the condition operand of SELECT and BRCOND nodes. In the case of 194 /// BRCOND the argument passed is MVT::Other since there are no other 195 /// operands to get a type hint from. 196 virtual EVT getSetCCResultType(EVT VT) const; 197 198 /// getCmpLibcallReturnType - Return the ValueType for comparison 199 /// libcalls. Comparions libcalls include floating point comparion calls, 200 /// and Ordered/Unordered check calls on floating point numbers. 201 virtual 202 MVT::SimpleValueType getCmpLibcallReturnType() const; 203 204 /// getBooleanContents - For targets without i1 registers, this gives the 205 /// nature of the high-bits of boolean values held in types wider than i1. 206 /// "Boolean values" are special true/false values produced by nodes like 207 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 208 /// Not to be confused with general values promoted from i1. 209 /// Some cpus distinguish between vectors of boolean and scalars; the isVec 210 /// parameter selects between the two kinds. For example on X86 a scalar 211 /// boolean should be zero extended from i1, while the elements of a vector 212 /// of booleans should be sign extended from i1. 213 BooleanContent getBooleanContents(bool isVec) const { 214 return isVec ? BooleanVectorContents : BooleanContents; 215 } 216 217 /// getSchedulingPreference - Return target scheduling preference. 218 Sched::Preference getSchedulingPreference() const { 219 return SchedPreferenceInfo; 220 } 221 222 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 223 /// different scheduling heuristics for different nodes. This function returns 224 /// the preference (or none) for the given node. 225 virtual Sched::Preference getSchedulingPreference(SDNode *) const { 226 return Sched::None; 227 } 228 229 /// getRegClassFor - Return the register class that should be used for the 230 /// specified value type. 231 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { 232 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 233 assert(RC && "This value type is not natively supported!"); 234 return RC; 235 } 236 237 /// getRepRegClassFor - Return the 'representative' register class for the 238 /// specified value type. The 'representative' register class is the largest 239 /// legal super-reg register class for the register class of the value type. 240 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 241 /// while the rep register class is GR64 on x86_64. 242 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { 243 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; 244 return RC; 245 } 246 247 /// getRepRegClassCostFor - Return the cost of the 'representative' register 248 /// class for the specified value type. 249 virtual uint8_t getRepRegClassCostFor(MVT VT) const { 250 return RepRegClassCostForVT[VT.SimpleTy]; 251 } 252 253 /// isTypeLegal - Return true if the target has native support for the 254 /// specified value type. This means that it has a register that directly 255 /// holds it without promotions or expansions. 256 bool isTypeLegal(EVT VT) const { 257 assert(!VT.isSimple() || 258 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 259 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 260 } 261 262 class ValueTypeActionImpl { 263 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum 264 /// that indicates how instruction selection should deal with the type. 265 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 266 267 public: 268 ValueTypeActionImpl() { 269 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 270 } 271 272 LegalizeTypeAction getTypeAction(MVT VT) const { 273 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; 274 } 275 276 void setTypeAction(MVT VT, LegalizeTypeAction Action) { 277 unsigned I = VT.SimpleTy; 278 ValueTypeActions[I] = Action; 279 } 280 }; 281 282 const ValueTypeActionImpl &getValueTypeActions() const { 283 return ValueTypeActions; 284 } 285 286 /// getTypeAction - Return how we should legalize values of this type, either 287 /// it is already legal (return 'Legal') or we need to promote it to a larger 288 /// type (return 'Promote'), or we need to expand it into multiple registers 289 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 290 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { 291 return getTypeConversion(Context, VT).first; 292 } 293 LegalizeTypeAction getTypeAction(MVT VT) const { 294 return ValueTypeActions.getTypeAction(VT); 295 } 296 297 /// getTypeToTransformTo - For types supported by the target, this is an 298 /// identity function. For types that must be promoted to larger types, this 299 /// returns the larger type to promote to. For integer types that are larger 300 /// than the largest integer register, this contains one step in the expansion 301 /// to get to the smaller register. For illegal floating point types, this 302 /// returns the integer type to transform to. 303 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 304 return getTypeConversion(Context, VT).second; 305 } 306 307 /// getTypeToExpandTo - For types supported by the target, this is an 308 /// identity function. For types that must be expanded (i.e. integer types 309 /// that are larger than the largest integer register or illegal floating 310 /// point types), this returns the largest legal type it will be expanded to. 311 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 312 assert(!VT.isVector()); 313 while (true) { 314 switch (getTypeAction(Context, VT)) { 315 case TypeLegal: 316 return VT; 317 case TypeExpandInteger: 318 VT = getTypeToTransformTo(Context, VT); 319 break; 320 default: 321 llvm_unreachable("Type is not legal nor is it to be expanded!"); 322 } 323 } 324 } 325 326 /// getVectorTypeBreakdown - Vector types are broken down into some number of 327 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 328 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 329 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 330 /// 331 /// This method returns the number of registers needed, and the VT for each 332 /// register. It also returns the VT and quantity of the intermediate values 333 /// before they are promoted/expanded. 334 /// 335 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 336 EVT &IntermediateVT, 337 unsigned &NumIntermediates, 338 MVT &RegisterVT) const; 339 340 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 341 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 342 /// this is the case, it returns true and store the intrinsic 343 /// information into the IntrinsicInfo that was passed to the function. 344 struct IntrinsicInfo { 345 unsigned opc; // target opcode 346 EVT memVT; // memory VT 347 const Value* ptrVal; // value representing memory location 348 int offset; // offset off of ptrVal 349 unsigned align; // alignment 350 bool vol; // is volatile? 351 bool readMem; // reads memory? 352 bool writeMem; // writes memory? 353 }; 354 355 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 356 unsigned /*Intrinsic*/) const { 357 return false; 358 } 359 360 /// isFPImmLegal - Returns true if the target can instruction select the 361 /// specified FP immediate natively. If false, the legalizer will materialize 362 /// the FP immediate as a load from a constant pool. 363 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const { 364 return false; 365 } 366 367 /// isShuffleMaskLegal - Targets can use this to indicate that they only 368 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 369 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 370 /// are assumed to be legal. 371 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 372 EVT /*VT*/) const { 373 return true; 374 } 375 376 /// canOpTrap - Returns true if the operation can trap for the value type. 377 /// VT must be a legal type. By default, we optimistically assume most 378 /// operations don't trap except for divide and remainder. 379 virtual bool canOpTrap(unsigned Op, EVT VT) const; 380 381 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 382 /// used by Targets can use this to indicate if there is a suitable 383 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 384 /// pool entry. 385 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 386 EVT /*VT*/) const { 387 return false; 388 } 389 390 /// getOperationAction - Return how this operation should be treated: either 391 /// it is legal, needs to be promoted to a larger size, needs to be 392 /// expanded to some other code sequence, or the target has a custom expander 393 /// for it. 394 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 395 if (VT.isExtended()) return Expand; 396 // If a target-specific SDNode requires legalization, require the target 397 // to provide custom legalization for it. 398 if (Op > array_lengthof(OpActions[0])) return Custom; 399 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 400 return (LegalizeAction)OpActions[I][Op]; 401 } 402 403 /// isOperationLegalOrCustom - Return true if the specified operation is 404 /// legal on this target or can be made legal with custom lowering. This 405 /// is used to help guide high-level lowering decisions. 406 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 407 return (VT == MVT::Other || isTypeLegal(VT)) && 408 (getOperationAction(Op, VT) == Legal || 409 getOperationAction(Op, VT) == Custom); 410 } 411 412 /// isOperationLegalOrPromote - Return true if the specified operation is 413 /// legal on this target or can be made legal using promotion. This 414 /// is used to help guide high-level lowering decisions. 415 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const { 416 return (VT == MVT::Other || isTypeLegal(VT)) && 417 (getOperationAction(Op, VT) == Legal || 418 getOperationAction(Op, VT) == Promote); 419 } 420 421 /// isOperationExpand - Return true if the specified operation is illegal on 422 /// this target or unlikely to be made legal with custom lowering. This is 423 /// used to help guide high-level lowering decisions. 424 bool isOperationExpand(unsigned Op, EVT VT) const { 425 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); 426 } 427 428 /// isOperationLegal - Return true if the specified operation is legal on this 429 /// target. 430 bool isOperationLegal(unsigned Op, EVT VT) const { 431 return (VT == MVT::Other || isTypeLegal(VT)) && 432 getOperationAction(Op, VT) == Legal; 433 } 434 435 /// getLoadExtAction - Return how this load with extension should be treated: 436 /// either it is legal, needs to be promoted to a larger size, needs to be 437 /// expanded to some other code sequence, or the target has a custom expander 438 /// for it. 439 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const { 440 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 441 "Table isn't big enough!"); 442 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType]; 443 } 444 445 /// isLoadExtLegal - Return true if the specified load with extension is legal 446 /// on this target. 447 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 448 return VT.isSimple() && 449 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal; 450 } 451 452 /// getTruncStoreAction - Return how this store with truncation should be 453 /// treated: either it is legal, needs to be promoted to a larger size, needs 454 /// to be expanded to some other code sequence, or the target has a custom 455 /// expander for it. 456 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const { 457 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 458 "Table isn't big enough!"); 459 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy] 460 [MemVT.SimpleTy]; 461 } 462 463 /// isTruncStoreLegal - Return true if the specified store with truncation is 464 /// legal on this target. 465 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 466 return isTypeLegal(ValVT) && MemVT.isSimple() && 467 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal; 468 } 469 470 /// getIndexedLoadAction - Return how the indexed load should be treated: 471 /// either it is legal, needs to be promoted to a larger size, needs to be 472 /// expanded to some other code sequence, or the target has a custom expander 473 /// for it. 474 LegalizeAction 475 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 476 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 477 "Table isn't big enough!"); 478 unsigned Ty = (unsigned)VT.SimpleTy; 479 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 480 } 481 482 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 483 /// on this target. 484 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 485 return VT.isSimple() && 486 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || 487 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); 488 } 489 490 /// getIndexedStoreAction - Return how the indexed store should be treated: 491 /// either it is legal, needs to be promoted to a larger size, needs to be 492 /// expanded to some other code sequence, or the target has a custom expander 493 /// for it. 494 LegalizeAction 495 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 496 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 497 "Table isn't big enough!"); 498 unsigned Ty = (unsigned)VT.SimpleTy; 499 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 500 } 501 502 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 503 /// on this target. 504 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 505 return VT.isSimple() && 506 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || 507 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); 508 } 509 510 /// getCondCodeAction - Return how the condition code should be treated: 511 /// either it is legal, needs to be expanded to some other code sequence, 512 /// or the target has a custom expander for it. 513 LegalizeAction 514 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 515 assert((unsigned)CC < array_lengthof(CondCodeActions) && 516 (unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 && 517 "Table isn't big enough!"); 518 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 519 /// value and the upper 27 bits index into the second dimension of the 520 /// array to select what 64bit value to use. 521 LegalizeAction Action = (LegalizeAction) 522 ((CondCodeActions[CC][VT.SimpleTy >> 5] >> (2*(VT.SimpleTy & 0x1F))) & 3); 523 assert(Action != Promote && "Can't promote condition code!"); 524 return Action; 525 } 526 527 /// isCondCodeLegal - Return true if the specified condition code is legal 528 /// on this target. 529 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 530 return 531 getCondCodeAction(CC, VT) == Legal || 532 getCondCodeAction(CC, VT) == Custom; 533 } 534 535 536 /// getTypeToPromoteTo - If the action for this operation is to promote, this 537 /// method returns the ValueType to promote to. 538 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 539 assert(getOperationAction(Op, VT) == Promote && 540 "This operation isn't promoted!"); 541 542 // See if this has an explicit type specified. 543 std::map<std::pair<unsigned, MVT::SimpleValueType>, 544 MVT::SimpleValueType>::const_iterator PTTI = 545 PromoteToType.find(std::make_pair(Op, VT.SimpleTy)); 546 if (PTTI != PromoteToType.end()) return PTTI->second; 547 548 assert((VT.isInteger() || VT.isFloatingPoint()) && 549 "Cannot autopromote this type, add it with AddPromotedToType."); 550 551 MVT NVT = VT; 552 do { 553 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1); 554 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 555 "Didn't find type to promote to!"); 556 } while (!isTypeLegal(NVT) || 557 getOperationAction(Op, NVT) == Promote); 558 return NVT; 559 } 560 561 /// getValueType - Return the EVT corresponding to this LLVM type. 562 /// This is fixed by the LLVM operations except for the pointer size. If 563 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 564 /// counterpart (e.g. structs), otherwise it will assert. 565 EVT getValueType(Type *Ty, bool AllowUnknown = false) const { 566 // Lower scalar pointers to native pointer types. 567 if (Ty->isPointerTy()) return PointerTy; 568 569 if (Ty->isVectorTy()) { 570 VectorType *VTy = cast<VectorType>(Ty); 571 Type *Elm = VTy->getElementType(); 572 // Lower vectors of pointers to native pointer types. 573 if (Elm->isPointerTy()) 574 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext()); 575 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), 576 VTy->getNumElements()); 577 } 578 return EVT::getEVT(Ty, AllowUnknown); 579 } 580 581 /// Return the MVT corresponding to this LLVM type. See getValueType. 582 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const { 583 return getValueType(Ty, AllowUnknown).getSimpleVT(); 584 } 585 586 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 587 /// function arguments in the caller parameter area. This is the actual 588 /// alignment, not its logarithm. 589 virtual unsigned getByValTypeAlignment(Type *Ty) const; 590 591 /// getRegisterType - Return the type of registers that this ValueType will 592 /// eventually require. 593 MVT getRegisterType(MVT VT) const { 594 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 595 return RegisterTypeForVT[VT.SimpleTy]; 596 } 597 598 /// getRegisterType - Return the type of registers that this ValueType will 599 /// eventually require. 600 MVT getRegisterType(LLVMContext &Context, EVT VT) const { 601 if (VT.isSimple()) { 602 assert((unsigned)VT.getSimpleVT().SimpleTy < 603 array_lengthof(RegisterTypeForVT)); 604 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 605 } 606 if (VT.isVector()) { 607 EVT VT1; 608 MVT RegisterVT; 609 unsigned NumIntermediates; 610 (void)getVectorTypeBreakdown(Context, VT, VT1, 611 NumIntermediates, RegisterVT); 612 return RegisterVT; 613 } 614 if (VT.isInteger()) { 615 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 616 } 617 llvm_unreachable("Unsupported extended type!"); 618 } 619 620 /// getNumRegisters - Return the number of registers that this ValueType will 621 /// eventually require. This is one for any types promoted to live in larger 622 /// registers, but may be more than one for types (like i64) that are split 623 /// into pieces. For types like i140, which are first promoted then expanded, 624 /// it is the number of registers needed to hold all the bits of the original 625 /// type. For an i140 on a 32 bit machine this means 5 registers. 626 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 627 if (VT.isSimple()) { 628 assert((unsigned)VT.getSimpleVT().SimpleTy < 629 array_lengthof(NumRegistersForVT)); 630 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 631 } 632 if (VT.isVector()) { 633 EVT VT1; 634 MVT VT2; 635 unsigned NumIntermediates; 636 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 637 } 638 if (VT.isInteger()) { 639 unsigned BitWidth = VT.getSizeInBits(); 640 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 641 return (BitWidth + RegWidth - 1) / RegWidth; 642 } 643 llvm_unreachable("Unsupported extended type!"); 644 } 645 646 /// ShouldShrinkFPConstant - If true, then instruction selection should 647 /// seek to shrink the FP constant of the specified type to a smaller type 648 /// in order to save space and / or reduce runtime. 649 virtual bool ShouldShrinkFPConstant(EVT) const { return true; } 650 651 /// hasTargetDAGCombine - If true, the target has custom DAG combine 652 /// transformations that it can perform for the specified node. 653 bool hasTargetDAGCombine(ISD::NodeType NT) const { 654 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 655 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 656 } 657 658 /// This function returns the maximum number of store operations permitted 659 /// to replace a call to llvm.memset. The value is set by the target at the 660 /// performance threshold for such a replacement. If OptSize is true, 661 /// return the limit for functions that have OptSize attribute. 662 /// @brief Get maximum # of store operations permitted for llvm.memset 663 unsigned getMaxStoresPerMemset(bool OptSize) const { 664 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset; 665 } 666 667 /// This function returns the maximum number of store operations permitted 668 /// to replace a call to llvm.memcpy. The value is set by the target at the 669 /// performance threshold for such a replacement. If OptSize is true, 670 /// return the limit for functions that have OptSize attribute. 671 /// @brief Get maximum # of store operations permitted for llvm.memcpy 672 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 673 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy; 674 } 675 676 /// This function returns the maximum number of store operations permitted 677 /// to replace a call to llvm.memmove. The value is set by the target at the 678 /// performance threshold for such a replacement. If OptSize is true, 679 /// return the limit for functions that have OptSize attribute. 680 /// @brief Get maximum # of store operations permitted for llvm.memmove 681 unsigned getMaxStoresPerMemmove(bool OptSize) const { 682 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove; 683 } 684 685 /// This function returns true if the target allows unaligned memory accesses. 686 /// of the specified type. If true, it also returns whether the unaligned 687 /// memory access is "fast" in the second argument by reference. This is used, 688 /// for example, in situations where an array copy/move/set is converted to a 689 /// sequence of store operations. It's use helps to ensure that such 690 /// replacements don't generate code that causes an alignment error (trap) on 691 /// the target machine. 692 /// @brief Determine if the target supports unaligned memory accesses. 693 virtual bool allowsUnalignedMemoryAccesses(EVT, bool *Fast = 0) const { 694 return false; 695 } 696 697 /// getOptimalMemOpType - Returns the target specific optimal type for load 698 /// and store operations as a result of memset, memcpy, and memmove 699 /// lowering. If DstAlign is zero that means it's safe to destination 700 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 701 /// means there isn't a need to check it against alignment requirement, 702 /// probably because the source does not need to be loaded. If 'IsMemset' is 703 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 704 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 705 /// source is constant so it does not need to be loaded. 706 /// It returns EVT::Other if the type should be determined using generic 707 /// target-independent logic. 708 virtual EVT getOptimalMemOpType(uint64_t /*Size*/, 709 unsigned /*DstAlign*/, unsigned /*SrcAlign*/, 710 bool /*IsMemset*/, 711 bool /*ZeroMemset*/, 712 bool /*MemcpyStrSrc*/, 713 MachineFunction &/*MF*/) const { 714 return MVT::Other; 715 } 716 717 /// isSafeMemOpType - Returns true if it's safe to use load / store of the 718 /// specified type to expand memcpy / memset inline. This is mostly true 719 /// for all types except for some special cases. For example, on X86 720 /// targets without SSE2 f64 load / store are done with fldl / fstpl which 721 /// also does type conversion. Note the specified type doesn't have to be 722 /// legal as the hook is used before type legalization. 723 virtual bool isSafeMemOpType(MVT VT) const { 724 return true; 725 } 726 727 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 728 /// to implement llvm.setjmp. 729 bool usesUnderscoreSetJmp() const { 730 return UseUnderscoreSetJmp; 731 } 732 733 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 734 /// to implement llvm.longjmp. 735 bool usesUnderscoreLongJmp() const { 736 return UseUnderscoreLongJmp; 737 } 738 739 /// supportJumpTables - return whether the target can generate code for 740 /// jump tables. 741 bool supportJumpTables() const { 742 return SupportJumpTables; 743 } 744 745 /// getMinimumJumpTableEntries - return integer threshold on number of 746 /// blocks to use jump tables rather than if sequence. 747 int getMinimumJumpTableEntries() const { 748 return MinimumJumpTableEntries; 749 } 750 751 /// getStackPointerRegisterToSaveRestore - If a physical register, this 752 /// specifies the register that llvm.savestack/llvm.restorestack should save 753 /// and restore. 754 unsigned getStackPointerRegisterToSaveRestore() const { 755 return StackPointerRegisterToSaveRestore; 756 } 757 758 /// getExceptionPointerRegister - If a physical register, this returns 759 /// the register that receives the exception address on entry to a landing 760 /// pad. 761 unsigned getExceptionPointerRegister() const { 762 return ExceptionPointerRegister; 763 } 764 765 /// getExceptionSelectorRegister - If a physical register, this returns 766 /// the register that receives the exception typeid on entry to a landing 767 /// pad. 768 unsigned getExceptionSelectorRegister() const { 769 return ExceptionSelectorRegister; 770 } 771 772 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 773 /// set, the default is 200) 774 unsigned getJumpBufSize() const { 775 return JumpBufSize; 776 } 777 778 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 779 /// (if never set, the default is 0) 780 unsigned getJumpBufAlignment() const { 781 return JumpBufAlignment; 782 } 783 784 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 785 /// argument. 786 unsigned getMinStackArgumentAlignment() const { 787 return MinStackArgumentAlignment; 788 } 789 790 /// getMinFunctionAlignment - return the minimum function alignment. 791 /// 792 unsigned getMinFunctionAlignment() const { 793 return MinFunctionAlignment; 794 } 795 796 /// getPrefFunctionAlignment - return the preferred function alignment. 797 /// 798 unsigned getPrefFunctionAlignment() const { 799 return PrefFunctionAlignment; 800 } 801 802 /// getPrefLoopAlignment - return the preferred loop alignment. 803 /// 804 unsigned getPrefLoopAlignment() const { 805 return PrefLoopAlignment; 806 } 807 808 /// getShouldFoldAtomicFences - return whether the combiner should fold 809 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 810 /// 811 bool getShouldFoldAtomicFences() const { 812 return ShouldFoldAtomicFences; 813 } 814 815 /// getInsertFencesFor - return whether the DAG builder should automatically 816 /// insert fences and reduce ordering for atomics. 817 /// 818 bool getInsertFencesForAtomic() const { 819 return InsertFencesForAtomic; 820 } 821 822 /// getStackCookieLocation - Return true if the target stores stack 823 /// protector cookies at a fixed offset in some non-standard address 824 /// space, and populates the address space and offset as 825 /// appropriate. 826 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/, 827 unsigned &/*Offset*/) const { 828 return false; 829 } 830 831 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be 832 /// used for loads / stores from the global. 833 virtual unsigned getMaximalGlobalOffset() const { 834 return 0; 835 } 836 837 //===--------------------------------------------------------------------===// 838 /// \name Helpers for TargetTransformInfo implementations 839 /// @{ 840 841 /// Get the ISD node that corresponds to the Instruction class opcode. 842 int InstructionOpcodeToISD(unsigned Opcode) const; 843 844 /// Estimate the cost of type-legalization and the legalized type. 845 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const; 846 847 /// @} 848 849 //===--------------------------------------------------------------------===// 850 // TargetLowering Configuration Methods - These methods should be invoked by 851 // the derived class constructor to configure this object for the target. 852 // 853 854protected: 855 /// setBooleanContents - Specify how the target extends the result of a 856 /// boolean value from i1 to a wider type. See getBooleanContents. 857 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 858 /// setBooleanVectorContents - Specify how the target extends the result 859 /// of a vector boolean value from a vector of i1 to a wider type. See 860 /// getBooleanContents. 861 void setBooleanVectorContents(BooleanContent Ty) { 862 BooleanVectorContents = Ty; 863 } 864 865 /// setSchedulingPreference - Specify the target scheduling preference. 866 void setSchedulingPreference(Sched::Preference Pref) { 867 SchedPreferenceInfo = Pref; 868 } 869 870 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 871 /// use _setjmp to implement llvm.setjmp or the non _ version. 872 /// Defaults to false. 873 void setUseUnderscoreSetJmp(bool Val) { 874 UseUnderscoreSetJmp = Val; 875 } 876 877 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 878 /// use _longjmp to implement llvm.longjmp or the non _ version. 879 /// Defaults to false. 880 void setUseUnderscoreLongJmp(bool Val) { 881 UseUnderscoreLongJmp = Val; 882 } 883 884 /// setSupportJumpTables - Indicate whether the target can generate code for 885 /// jump tables. 886 void setSupportJumpTables(bool Val) { 887 SupportJumpTables = Val; 888 } 889 890 /// setMinimumJumpTableEntries - Indicate the number of blocks to generate 891 /// jump tables rather than if sequence. 892 void setMinimumJumpTableEntries(int Val) { 893 MinimumJumpTableEntries = Val; 894 } 895 896 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 897 /// specifies the register that llvm.savestack/llvm.restorestack should save 898 /// and restore. 899 void setStackPointerRegisterToSaveRestore(unsigned R) { 900 StackPointerRegisterToSaveRestore = R; 901 } 902 903 /// setExceptionPointerRegister - If set to a physical register, this sets 904 /// the register that receives the exception address on entry to a landing 905 /// pad. 906 void setExceptionPointerRegister(unsigned R) { 907 ExceptionPointerRegister = R; 908 } 909 910 /// setExceptionSelectorRegister - If set to a physical register, this sets 911 /// the register that receives the exception typeid on entry to a landing 912 /// pad. 913 void setExceptionSelectorRegister(unsigned R) { 914 ExceptionSelectorRegister = R; 915 } 916 917 /// SelectIsExpensive - Tells the code generator not to expand operations 918 /// into sequences that use the select operations if possible. 919 void setSelectIsExpensive(bool isExpensive = true) { 920 SelectIsExpensive = isExpensive; 921 } 922 923 /// JumpIsExpensive - Tells the code generator not to expand sequence of 924 /// operations into a separate sequences that increases the amount of 925 /// flow control. 926 void setJumpIsExpensive(bool isExpensive = true) { 927 JumpIsExpensive = isExpensive; 928 } 929 930 /// setIntDivIsCheap - Tells the code generator that integer divide is 931 /// expensive, and if possible, should be replaced by an alternate sequence 932 /// of instructions not containing an integer divide. 933 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 934 935 /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass. 936 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { 937 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; 938 } 939 940 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 941 /// srl/add/sra for a signed divide by power of two, and let the target handle 942 /// it. 943 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 944 945 /// addRegisterClass - Add the specified register class as an available 946 /// regclass for the specified value type. This indicates the selector can 947 /// handle values of that class natively. 948 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { 949 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); 950 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 951 RegClassForVT[VT.SimpleTy] = RC; 952 } 953 954 /// clearRegisterClasses - remove all register classes 955 void clearRegisterClasses() { 956 for (unsigned i = 0 ; i<array_lengthof(RegClassForVT); i++) 957 RegClassForVT[i] = 0; 958 AvailableRegClasses.clear(); 959 } 960 961 /// findRepresentativeClass - Return the largest legal super-reg register class 962 /// of the register class for the specified type and its associated "cost". 963 virtual std::pair<const TargetRegisterClass*, uint8_t> 964 findRepresentativeClass(MVT VT) const; 965 966 /// computeRegisterProperties - Once all of the register classes are added, 967 /// this allows us to compute derived properties we expose. 968 void computeRegisterProperties(); 969 970 /// setOperationAction - Indicate that the specified operation does not work 971 /// with the specified type and indicate what to do about it. 972 void setOperationAction(unsigned Op, MVT VT, 973 LegalizeAction Action) { 974 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 975 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 976 } 977 978 /// setLoadExtAction - Indicate that the specified load with extension does 979 /// not work with the specified type and indicate what to do about it. 980 void setLoadExtAction(unsigned ExtType, MVT VT, 981 LegalizeAction Action) { 982 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 983 "Table isn't big enough!"); 984 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 985 } 986 987 /// setTruncStoreAction - Indicate that the specified truncating store does 988 /// not work with the specified type and indicate what to do about it. 989 void setTruncStoreAction(MVT ValVT, MVT MemVT, 990 LegalizeAction Action) { 991 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 992 "Table isn't big enough!"); 993 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 994 } 995 996 /// setIndexedLoadAction - Indicate that the specified indexed load does or 997 /// does not work with the specified type and indicate what to do abort 998 /// it. NOTE: All indexed mode loads are initialized to Expand in 999 /// TargetLowering.cpp 1000 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1001 LegalizeAction Action) { 1002 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1003 (unsigned)Action < 0xf && "Table isn't big enough!"); 1004 // Load action are kept in the upper half. 1005 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1006 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1007 } 1008 1009 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1010 /// does not work with the specified type and indicate what to do about 1011 /// it. NOTE: All indexed mode stores are initialized to Expand in 1012 /// TargetLowering.cpp 1013 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1014 LegalizeAction Action) { 1015 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1016 (unsigned)Action < 0xf && "Table isn't big enough!"); 1017 // Store action are kept in the lower half. 1018 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1019 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1020 } 1021 1022 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1023 /// supported on the target and indicate what to do about it. 1024 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1025 LegalizeAction Action) { 1026 assert(VT < MVT::LAST_VALUETYPE && 1027 (unsigned)CC < array_lengthof(CondCodeActions) && 1028 "Table isn't big enough!"); 1029 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 1030 /// value and the upper 27 bits index into the second dimension of the 1031 /// array to select what 64bit value to use. 1032 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1033 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2); 1034 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1035 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2; 1036 } 1037 1038 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1039 /// promotion code defaults to trying a larger integer/fp until it can find 1040 /// one that works. If that default is insufficient, this method can be used 1041 /// by the target to override the default. 1042 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1043 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1044 } 1045 1046 /// setTargetDAGCombine - Targets should invoke this method for each target 1047 /// independent node that they want to provide a custom DAG combiner for by 1048 /// implementing the PerformDAGCombine virtual method. 1049 void setTargetDAGCombine(ISD::NodeType NT) { 1050 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1051 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1052 } 1053 1054 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1055 /// bytes); default is 200 1056 void setJumpBufSize(unsigned Size) { 1057 JumpBufSize = Size; 1058 } 1059 1060 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1061 /// alignment (in bytes); default is 0 1062 void setJumpBufAlignment(unsigned Align) { 1063 JumpBufAlignment = Align; 1064 } 1065 1066 /// setMinFunctionAlignment - Set the target's minimum function alignment (in 1067 /// log2(bytes)) 1068 void setMinFunctionAlignment(unsigned Align) { 1069 MinFunctionAlignment = Align; 1070 } 1071 1072 /// setPrefFunctionAlignment - Set the target's preferred function alignment. 1073 /// This should be set if there is a performance benefit to 1074 /// higher-than-minimum alignment (in log2(bytes)) 1075 void setPrefFunctionAlignment(unsigned Align) { 1076 PrefFunctionAlignment = Align; 1077 } 1078 1079 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1080 /// alignment is zero, it means the target does not care about loop alignment. 1081 /// The alignment is specified in log2(bytes). 1082 void setPrefLoopAlignment(unsigned Align) { 1083 PrefLoopAlignment = Align; 1084 } 1085 1086 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1087 /// argument (in log2(bytes)). 1088 void setMinStackArgumentAlignment(unsigned Align) { 1089 MinStackArgumentAlignment = Align; 1090 } 1091 1092 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1093 /// atomic operation intrinsics includes locking. Default is false. 1094 void setShouldFoldAtomicFences(bool fold) { 1095 ShouldFoldAtomicFences = fold; 1096 } 1097 1098 /// setInsertFencesForAtomic - Set if the DAG builder should 1099 /// automatically insert fences and reduce the order of atomic memory 1100 /// operations to Monotonic. 1101 void setInsertFencesForAtomic(bool fence) { 1102 InsertFencesForAtomic = fence; 1103 } 1104 1105public: 1106 //===--------------------------------------------------------------------===// 1107 // Addressing mode description hooks (used by LSR etc). 1108 // 1109 1110 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the 1111 /// same BB as Load/Store instructions reading the address. This allows as 1112 /// much computation as possible to be done in the address mode for that 1113 /// operand. This hook lets targets also pass back when this should be done 1114 /// on intrinsics which load/store. 1115 virtual bool GetAddrModeArguments(IntrinsicInst *I, 1116 SmallVectorImpl<Value*> &Ops, 1117 Type *&AccessTy) const { 1118 return false; 1119 } 1120 1121 /// AddrMode - This represents an addressing mode of: 1122 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1123 /// If BaseGV is null, there is no BaseGV. 1124 /// If BaseOffs is zero, there is no base offset. 1125 /// If HasBaseReg is false, there is no base register. 1126 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1127 /// no scale. 1128 /// 1129 struct AddrMode { 1130 GlobalValue *BaseGV; 1131 int64_t BaseOffs; 1132 bool HasBaseReg; 1133 int64_t Scale; 1134 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1135 }; 1136 1137 /// isLegalAddressingMode - Return true if the addressing mode represented by 1138 /// AM is legal for this target, for a load/store of the specified type. 1139 /// The type may be VoidTy, in which case only return true if the addressing 1140 /// mode is legal for a load/store of any legal type. 1141 /// TODO: Handle pre/postinc as well. 1142 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 1143 1144 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1145 /// icmp immediate, that is the target has icmp instructions which can compare 1146 /// a register against the immediate without having to materialize the 1147 /// immediate into a register. 1148 virtual bool isLegalICmpImmediate(int64_t) const { 1149 return true; 1150 } 1151 1152 /// isLegalAddImmediate - Return true if the specified immediate is legal 1153 /// add immediate, that is the target has add instructions which can add 1154 /// a register with the immediate without having to materialize the 1155 /// immediate into a register. 1156 virtual bool isLegalAddImmediate(int64_t) const { 1157 return true; 1158 } 1159 1160 /// isTruncateFree - Return true if it's free to truncate a value of 1161 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1162 /// register EAX to i16 by referencing its sub-register AX. 1163 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1164 return false; 1165 } 1166 1167 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const { 1168 return false; 1169 } 1170 1171 /// isZExtFree - Return true if any actual instruction that defines a 1172 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1173 /// register. This does not necessarily include registers defined in 1174 /// unknown ways, such as incoming arguments, or copies from unknown 1175 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1176 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1177 /// all instructions that define 32-bit values implicit zero-extend the 1178 /// result out to 64 bits. 1179 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1180 return false; 1181 } 1182 1183 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const { 1184 return false; 1185 } 1186 1187 /// isZExtFree - Return true if zero-extending the specific node Val to type 1188 /// VT2 is free (either because it's implicitly zero-extended such as ARM 1189 /// ldrb / ldrh or because it's folded such as X86 zero-extending loads). 1190 virtual bool isZExtFree(SDValue Val, EVT VT2) const { 1191 return isZExtFree(Val.getValueType(), VT2); 1192 } 1193 1194 /// isFNegFree - Return true if an fneg operation is free to the point where 1195 /// it is never worthwhile to replace it with a bitwise operation. 1196 virtual bool isFNegFree(EVT) const { 1197 return false; 1198 } 1199 1200 /// isFAbsFree - Return true if an fneg operation is free to the point where 1201 /// it is never worthwhile to replace it with a bitwise operation. 1202 virtual bool isFAbsFree(EVT) const { 1203 return false; 1204 } 1205 1206 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 1207 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 1208 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 1209 /// is expanded to mul + add. 1210 virtual bool isFMAFasterThanMulAndAdd(EVT) const { 1211 return false; 1212 } 1213 1214 /// isNarrowingProfitable - Return true if it's profitable to narrow 1215 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1216 /// from i32 to i8 but not from i32 to i16. 1217 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { 1218 return false; 1219 } 1220 1221 //===--------------------------------------------------------------------===// 1222 // Runtime Library hooks 1223 // 1224 1225 /// setLibcallName - Rename the default libcall routine name for the specified 1226 /// libcall. 1227 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1228 LibcallRoutineNames[Call] = Name; 1229 } 1230 1231 /// getLibcallName - Get the libcall routine name for the specified libcall. 1232 /// 1233 const char *getLibcallName(RTLIB::Libcall Call) const { 1234 return LibcallRoutineNames[Call]; 1235 } 1236 1237 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1238 /// result of the comparison libcall against zero. 1239 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1240 CmpLibcallCCs[Call] = CC; 1241 } 1242 1243 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1244 /// the comparison libcall against zero. 1245 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1246 return CmpLibcallCCs[Call]; 1247 } 1248 1249 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1250 /// specified libcall. 1251 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1252 LibcallCallingConvs[Call] = CC; 1253 } 1254 1255 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1256 /// specified libcall. 1257 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1258 return LibcallCallingConvs[Call]; 1259 } 1260 1261private: 1262 const TargetMachine &TM; 1263 const DataLayout *TD; 1264 const TargetLoweringObjectFile &TLOF; 1265 1266 /// PointerTy - The type to use for pointers for the default address space, 1267 /// usually i32 or i64. 1268 /// 1269 MVT PointerTy; 1270 1271 /// IsLittleEndian - True if this is a little endian target. 1272 /// 1273 bool IsLittleEndian; 1274 1275 /// SelectIsExpensive - Tells the code generator not to expand operations 1276 /// into sequences that use the select operations if possible. 1277 bool SelectIsExpensive; 1278 1279 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1280 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1281 /// a real cost model is in place. If we ever optimize for size, this will be 1282 /// set to true unconditionally. 1283 bool IntDivIsCheap; 1284 1285 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or 1286 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the 1287 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned 1288 /// integer div/rem when the operands are positive and less than 256. 1289 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths; 1290 1291 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1292 /// srl/add/sra for a signed divide by power of two, and let the target handle 1293 /// it. 1294 bool Pow2DivIsCheap; 1295 1296 /// JumpIsExpensive - Tells the code generator that it shouldn't generate 1297 /// extra flow control instructions and should attempt to combine flow 1298 /// control instructions via predication. 1299 bool JumpIsExpensive; 1300 1301 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1302 /// llvm.setjmp. Defaults to false. 1303 bool UseUnderscoreSetJmp; 1304 1305 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1306 /// llvm.longjmp. Defaults to false. 1307 bool UseUnderscoreLongJmp; 1308 1309 /// SupportJumpTables - Whether the target can generate code for jumptables. 1310 /// If it's not true, then each jumptable must be lowered into if-then-else's. 1311 bool SupportJumpTables; 1312 1313 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables. 1314 int MinimumJumpTableEntries; 1315 1316 /// BooleanContents - Information about the contents of the high-bits in 1317 /// boolean values held in a type wider than i1. See getBooleanContents. 1318 BooleanContent BooleanContents; 1319 /// BooleanVectorContents - Information about the contents of the high-bits 1320 /// in boolean vector values when the element type is wider than i1. See 1321 /// getBooleanContents. 1322 BooleanContent BooleanVectorContents; 1323 1324 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1325 /// total cycles or lowest register usage. 1326 Sched::Preference SchedPreferenceInfo; 1327 1328 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1329 unsigned JumpBufSize; 1330 1331 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1332 /// buffers 1333 unsigned JumpBufAlignment; 1334 1335 /// MinStackArgumentAlignment - The minimum alignment that any argument 1336 /// on the stack needs to have. 1337 /// 1338 unsigned MinStackArgumentAlignment; 1339 1340 /// MinFunctionAlignment - The minimum function alignment (used when 1341 /// optimizing for size, and to prevent explicitly provided alignment 1342 /// from leading to incorrect code). 1343 /// 1344 unsigned MinFunctionAlignment; 1345 1346 /// PrefFunctionAlignment - The preferred function alignment (used when 1347 /// alignment unspecified and optimizing for speed). 1348 /// 1349 unsigned PrefFunctionAlignment; 1350 1351 /// PrefLoopAlignment - The preferred loop alignment. 1352 /// 1353 unsigned PrefLoopAlignment; 1354 1355 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1356 /// be folded into the enclosed atomic intrinsic instruction by the 1357 /// combiner. 1358 bool ShouldFoldAtomicFences; 1359 1360 /// InsertFencesForAtomic - Whether the DAG builder should automatically 1361 /// insert fences and reduce ordering for atomics. (This will be set for 1362 /// for most architectures with weak memory ordering.) 1363 bool InsertFencesForAtomic; 1364 1365 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1366 /// specifies the register that llvm.savestack/llvm.restorestack should save 1367 /// and restore. 1368 unsigned StackPointerRegisterToSaveRestore; 1369 1370 /// ExceptionPointerRegister - If set to a physical register, this specifies 1371 /// the register that receives the exception address on entry to a landing 1372 /// pad. 1373 unsigned ExceptionPointerRegister; 1374 1375 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1376 /// the register that receives the exception typeid on entry to a landing 1377 /// pad. 1378 unsigned ExceptionSelectorRegister; 1379 1380 /// RegClassForVT - This indicates the default register class to use for 1381 /// each ValueType the target supports natively. 1382 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1383 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1384 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1385 1386 /// RepRegClassForVT - This indicates the "representative" register class to 1387 /// use for each ValueType the target supports natively. This information is 1388 /// used by the scheduler to track register pressure. By default, the 1389 /// representative register class is the largest legal super-reg register 1390 /// class of the register class of the specified type. e.g. On x86, i8, i16, 1391 /// and i32's representative class would be GR32. 1392 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1393 1394 /// RepRegClassCostForVT - This indicates the "cost" of the "representative" 1395 /// register class for each ValueType. The cost is used by the scheduler to 1396 /// approximate register pressure. 1397 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1398 1399 /// TransformToType - For any value types we are promoting or expanding, this 1400 /// contains the value type that we are changing to. For Expanded types, this 1401 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1402 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1403 /// by the system, this holds the same type (e.g. i32 -> i32). 1404 MVT TransformToType[MVT::LAST_VALUETYPE]; 1405 1406 /// OpActions - For each operation and each value type, keep a LegalizeAction 1407 /// that indicates how instruction selection should deal with the operation. 1408 /// Most operations are Legal (aka, supported natively by the target), but 1409 /// operations that are not should be described. Note that operations on 1410 /// non-legal value types are not described here. 1411 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1412 1413 /// LoadExtActions - For each load extension type and each value type, 1414 /// keep a LegalizeAction that indicates how instruction selection should deal 1415 /// with a load of a specific value type and extension type. 1416 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1417 1418 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1419 /// indicates whether a truncating store of a specific value type and 1420 /// truncating type is legal. 1421 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1422 1423 /// IndexedModeActions - For each indexed mode and each value type, 1424 /// keep a pair of LegalizeAction that indicates how instruction 1425 /// selection should deal with the load / store. The first dimension is the 1426 /// value_type for the reference. The second dimension represents the various 1427 /// modes for load store. 1428 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1429 1430 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1431 /// LegalizeAction that indicates how instruction selection should 1432 /// deal with the condition code. 1433 /// Because each CC action takes up 2 bits, we need to have the array size 1434 /// be large enough to fit all of the value types. This can be done by 1435 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one. 1436 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1]; 1437 1438 ValueTypeActionImpl ValueTypeActions; 1439 1440public: 1441 LegalizeKind 1442 getTypeConversion(LLVMContext &Context, EVT VT) const { 1443 // If this is a simple type, use the ComputeRegisterProp mechanism. 1444 if (VT.isSimple()) { 1445 MVT SVT = VT.getSimpleVT(); 1446 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 1447 MVT NVT = TransformToType[SVT.SimpleTy]; 1448 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 1449 1450 assert( 1451 (LA == TypeLegal || 1452 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) 1453 && "Promote may not follow Expand or Promote"); 1454 1455 if (LA == TypeSplitVector) 1456 return LegalizeKind(LA, EVT::getVectorVT(Context, 1457 SVT.getVectorElementType(), 1458 SVT.getVectorNumElements()/2)); 1459 if (LA == TypeScalarizeVector) 1460 return LegalizeKind(LA, SVT.getVectorElementType()); 1461 return LegalizeKind(LA, NVT); 1462 } 1463 1464 // Handle Extended Scalar Types. 1465 if (!VT.isVector()) { 1466 assert(VT.isInteger() && "Float types must be simple"); 1467 unsigned BitSize = VT.getSizeInBits(); 1468 // First promote to a power-of-two size, then expand if necessary. 1469 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1470 EVT NVT = VT.getRoundIntegerType(Context); 1471 assert(NVT != VT && "Unable to round integer VT"); 1472 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1473 // Avoid multi-step promotion. 1474 if (NextStep.first == TypePromoteInteger) return NextStep; 1475 // Return rounded integer type. 1476 return LegalizeKind(TypePromoteInteger, NVT); 1477 } 1478 1479 return LegalizeKind(TypeExpandInteger, 1480 EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); 1481 } 1482 1483 // Handle vector types. 1484 unsigned NumElts = VT.getVectorNumElements(); 1485 EVT EltVT = VT.getVectorElementType(); 1486 1487 // Vectors with only one element are always scalarized. 1488 if (NumElts == 1) 1489 return LegalizeKind(TypeScalarizeVector, EltVT); 1490 1491 // Try to widen vector elements until a legal type is found. 1492 if (EltVT.isInteger()) { 1493 // Vectors with a number of elements that is not a power of two are always 1494 // widened, for example <3 x float> -> <4 x float>. 1495 if (!VT.isPow2VectorType()) { 1496 NumElts = (unsigned)NextPowerOf2(NumElts); 1497 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1498 return LegalizeKind(TypeWidenVector, NVT); 1499 } 1500 1501 // Examine the element type. 1502 LegalizeKind LK = getTypeConversion(Context, EltVT); 1503 1504 // If type is to be expanded, split the vector. 1505 // <4 x i140> -> <2 x i140> 1506 if (LK.first == TypeExpandInteger) 1507 return LegalizeKind(TypeSplitVector, 1508 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1509 1510 // Promote the integer element types until a legal vector type is found 1511 // or until the element integer type is too big. If a legal type was not 1512 // found, fallback to the usual mechanism of widening/splitting the 1513 // vector. 1514 while (1) { 1515 // Increase the bitwidth of the element to the next pow-of-two 1516 // (which is greater than 8 bits). 1517 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() 1518 ).getRoundIntegerType(Context); 1519 1520 // Stop trying when getting a non-simple element type. 1521 // Note that vector elements may be greater than legal vector element 1522 // types. Example: X86 XMM registers hold 64bit element on 32bit systems. 1523 if (!EltVT.isSimple()) break; 1524 1525 // Build a new vector type and check if it is legal. 1526 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1527 // Found a legal promoted vector type. 1528 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1529 return LegalizeKind(TypePromoteInteger, 1530 EVT::getVectorVT(Context, EltVT, NumElts)); 1531 } 1532 } 1533 1534 // Try to widen the vector until a legal type is found. 1535 // If there is no wider legal type, split the vector. 1536 while (1) { 1537 // Round up to the next power of 2. 1538 NumElts = (unsigned)NextPowerOf2(NumElts); 1539 1540 // If there is no simple vector type with this many elements then there 1541 // cannot be a larger legal vector type. Note that this assumes that 1542 // there are no skipped intermediate vector types in the simple types. 1543 if (!EltVT.isSimple()) break; 1544 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1545 if (LargerVector == MVT()) break; 1546 1547 // If this type is legal then widen the vector. 1548 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1549 return LegalizeKind(TypeWidenVector, LargerVector); 1550 } 1551 1552 // Widen odd vectors to next power of two. 1553 if (!VT.isPow2VectorType()) { 1554 EVT NVT = VT.getPow2VectorType(Context); 1555 return LegalizeKind(TypeWidenVector, NVT); 1556 } 1557 1558 // Vectors with illegal element types are expanded. 1559 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1560 return LegalizeKind(TypeSplitVector, NVT); 1561 } 1562 1563private: 1564 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses; 1565 1566 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1567 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1568 /// which sets a bit in this array. 1569 unsigned char 1570 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1571 1572 /// PromoteToType - For operations that must be promoted to a specific type, 1573 /// this holds the destination type. This map should be sparse, so don't hold 1574 /// it as an array. 1575 /// 1576 /// Targets add entries to this map with AddPromotedToType(..), clients access 1577 /// this with getTypeToPromoteTo(..). 1578 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1579 PromoteToType; 1580 1581 /// LibcallRoutineNames - Stores the name each libcall. 1582 /// 1583 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1584 1585 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1586 /// of each of the comparison libcall against zero. 1587 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1588 1589 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1590 /// libcall. 1591 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1592 1593protected: 1594 /// When lowering \@llvm.memset this field specifies the maximum number of 1595 /// store operations that may be substituted for the call to memset. Targets 1596 /// must set this value based on the cost threshold for that target. Targets 1597 /// should assume that the memset will be done using as many of the largest 1598 /// store operations first, followed by smaller ones, if necessary, per 1599 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1600 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1601 /// store. This only applies to setting a constant array of a constant size. 1602 /// @brief Specify maximum number of store instructions per memset call. 1603 unsigned MaxStoresPerMemset; 1604 1605 /// Maximum number of stores operations that may be substituted for the call 1606 /// to memset, used for functions with OptSize attribute. 1607 unsigned MaxStoresPerMemsetOptSize; 1608 1609 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1610 /// store operations that may be substituted for a call to memcpy. Targets 1611 /// must set this value based on the cost threshold for that target. Targets 1612 /// should assume that the memcpy will be done using as many of the largest 1613 /// store operations first, followed by smaller ones, if necessary, per 1614 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1615 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1616 /// and one 1-byte store. This only applies to copying a constant array of 1617 /// constant size. 1618 /// @brief Specify maximum bytes of store instructions per memcpy call. 1619 unsigned MaxStoresPerMemcpy; 1620 1621 /// Maximum number of store operations that may be substituted for a call 1622 /// to memcpy, used for functions with OptSize attribute. 1623 unsigned MaxStoresPerMemcpyOptSize; 1624 1625 /// When lowering \@llvm.memmove this field specifies the maximum number of 1626 /// store instructions that may be substituted for a call to memmove. Targets 1627 /// must set this value based on the cost threshold for that target. Targets 1628 /// should assume that the memmove will be done using as many of the largest 1629 /// store operations first, followed by smaller ones, if necessary, per 1630 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1631 /// with 8-bit alignment would result in nine 1-byte stores. This only 1632 /// applies to copying a constant array of constant size. 1633 /// @brief Specify maximum bytes of store instructions per memmove call. 1634 unsigned MaxStoresPerMemmove; 1635 1636 /// Maximum number of store instructions that may be substituted for a call 1637 /// to memmove, used for functions with OpSize attribute. 1638 unsigned MaxStoresPerMemmoveOptSize; 1639 1640 /// PredictableSelectIsExpensive - Tells the code generator that select is 1641 /// more expensive than a branch if the branch is usually predicted right. 1642 bool PredictableSelectIsExpensive; 1643 1644protected: 1645 /// isLegalRC - Return true if the value types that can be represented by the 1646 /// specified register class are all legal. 1647 bool isLegalRC(const TargetRegisterClass *RC) const; 1648}; 1649 1650//===----------------------------------------------------------------------===// 1651/// TargetLowering - This class defines information used to lower LLVM code to 1652/// legal SelectionDAG operators that the target instruction selector can accept 1653/// natively. 1654/// 1655/// This class also defines callbacks that targets must implement to lower 1656/// target-specific constructs to SelectionDAG operators. 1657/// 1658class TargetLowering : public TargetLoweringBase { 1659 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION; 1660 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION; 1661 1662public: 1663 /// NOTE: The constructor takes ownership of TLOF. 1664 explicit TargetLowering(const TargetMachine &TM, 1665 const TargetLoweringObjectFile *TLOF); 1666 1667 /// getPreIndexedAddressParts - returns true by value, base pointer and 1668 /// offset pointer and addressing mode by reference if the node's address 1669 /// can be legally represented as pre-indexed load / store address. 1670 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, 1671 SDValue &/*Offset*/, 1672 ISD::MemIndexedMode &/*AM*/, 1673 SelectionDAG &/*DAG*/) const { 1674 return false; 1675 } 1676 1677 /// getPostIndexedAddressParts - returns true by value, base pointer and 1678 /// offset pointer and addressing mode by reference if this node can be 1679 /// combined with a load / store to form a post-indexed load / store. 1680 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, 1681 SDValue &/*Base*/, SDValue &/*Offset*/, 1682 ISD::MemIndexedMode &/*AM*/, 1683 SelectionDAG &/*DAG*/) const { 1684 return false; 1685 } 1686 1687 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 1688 /// current function. The returned value is a member of the 1689 /// MachineJumpTableInfo::JTEntryKind enum. 1690 virtual unsigned getJumpTableEncoding() const; 1691 1692 virtual const MCExpr * 1693 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/, 1694 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/, 1695 MCContext &/*Ctx*/) const { 1696 llvm_unreachable("Need to implement this hook if target has custom JTIs"); 1697 } 1698 1699 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1700 /// jumptable. 1701 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 1702 SelectionDAG &DAG) const; 1703 1704 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1705 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1706 /// MCExpr. 1707 virtual const MCExpr * 1708 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1709 unsigned JTI, MCContext &Ctx) const; 1710 1711 /// isOffsetFoldingLegal - Return true if folding a constant offset 1712 /// with the given GlobalAddress is legal. It is frequently not legal in 1713 /// PIC relocation models. 1714 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 1715 1716 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 1717 SDValue &Chain) const; 1718 1719 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, 1720 SDValue &NewLHS, SDValue &NewRHS, 1721 ISD::CondCode &CCCode, DebugLoc DL) const; 1722 1723 SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, 1724 const SDValue *Ops, unsigned NumOps, 1725 bool isSigned, DebugLoc dl) const; 1726 1727 //===--------------------------------------------------------------------===// 1728 // TargetLowering Optimization Methods 1729 // 1730 1731 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 1732 /// SDValues for returning information from TargetLowering to its clients 1733 /// that want to combine 1734 struct TargetLoweringOpt { 1735 SelectionDAG &DAG; 1736 bool LegalTys; 1737 bool LegalOps; 1738 SDValue Old; 1739 SDValue New; 1740 1741 explicit TargetLoweringOpt(SelectionDAG &InDAG, 1742 bool LT, bool LO) : 1743 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 1744 1745 bool LegalTypes() const { return LegalTys; } 1746 bool LegalOperations() const { return LegalOps; } 1747 1748 bool CombineTo(SDValue O, SDValue N) { 1749 Old = O; 1750 New = N; 1751 return true; 1752 } 1753 1754 /// ShrinkDemandedConstant - Check to see if the specified operand of the 1755 /// specified instruction is a constant integer. If so, check to see if 1756 /// there are any bits set in the constant that are not demanded. If so, 1757 /// shrink the constant and return true. 1758 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 1759 1760 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1761 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1762 /// cast, but it could be generalized for targets with other types of 1763 /// implicit widening casts. 1764 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 1765 DebugLoc dl); 1766 }; 1767 1768 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1769 /// DemandedMask bits of the result of Op are ever used downstream. If we can 1770 /// use this information to simplify Op, create a new simplified DAG node and 1771 /// return true, returning the original and new nodes in Old and New. 1772 /// Otherwise, analyze the expression and return a mask of KnownOne and 1773 /// KnownZero bits for the expression (used to simplify the caller). 1774 /// The KnownZero/One bits may only be accurate for those bits in the 1775 /// DemandedMask. 1776 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 1777 APInt &KnownZero, APInt &KnownOne, 1778 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 1779 1780 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 1781 /// Mask are known to be either zero or one and return them in the 1782 /// KnownZero/KnownOne bitsets. 1783 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 1784 APInt &KnownZero, 1785 APInt &KnownOne, 1786 const SelectionDAG &DAG, 1787 unsigned Depth = 0) const; 1788 1789 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 1790 /// targets that want to expose additional information about sign bits to the 1791 /// DAG Combiner. 1792 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 1793 unsigned Depth = 0) const; 1794 1795 struct DAGCombinerInfo { 1796 void *DC; // The DAG Combiner object. 1797 CombineLevel Level; 1798 bool CalledByLegalizer; 1799 public: 1800 SelectionDAG &DAG; 1801 1802 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc) 1803 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {} 1804 1805 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } 1806 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } 1807 bool isAfterLegalizeVectorOps() const { 1808 return Level == AfterLegalizeDAG; 1809 } 1810 CombineLevel getDAGCombineLevel() { return Level; } 1811 bool isCalledByLegalizer() const { return CalledByLegalizer; } 1812 1813 void AddToWorklist(SDNode *N); 1814 void RemoveFromWorklist(SDNode *N); 1815 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 1816 bool AddTo = true); 1817 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 1818 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 1819 1820 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 1821 }; 1822 1823 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 1824 /// and cc. If it is unable to simplify it, return a null SDValue. 1825 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1826 ISD::CondCode Cond, bool foldBooleans, 1827 DAGCombinerInfo &DCI, DebugLoc dl) const; 1828 1829 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1830 /// node is a GlobalAddress + offset. 1831 virtual bool 1832 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 1833 1834 /// PerformDAGCombine - This method will be invoked for all target nodes and 1835 /// for any target-independent nodes that the target has registered with 1836 /// invoke it for. 1837 /// 1838 /// The semantics are as follows: 1839 /// Return Value: 1840 /// SDValue.Val == 0 - No change was made 1841 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 1842 /// otherwise - N should be replaced by the returned Operand. 1843 /// 1844 /// In addition, methods provided by DAGCombinerInfo may be used to perform 1845 /// more complex transformations. 1846 /// 1847 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 1848 1849 /// isTypeDesirableForOp - Return true if the target has native support for 1850 /// the specified value type and it is 'desirable' to use the type for the 1851 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 1852 /// instruction encodings are longer and some i16 instructions are slow. 1853 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { 1854 // By default, assume all legal types are desirable. 1855 return isTypeLegal(VT); 1856 } 1857 1858 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner 1859 /// to transform a floating point op of specified opcode to a equivalent op of 1860 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM. 1861 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, 1862 EVT /*VT*/) const { 1863 return false; 1864 } 1865 1866 /// IsDesirableToPromoteOp - This method query the target whether it is 1867 /// beneficial for dag combiner to promote the specified node. If true, it 1868 /// should return the desired promotion type by reference. 1869 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { 1870 return false; 1871 } 1872 1873 //===--------------------------------------------------------------------===// 1874 // Lowering methods - These methods must be implemented by targets so that 1875 // the SelectionDAGBuilder code knows how to lower these. 1876 // 1877 1878 /// LowerFormalArguments - This hook must be implemented to lower the 1879 /// incoming (formal) arguments, described by the Ins array, into the 1880 /// specified DAG. The implementation should fill in the InVals array 1881 /// with legal-type argument values, and return the resulting token 1882 /// chain value. 1883 /// 1884 virtual SDValue 1885 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1886 bool /*isVarArg*/, 1887 const SmallVectorImpl<ISD::InputArg> &/*Ins*/, 1888 DebugLoc /*dl*/, SelectionDAG &/*DAG*/, 1889 SmallVectorImpl<SDValue> &/*InVals*/) const { 1890 llvm_unreachable("Not Implemented"); 1891 } 1892 1893 struct ArgListEntry { 1894 SDValue Node; 1895 Type* Ty; 1896 bool isSExt : 1; 1897 bool isZExt : 1; 1898 bool isInReg : 1; 1899 bool isSRet : 1; 1900 bool isNest : 1; 1901 bool isByVal : 1; 1902 uint16_t Alignment; 1903 1904 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1905 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1906 }; 1907 typedef std::vector<ArgListEntry> ArgListTy; 1908 1909 /// CallLoweringInfo - This structure contains all information that is 1910 /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the 1911 /// SelectionDAG builder needs to lower a call, and targets will see this 1912 /// struct in their LowerCall implementation. 1913 struct CallLoweringInfo { 1914 SDValue Chain; 1915 Type *RetTy; 1916 bool RetSExt : 1; 1917 bool RetZExt : 1; 1918 bool IsVarArg : 1; 1919 bool IsInReg : 1; 1920 bool DoesNotReturn : 1; 1921 bool IsReturnValueUsed : 1; 1922 1923 // IsTailCall should be modified by implementations of 1924 // TargetLowering::LowerCall that perform tail call conversions. 1925 bool IsTailCall; 1926 1927 unsigned NumFixedArgs; 1928 CallingConv::ID CallConv; 1929 SDValue Callee; 1930 ArgListTy &Args; 1931 SelectionDAG &DAG; 1932 DebugLoc DL; 1933 ImmutableCallSite *CS; 1934 SmallVector<ISD::OutputArg, 32> Outs; 1935 SmallVector<SDValue, 32> OutVals; 1936 SmallVector<ISD::InputArg, 32> Ins; 1937 1938 1939 /// CallLoweringInfo - Constructs a call lowering context based on the 1940 /// ImmutableCallSite \p cs. 1941 CallLoweringInfo(SDValue chain, Type *retTy, 1942 FunctionType *FTy, bool isTailCall, SDValue callee, 1943 ArgListTy &args, SelectionDAG &dag, DebugLoc dl, 1944 ImmutableCallSite &cs) 1945 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)), 1946 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()), 1947 IsInReg(cs.paramHasAttr(0, Attribute::InReg)), 1948 DoesNotReturn(cs.doesNotReturn()), 1949 IsReturnValueUsed(!cs.getInstruction()->use_empty()), 1950 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()), 1951 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag), 1952 DL(dl), CS(&cs) {} 1953 1954 /// CallLoweringInfo - Constructs a call lowering context based on the 1955 /// provided call information. 1956 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt, 1957 bool isVarArg, bool isInReg, unsigned numFixedArgs, 1958 CallingConv::ID callConv, bool isTailCall, 1959 bool doesNotReturn, bool isReturnValueUsed, SDValue callee, 1960 ArgListTy &args, SelectionDAG &dag, DebugLoc dl) 1961 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt), 1962 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn), 1963 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall), 1964 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee), 1965 Args(args), DAG(dag), DL(dl), CS(NULL) {} 1966 }; 1967 1968 /// LowerCallTo - This function lowers an abstract call to a function into an 1969 /// actual call. This returns a pair of operands. The first element is the 1970 /// return value for the function (if RetTy is not VoidTy). The second 1971 /// element is the outgoing token chain. It calls LowerCall to do the actual 1972 /// lowering. 1973 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const; 1974 1975 /// LowerCall - This hook must be implemented to lower calls into the 1976 /// the specified DAG. The outgoing arguments to the call are described 1977 /// by the Outs array, and the values to be returned by the call are 1978 /// described by the Ins array. The implementation should fill in the 1979 /// InVals array with legal-type return values from the call, and return 1980 /// the resulting token chain value. 1981 virtual SDValue 1982 LowerCall(CallLoweringInfo &/*CLI*/, 1983 SmallVectorImpl<SDValue> &/*InVals*/) const { 1984 llvm_unreachable("Not Implemented"); 1985 } 1986 1987 /// HandleByVal - Target-specific cleanup for formal ByVal parameters. 1988 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {} 1989 1990 /// CanLowerReturn - This hook should be implemented to check whether the 1991 /// return values described by the Outs array can fit into the return 1992 /// registers. If false is returned, an sret-demotion is performed. 1993 /// 1994 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, 1995 MachineFunction &/*MF*/, bool /*isVarArg*/, 1996 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 1997 LLVMContext &/*Context*/) const 1998 { 1999 // Return true by default to get preexisting behavior. 2000 return true; 2001 } 2002 2003 /// LowerReturn - This hook must be implemented to lower outgoing 2004 /// return values, described by the Outs array, into the specified 2005 /// DAG. The implementation should return the resulting token chain 2006 /// value. 2007 /// 2008 virtual SDValue 2009 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 2010 bool /*isVarArg*/, 2011 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 2012 const SmallVectorImpl<SDValue> &/*OutVals*/, 2013 DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const { 2014 llvm_unreachable("Not Implemented"); 2015 } 2016 2017 /// isUsedByReturnOnly - Return true if result of the specified node is used 2018 /// by a return node only. It also compute and return the input chain for the 2019 /// tail call. 2020 /// This is used to determine whether it is possible 2021 /// to codegen a libcall as tail call at legalization time. 2022 virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const { 2023 return false; 2024 } 2025 2026 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the 2027 /// call instruction as a tail call. This is used by optimization passes to 2028 /// determine if it's profitable to duplicate return instructions to enable 2029 /// tailcall optimization. 2030 virtual bool mayBeEmittedAsTailCall(CallInst *) const { 2031 return false; 2032 } 2033 2034 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or 2035 /// sign extend a zeroext/signext integer argument or return value. 2036 /// FIXME: Most C calling convention requires the return type to be promoted, 2037 /// but this is not true all the time, e.g. i1 on x86-64. It is also not 2038 /// necessary for non-C calling conventions. The frontend should handle this 2039 /// and include all of the necessary information. 2040 virtual MVT getTypeForExtArgOrReturn(MVT VT, 2041 ISD::NodeType /*ExtendKind*/) const { 2042 MVT MinVT = getRegisterType(MVT::i32); 2043 return VT.bitsLT(MinVT) ? MinVT : VT; 2044 } 2045 2046 /// LowerOperationWrapper - This callback is invoked by the type legalizer 2047 /// to legalize nodes with an illegal operand type but legal result types. 2048 /// It replaces the LowerOperation callback in the type Legalizer. 2049 /// The reason we can not do away with LowerOperation entirely is that 2050 /// LegalizeDAG isn't yet ready to use this callback. 2051 /// TODO: Consider merging with ReplaceNodeResults. 2052 2053 /// The target places new result values for the node in Results (their number 2054 /// and types must exactly match those of the original return values of 2055 /// the node), or leaves Results empty, which indicates that the node is not 2056 /// to be custom lowered after all. 2057 /// The default implementation calls LowerOperation. 2058 virtual void LowerOperationWrapper(SDNode *N, 2059 SmallVectorImpl<SDValue> &Results, 2060 SelectionDAG &DAG) const; 2061 2062 /// LowerOperation - This callback is invoked for operations that are 2063 /// unsupported by the target, which are registered to use 'custom' lowering, 2064 /// and whose defined values are all legal. 2065 /// If the target has no operations that require custom lowering, it need not 2066 /// implement this. The default implementation of this aborts. 2067 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 2068 2069 /// ReplaceNodeResults - This callback is invoked when a node result type is 2070 /// illegal for the target, and the operation was registered to use 'custom' 2071 /// lowering for that result type. The target places new result values for 2072 /// the node in Results (their number and types must exactly match those of 2073 /// the original return values of the node), or leaves Results empty, which 2074 /// indicates that the node is not to be custom lowered after all. 2075 /// 2076 /// If the target has no operations that require custom lowering, it need not 2077 /// implement this. The default implementation aborts. 2078 virtual void ReplaceNodeResults(SDNode * /*N*/, 2079 SmallVectorImpl<SDValue> &/*Results*/, 2080 SelectionDAG &/*DAG*/) const { 2081 llvm_unreachable("ReplaceNodeResults not implemented for this target!"); 2082 } 2083 2084 /// getTargetNodeName() - This method returns the name of a target specific 2085 /// DAG node. 2086 virtual const char *getTargetNodeName(unsigned Opcode) const; 2087 2088 /// createFastISel - This method returns a target specific FastISel object, 2089 /// or null if the target does not support "fast" ISel. 2090 virtual FastISel *createFastISel(FunctionLoweringInfo &, 2091 const TargetLibraryInfo *) const { 2092 return 0; 2093 } 2094 2095 //===--------------------------------------------------------------------===// 2096 // Inline Asm Support hooks 2097 // 2098 2099 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 2100 /// call to be explicit llvm code if it wants to. This is useful for 2101 /// turning simple inline asms into LLVM intrinsics, which gives the 2102 /// compiler more information about the behavior of the code. 2103 virtual bool ExpandInlineAsm(CallInst *) const { 2104 return false; 2105 } 2106 2107 enum ConstraintType { 2108 C_Register, // Constraint represents specific register(s). 2109 C_RegisterClass, // Constraint represents any of register(s) in class. 2110 C_Memory, // Memory constraint. 2111 C_Other, // Something else. 2112 C_Unknown // Unsupported constraint. 2113 }; 2114 2115 enum ConstraintWeight { 2116 // Generic weights. 2117 CW_Invalid = -1, // No match. 2118 CW_Okay = 0, // Acceptable. 2119 CW_Good = 1, // Good weight. 2120 CW_Better = 2, // Better weight. 2121 CW_Best = 3, // Best weight. 2122 2123 // Well-known weights. 2124 CW_SpecificReg = CW_Okay, // Specific register operands. 2125 CW_Register = CW_Good, // Register operands. 2126 CW_Memory = CW_Better, // Memory operands. 2127 CW_Constant = CW_Best, // Constant operand. 2128 CW_Default = CW_Okay // Default or don't know type. 2129 }; 2130 2131 /// AsmOperandInfo - This contains information for each constraint that we are 2132 /// lowering. 2133 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 2134 /// ConstraintCode - This contains the actual string for the code, like "m". 2135 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 2136 /// most closely matches the operand. 2137 std::string ConstraintCode; 2138 2139 /// ConstraintType - Information about the constraint code, e.g. Register, 2140 /// RegisterClass, Memory, Other, Unknown. 2141 TargetLowering::ConstraintType ConstraintType; 2142 2143 /// CallOperandval - If this is the result output operand or a 2144 /// clobber, this is null, otherwise it is the incoming operand to the 2145 /// CallInst. This gets modified as the asm is processed. 2146 Value *CallOperandVal; 2147 2148 /// ConstraintVT - The ValueType for the operand value. 2149 MVT ConstraintVT; 2150 2151 /// isMatchingInputConstraint - Return true of this is an input operand that 2152 /// is a matching constraint like "4". 2153 bool isMatchingInputConstraint() const; 2154 2155 /// getMatchedOperand - If this is an input matching constraint, this method 2156 /// returns the output operand it matches. 2157 unsigned getMatchedOperand() const; 2158 2159 /// Copy constructor for copying from an AsmOperandInfo. 2160 AsmOperandInfo(const AsmOperandInfo &info) 2161 : InlineAsm::ConstraintInfo(info), 2162 ConstraintCode(info.ConstraintCode), 2163 ConstraintType(info.ConstraintType), 2164 CallOperandVal(info.CallOperandVal), 2165 ConstraintVT(info.ConstraintVT) { 2166 } 2167 2168 /// Copy constructor for copying from a ConstraintInfo. 2169 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 2170 : InlineAsm::ConstraintInfo(info), 2171 ConstraintType(TargetLowering::C_Unknown), 2172 CallOperandVal(0), ConstraintVT(MVT::Other) { 2173 } 2174 }; 2175 2176 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; 2177 2178 /// ParseConstraints - Split up the constraint string from the inline 2179 /// assembly value into the specific constraints and their prefixes, 2180 /// and also tie in the associated operand values. 2181 /// If this returns an empty vector, and if the constraint string itself 2182 /// isn't empty, there was an error parsing. 2183 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; 2184 2185 /// Examine constraint type and operand type and determine a weight value. 2186 /// The operand object must already have been set up with the operand type. 2187 virtual ConstraintWeight getMultipleConstraintMatchWeight( 2188 AsmOperandInfo &info, int maIndex) const; 2189 2190 /// Examine constraint string and operand type and determine a weight value. 2191 /// The operand object must already have been set up with the operand type. 2192 virtual ConstraintWeight getSingleConstraintMatchWeight( 2193 AsmOperandInfo &info, const char *constraint) const; 2194 2195 /// ComputeConstraintToUse - Determines the constraint code and constraint 2196 /// type to use for the specific AsmOperandInfo, setting 2197 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 2198 /// being passed in is available, it can be passed in as Op, otherwise an 2199 /// empty SDValue can be passed. 2200 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2201 SDValue Op, 2202 SelectionDAG *DAG = 0) const; 2203 2204 /// getConstraintType - Given a constraint, return the type of constraint it 2205 /// is for this target. 2206 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 2207 2208 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 2209 /// {edx}), return the register number and the register class for the 2210 /// register. 2211 /// 2212 /// Given a register class constraint, like 'r', if this corresponds directly 2213 /// to an LLVM register class, return a register of 0 and the register class 2214 /// pointer. 2215 /// 2216 /// This should only be used for C_Register constraints. On error, 2217 /// this returns a register number of 0 and a null register class pointer.. 2218 virtual std::pair<unsigned, const TargetRegisterClass*> 2219 getRegForInlineAsmConstraint(const std::string &Constraint, 2220 EVT VT) const; 2221 2222 /// LowerXConstraint - try to replace an X constraint, which matches anything, 2223 /// with another that has more specific requirements based on the type of the 2224 /// corresponding operand. This returns null if there is no replacement to 2225 /// make. 2226 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 2227 2228 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2229 /// vector. If it is invalid, don't add anything to Ops. 2230 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 2231 std::vector<SDValue> &Ops, 2232 SelectionDAG &DAG) const; 2233 2234 //===--------------------------------------------------------------------===// 2235 // Div utility functions 2236 // 2237 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 2238 SelectionDAG &DAG) const; 2239 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2240 std::vector<SDNode*> *Created) const; 2241 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2242 std::vector<SDNode*> *Created) const; 2243 2244 //===--------------------------------------------------------------------===// 2245 // Instruction Emitting Hooks 2246 // 2247 2248 // EmitInstrWithCustomInserter - This method should be implemented by targets 2249 // that mark instructions with the 'usesCustomInserter' flag. These 2250 // instructions are special in various ways, which require special support to 2251 // insert. The specified MachineInstr is created but not inserted into any 2252 // basic blocks, and this method is called to expand it into a sequence of 2253 // instructions, potentially also creating new basic blocks and control flow. 2254 virtual MachineBasicBlock * 2255 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 2256 2257 /// AdjustInstrPostInstrSelection - This method should be implemented by 2258 /// targets that mark instructions with the 'hasPostISelHook' flag. These 2259 /// instructions must be adjusted after instruction selection by target hooks. 2260 /// e.g. To fill in optional defs for ARM 's' setting instructions. 2261 virtual void 2262 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 2263}; 2264 2265/// GetReturnInfo - Given an LLVM IR type and return type attributes, 2266/// compute the return value EVTs and flags, and optionally also 2267/// the offsets, if the return value is being lowered to memory. 2268void GetReturnInfo(Type* ReturnType, AttributeSet attr, 2269 SmallVectorImpl<ISD::OutputArg> &Outs, 2270 const TargetLowering &TLI); 2271 2272} // end llvm namespace 2273 2274#endif 2275