TargetLowering.h revision 7f32156bb9c017b71971c52fac892fa7b9b06dd2
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CodeGen/SelectionDAGNodes.h" 26#include "llvm/CodeGen/RuntimeLibcalls.h" 27#include <map> 28#include <vector> 29 30namespace llvm { 31 class Value; 32 class Function; 33 class TargetMachine; 34 class TargetData; 35 class TargetRegisterClass; 36 class SDNode; 37 class SDOperand; 38 class SelectionDAG; 39 class MachineBasicBlock; 40 class MachineInstr; 41 class VectorType; 42 43//===----------------------------------------------------------------------===// 44/// TargetLowering - This class defines information used to lower LLVM code to 45/// legal SelectionDAG operators that the target instruction selector can accept 46/// natively. 47/// 48/// This class also defines callbacks that targets must implement to lower 49/// target-specific constructs to SelectionDAG operators. 50/// 51class TargetLowering { 52public: 53 /// LegalizeAction - This enum indicates whether operations are valid for a 54 /// target, and if not, what action should be used to make them valid. 55 enum LegalizeAction { 56 Legal, // The target natively supports this operation. 57 Promote, // This operation should be executed in a larger type. 58 Expand, // Try to expand this to other ops, otherwise use a libcall. 59 Custom // Use the LowerOperation hook to implement custom lowering. 60 }; 61 62 enum OutOfRangeShiftAmount { 63 Undefined, // Oversized shift amounts are undefined (default). 64 Mask, // Shift amounts are auto masked (anded) to value size. 65 Extend // Oversized shift pulls in zeros or sign bits. 66 }; 67 68 enum SetCCResultValue { 69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 72 }; 73 74 enum SchedPreference { 75 SchedulingForLatency, // Scheduling for shortest total latency. 76 SchedulingForRegPressure // Scheduling for lowest register pressure. 77 }; 78 79 TargetLowering(TargetMachine &TM); 80 virtual ~TargetLowering(); 81 82 TargetMachine &getTargetMachine() const { return TM; } 83 const TargetData *getTargetData() const { return TD; } 84 85 bool isLittleEndian() const { return IsLittleEndian; } 86 MVT::ValueType getPointerTy() const { return PointerTy; } 87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 89 90 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 91 /// codegen. 92 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 93 94 /// isSelectExpensive - Return true if the select operation is expensive for 95 /// this target. 96 bool isSelectExpensive() const { return SelectIsExpensive; } 97 98 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 99 /// a sequence of several shifts, adds, and multiplies for this target. 100 bool isIntDivCheap() const { return IntDivIsCheap; } 101 102 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 103 /// srl/add/sra. 104 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 105 106 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 107 /// 108 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 109 110 /// getSetCCResultContents - For targets without boolean registers, this flag 111 /// returns information about the contents of the high-bits in the setcc 112 /// result register. 113 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 114 115 /// getSchedulingPreference - Return target scheduling preference. 116 SchedPreference getSchedulingPreference() const { 117 return SchedPreferenceInfo; 118 } 119 120 /// getRegClassFor - Return the register class that should be used for the 121 /// specified value type. This may only be called on legal types. 122 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 123 assert(!MVT::isExtendedValueType(VT)); 124 TargetRegisterClass *RC = RegClassForVT[VT]; 125 assert(RC && "This value type is not natively supported!"); 126 return RC; 127 } 128 129 /// isTypeLegal - Return true if the target has native support for the 130 /// specified value type. This means that it has a register that directly 131 /// holds it without promotions or expansions. 132 bool isTypeLegal(MVT::ValueType VT) const { 133 return !MVT::isExtendedValueType(VT) ? 134 RegClassForVT[VT] != 0 : 135 false; 136 } 137 138 class ValueTypeActionImpl { 139 /// ValueTypeActions - This is a bitvector that contains two bits for each 140 /// value type, where the two bits correspond to the LegalizeAction enum. 141 /// This can be queried with "getTypeAction(VT)". 142 uint32_t ValueTypeActions[2]; 143 public: 144 ValueTypeActionImpl() { 145 ValueTypeActions[0] = ValueTypeActions[1] = 0; 146 } 147 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 148 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 149 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 150 } 151 152 LegalizeAction getTypeAction(MVT::ValueType VT) const { 153 return !MVT::isExtendedValueType(VT) ? 154 (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3) : 155 Expand; 156 } 157 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 158 assert(!MVT::isExtendedValueType(VT)); 159 assert(unsigned(VT >> 4) < 160 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 161 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 162 } 163 }; 164 165 const ValueTypeActionImpl &getValueTypeActions() const { 166 return ValueTypeActions; 167 } 168 169 /// getTypeAction - Return how we should legalize values of this type, either 170 /// it is already legal (return 'Legal') or we need to promote it to a larger 171 /// type (return 'Promote'), or we need to expand it into multiple registers 172 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 173 LegalizeAction getTypeAction(MVT::ValueType VT) const { 174 return ValueTypeActions.getTypeAction(VT); 175 } 176 177 /// getTypeToTransformTo - For types supported by the target, this is an 178 /// identity function. For types that must be promoted to larger types, this 179 /// returns the larger type to promote to. For integer types that are larger 180 /// than the largest integer register, this contains one step in the expansion 181 /// to get to the smaller register. For illegal floating point types, this 182 /// returns the integer type to transform to. 183 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 184 if (MVT::isExtendedValueType(VT)) 185 return MVT::getVectorType(MVT::getVectorElementType(VT), 186 MVT::getVectorNumElements(VT) / 2); 187 188 return TransformToType[VT]; 189 } 190 191 /// getTypeToExpandTo - For types supported by the target, this is an 192 /// identity function. For types that must be expanded (i.e. integer types 193 /// that are larger than the largest integer register or illegal floating 194 /// point types), this returns the largest legal type it will be expanded to. 195 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 196 assert(!MVT::isExtendedValueType(VT)); 197 while (true) { 198 switch (getTypeAction(VT)) { 199 case Legal: 200 return VT; 201 case Expand: 202 VT = getTypeToTransformTo(VT); 203 break; 204 default: 205 assert(false && "Type is not legal nor is it to be expanded!"); 206 return VT; 207 } 208 } 209 return VT; 210 } 211 212 /// getVectorTypeBreakdown - Vector types are broken down into some number of 213 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 214 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 215 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 216 /// 217 /// This method returns the number of registers needed, and the VT for each 218 /// register. It also returns the VT of the VectorType elements before they 219 /// are promoted/expanded. 220 /// 221 unsigned getVectorTypeBreakdown(MVT::ValueType VT, 222 MVT::ValueType &ElementVT, 223 MVT::ValueType &LegalElementVT) const; 224 225 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 226 legal_fpimm_iterator legal_fpimm_begin() const { 227 return LegalFPImmediates.begin(); 228 } 229 legal_fpimm_iterator legal_fpimm_end() const { 230 return LegalFPImmediates.end(); 231 } 232 233 /// isShuffleMaskLegal - Targets can use this to indicate that they only 234 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 235 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 236 /// are assumed to be legal. 237 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 238 return true; 239 } 240 241 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 242 /// used by Targets can use this to indicate if there is a suitable 243 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 244 /// pool entry. 245 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 246 MVT::ValueType EVT, 247 SelectionDAG &DAG) const { 248 return false; 249 } 250 251 /// getOperationAction - Return how this operation should be treated: either 252 /// it is legal, needs to be promoted to a larger size, needs to be 253 /// expanded to some other code sequence, or the target has a custom expander 254 /// for it. 255 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 256 return !MVT::isExtendedValueType(VT) ? 257 (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3) : 258 Expand; 259 } 260 261 /// isOperationLegal - Return true if the specified operation is legal on this 262 /// target. 263 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 264 return getOperationAction(Op, VT) == Legal || 265 getOperationAction(Op, VT) == Custom; 266 } 267 268 /// getLoadXAction - Return how this load with extension should be treated: 269 /// either it is legal, needs to be promoted to a larger size, needs to be 270 /// expanded to some other code sequence, or the target has a custom expander 271 /// for it. 272 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 273 return !MVT::isExtendedValueType(VT) ? 274 (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3) : 275 Expand; 276 } 277 278 /// isLoadXLegal - Return true if the specified load with extension is legal 279 /// on this target. 280 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 281 return getLoadXAction(LType, VT) == Legal || 282 getLoadXAction(LType, VT) == Custom; 283 } 284 285 /// getStoreXAction - Return how this store with truncation should be treated: 286 /// either it is legal, needs to be promoted to a larger size, needs to be 287 /// expanded to some other code sequence, or the target has a custom expander 288 /// for it. 289 LegalizeAction getStoreXAction(MVT::ValueType VT) const { 290 return !MVT::isExtendedValueType(VT) ? 291 (LegalizeAction)((StoreXActions >> (2*VT)) & 3) : 292 Expand; 293 } 294 295 /// isStoreXLegal - Return true if the specified store with truncation is 296 /// legal on this target. 297 bool isStoreXLegal(MVT::ValueType VT) const { 298 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom; 299 } 300 301 /// getIndexedLoadAction - Return how the indexed load should be treated: 302 /// either it is legal, needs to be promoted to a larger size, needs to be 303 /// expanded to some other code sequence, or the target has a custom expander 304 /// for it. 305 LegalizeAction 306 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 307 return !MVT::isExtendedValueType(VT) ? 308 (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3) : 309 Expand; 310 } 311 312 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 313 /// on this target. 314 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 315 return getIndexedLoadAction(IdxMode, VT) == Legal || 316 getIndexedLoadAction(IdxMode, VT) == Custom; 317 } 318 319 /// getIndexedStoreAction - Return how the indexed store should be treated: 320 /// either it is legal, needs to be promoted to a larger size, needs to be 321 /// expanded to some other code sequence, or the target has a custom expander 322 /// for it. 323 LegalizeAction 324 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 325 return !MVT::isExtendedValueType(VT) ? 326 (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3) : 327 Expand; 328 } 329 330 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 331 /// on this target. 332 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 333 return getIndexedStoreAction(IdxMode, VT) == Legal || 334 getIndexedStoreAction(IdxMode, VT) == Custom; 335 } 336 337 /// getTypeToPromoteTo - If the action for this operation is to promote, this 338 /// method returns the ValueType to promote to. 339 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 340 assert(getOperationAction(Op, VT) == Promote && 341 "This operation isn't promoted!"); 342 343 // See if this has an explicit type specified. 344 std::map<std::pair<unsigned, MVT::ValueType>, 345 MVT::ValueType>::const_iterator PTTI = 346 PromoteToType.find(std::make_pair(Op, VT)); 347 if (PTTI != PromoteToType.end()) return PTTI->second; 348 349 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 350 "Cannot autopromote this type, add it with AddPromotedToType."); 351 352 MVT::ValueType NVT = VT; 353 do { 354 NVT = (MVT::ValueType)(NVT+1); 355 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 356 "Didn't find type to promote to!"); 357 } while (!isTypeLegal(NVT) || 358 getOperationAction(Op, NVT) == Promote); 359 return NVT; 360 } 361 362 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 363 /// This is fixed by the LLVM operations except for the pointer size. If 364 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 365 /// counterpart (e.g. structs), otherwise it will assert. 366 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const { 367 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown); 368 return VT == MVT::iPTR ? PointerTy : VT; 369 } 370 371 /// getNumRegisters - Return the number of registers that this ValueType will 372 /// eventually require. This is one for any types promoted to live in larger 373 /// registers, but may be more than one for types (like i64) that are split 374 /// into pieces. 375 unsigned getNumRegisters(MVT::ValueType VT) const { 376 if (!MVT::isExtendedValueType(VT)) 377 return NumRegistersForVT[VT]; 378 379 MVT::ValueType VT1, VT2; 380 return getVectorTypeBreakdown(VT, VT1, VT2); 381 } 382 383 /// hasTargetDAGCombine - If true, the target has custom DAG combine 384 /// transformations that it can perform for the specified node. 385 bool hasTargetDAGCombine(ISD::NodeType NT) const { 386 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 387 } 388 389 /// This function returns the maximum number of store operations permitted 390 /// to replace a call to llvm.memset. The value is set by the target at the 391 /// performance threshold for such a replacement. 392 /// @brief Get maximum # of store operations permitted for llvm.memset 393 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 394 395 /// This function returns the maximum number of store operations permitted 396 /// to replace a call to llvm.memcpy. The value is set by the target at the 397 /// performance threshold for such a replacement. 398 /// @brief Get maximum # of store operations permitted for llvm.memcpy 399 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 400 401 /// This function returns the maximum number of store operations permitted 402 /// to replace a call to llvm.memmove. The value is set by the target at the 403 /// performance threshold for such a replacement. 404 /// @brief Get maximum # of store operations permitted for llvm.memmove 405 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 406 407 /// This function returns true if the target allows unaligned memory accesses. 408 /// This is used, for example, in situations where an array copy/move/set is 409 /// converted to a sequence of store operations. It's use helps to ensure that 410 /// such replacements don't generate code that causes an alignment error 411 /// (trap) on the target machine. 412 /// @brief Determine if the target supports unaligned memory accesses. 413 bool allowsUnalignedMemoryAccesses() const { 414 return allowUnalignedMemoryAccesses; 415 } 416 417 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 418 /// to implement llvm.setjmp. 419 bool usesUnderscoreSetJmp() const { 420 return UseUnderscoreSetJmp; 421 } 422 423 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 424 /// to implement llvm.longjmp. 425 bool usesUnderscoreLongJmp() const { 426 return UseUnderscoreLongJmp; 427 } 428 429 /// getStackPointerRegisterToSaveRestore - If a physical register, this 430 /// specifies the register that llvm.savestack/llvm.restorestack should save 431 /// and restore. 432 unsigned getStackPointerRegisterToSaveRestore() const { 433 return StackPointerRegisterToSaveRestore; 434 } 435 436 /// getExceptionAddressRegister - If a physical register, this returns 437 /// the register that receives the exception address on entry to a landing 438 /// pad. 439 unsigned getExceptionAddressRegister() const { 440 return ExceptionPointerRegister; 441 } 442 443 /// getExceptionSelectorRegister - If a physical register, this returns 444 /// the register that receives the exception typeid on entry to a landing 445 /// pad. 446 unsigned getExceptionSelectorRegister() const { 447 return ExceptionSelectorRegister; 448 } 449 450 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 451 /// set, the default is 200) 452 unsigned getJumpBufSize() const { 453 return JumpBufSize; 454 } 455 456 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 457 /// (if never set, the default is 0) 458 unsigned getJumpBufAlignment() const { 459 return JumpBufAlignment; 460 } 461 462 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 463 /// limit. Any block whose size is greater should not be predicated. 464 virtual unsigned getIfCvtBlockSizeLimit() const { 465 return IfCvtBlockSizeLimit; 466 } 467 468 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 469 /// block to be considered for duplication. Any block whose size is greater 470 /// should not be duplicated to facilitate its predication. 471 virtual unsigned getIfCvtDupBlockSizeLimit() const { 472 return IfCvtDupBlockSizeLimit; 473 } 474 475 /// getPreIndexedAddressParts - returns true by value, base pointer and 476 /// offset pointer and addressing mode by reference if the node's address 477 /// can be legally represented as pre-indexed load / store address. 478 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 479 SDOperand &Offset, 480 ISD::MemIndexedMode &AM, 481 SelectionDAG &DAG) { 482 return false; 483 } 484 485 /// getPostIndexedAddressParts - returns true by value, base pointer and 486 /// offset pointer and addressing mode by reference if this node can be 487 /// combined with a load / store to form a post-indexed load / store. 488 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 489 SDOperand &Base, SDOperand &Offset, 490 ISD::MemIndexedMode &AM, 491 SelectionDAG &DAG) { 492 return false; 493 } 494 495 //===--------------------------------------------------------------------===// 496 // TargetLowering Optimization Methods 497 // 498 499 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 500 /// SDOperands for returning information from TargetLowering to its clients 501 /// that want to combine 502 struct TargetLoweringOpt { 503 SelectionDAG &DAG; 504 SDOperand Old; 505 SDOperand New; 506 507 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 508 509 bool CombineTo(SDOperand O, SDOperand N) { 510 Old = O; 511 New = N; 512 return true; 513 } 514 515 /// ShrinkDemandedConstant - Check to see if the specified operand of the 516 /// specified instruction is a constant integer. If so, check to see if there 517 /// are any bits set in the constant that are not demanded. If so, shrink the 518 /// constant and return true. 519 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 520 }; 521 522 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 523 /// DemandedMask bits of the result of Op are ever used downstream. If we can 524 /// use this information to simplify Op, create a new simplified DAG node and 525 /// return true, returning the original and new nodes in Old and New. 526 /// Otherwise, analyze the expression and return a mask of KnownOne and 527 /// KnownZero bits for the expression (used to simplify the caller). 528 /// The KnownZero/One bits may only be accurate for those bits in the 529 /// DemandedMask. 530 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 531 uint64_t &KnownZero, uint64_t &KnownOne, 532 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 533 534 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 535 /// Mask are known to be either zero or one and return them in the 536 /// KnownZero/KnownOne bitsets. 537 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 538 uint64_t Mask, 539 uint64_t &KnownZero, 540 uint64_t &KnownOne, 541 const SelectionDAG &DAG, 542 unsigned Depth = 0) const; 543 544 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 545 /// targets that want to expose additional information about sign bits to the 546 /// DAG Combiner. 547 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 548 unsigned Depth = 0) const; 549 550 struct DAGCombinerInfo { 551 void *DC; // The DAG Combiner object. 552 bool BeforeLegalize; 553 bool CalledByLegalizer; 554 public: 555 SelectionDAG &DAG; 556 557 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 558 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 559 560 bool isBeforeLegalize() const { return BeforeLegalize; } 561 bool isCalledByLegalizer() const { return CalledByLegalizer; } 562 563 void AddToWorklist(SDNode *N); 564 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 565 SDOperand CombineTo(SDNode *N, SDOperand Res); 566 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 567 }; 568 569 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 570 /// and cc. If it is unable to simplify it, return a null SDOperand. 571 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 572 ISD::CondCode Cond, bool foldBooleans, 573 DAGCombinerInfo &DCI) const; 574 575 /// PerformDAGCombine - This method will be invoked for all target nodes and 576 /// for any target-independent nodes that the target has registered with 577 /// invoke it for. 578 /// 579 /// The semantics are as follows: 580 /// Return Value: 581 /// SDOperand.Val == 0 - No change was made 582 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 583 /// otherwise - N should be replaced by the returned Operand. 584 /// 585 /// In addition, methods provided by DAGCombinerInfo may be used to perform 586 /// more complex transformations. 587 /// 588 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 589 590 //===--------------------------------------------------------------------===// 591 // TargetLowering Configuration Methods - These methods should be invoked by 592 // the derived class constructor to configure this object for the target. 593 // 594 595protected: 596 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 597 /// GOT for PC-relative code. 598 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 599 600 /// setShiftAmountType - Describe the type that should be used for shift 601 /// amounts. This type defaults to the pointer type. 602 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 603 604 /// setSetCCResultType - Describe the type that shoudl be used as the result 605 /// of a setcc operation. This defaults to the pointer type. 606 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 607 608 /// setSetCCResultContents - Specify how the target extends the result of a 609 /// setcc operation in a register. 610 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 611 612 /// setSchedulingPreference - Specify the target scheduling preference. 613 void setSchedulingPreference(SchedPreference Pref) { 614 SchedPreferenceInfo = Pref; 615 } 616 617 /// setShiftAmountFlavor - Describe how the target handles out of range shift 618 /// amounts. 619 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 620 ShiftAmtHandling = OORSA; 621 } 622 623 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 624 /// use _setjmp to implement llvm.setjmp or the non _ version. 625 /// Defaults to false. 626 void setUseUnderscoreSetJmp(bool Val) { 627 UseUnderscoreSetJmp = Val; 628 } 629 630 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 631 /// use _longjmp to implement llvm.longjmp or the non _ version. 632 /// Defaults to false. 633 void setUseUnderscoreLongJmp(bool Val) { 634 UseUnderscoreLongJmp = Val; 635 } 636 637 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 638 /// specifies the register that llvm.savestack/llvm.restorestack should save 639 /// and restore. 640 void setStackPointerRegisterToSaveRestore(unsigned R) { 641 StackPointerRegisterToSaveRestore = R; 642 } 643 644 /// setExceptionPointerRegister - If set to a physical register, this sets 645 /// the register that receives the exception address on entry to a landing 646 /// pad. 647 void setExceptionPointerRegister(unsigned R) { 648 ExceptionPointerRegister = R; 649 } 650 651 /// setExceptionSelectorRegister - If set to a physical register, this sets 652 /// the register that receives the exception typeid on entry to a landing 653 /// pad. 654 void setExceptionSelectorRegister(unsigned R) { 655 ExceptionSelectorRegister = R; 656 } 657 658 /// SelectIsExpensive - Tells the code generator not to expand operations 659 /// into sequences that use the select operations if possible. 660 void setSelectIsExpensive() { SelectIsExpensive = true; } 661 662 /// setIntDivIsCheap - Tells the code generator that integer divide is 663 /// expensive, and if possible, should be replaced by an alternate sequence 664 /// of instructions not containing an integer divide. 665 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 666 667 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 668 /// srl/add/sra for a signed divide by power of two, and let the target handle 669 /// it. 670 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 671 672 /// addRegisterClass - Add the specified register class as an available 673 /// regclass for the specified value type. This indicates the selector can 674 /// handle values of that class natively. 675 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 676 assert(!MVT::isExtendedValueType(VT)); 677 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 678 RegClassForVT[VT] = RC; 679 } 680 681 /// computeRegisterProperties - Once all of the register classes are added, 682 /// this allows us to compute derived properties we expose. 683 void computeRegisterProperties(); 684 685 /// setOperationAction - Indicate that the specified operation does not work 686 /// with the specified type and indicate what to do about it. 687 void setOperationAction(unsigned Op, MVT::ValueType VT, 688 LegalizeAction Action) { 689 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 690 "Table isn't big enough!"); 691 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 692 OpActions[Op] |= (uint64_t)Action << VT*2; 693 } 694 695 /// setLoadXAction - Indicate that the specified load with extension does not 696 /// work with the with specified type and indicate what to do about it. 697 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 698 LegalizeAction Action) { 699 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) && 700 "Table isn't big enough!"); 701 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 702 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 703 } 704 705 /// setStoreXAction - Indicate that the specified store with truncation does 706 /// not work with the with specified type and indicate what to do about it. 707 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) { 708 assert(VT < 32 && "Table isn't big enough!"); 709 StoreXActions &= ~(uint64_t(3UL) << VT*2); 710 StoreXActions |= (uint64_t)Action << VT*2; 711 } 712 713 /// setIndexedLoadAction - Indicate that the specified indexed load does or 714 /// does not work with the with specified type and indicate what to do abort 715 /// it. NOTE: All indexed mode loads are initialized to Expand in 716 /// TargetLowering.cpp 717 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 718 LegalizeAction Action) { 719 assert(VT < 32 && IdxMode < 720 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) && 721 "Table isn't big enough!"); 722 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 723 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 724 } 725 726 /// setIndexedStoreAction - Indicate that the specified indexed store does or 727 /// does not work with the with specified type and indicate what to do about 728 /// it. NOTE: All indexed mode stores are initialized to Expand in 729 /// TargetLowering.cpp 730 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 731 LegalizeAction Action) { 732 assert(VT < 32 && IdxMode < 733 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) && 734 "Table isn't big enough!"); 735 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 736 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 737 } 738 739 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 740 /// promotion code defaults to trying a larger integer/fp until it can find 741 /// one that works. If that default is insufficient, this method can be used 742 /// by the target to override the default. 743 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 744 MVT::ValueType DestVT) { 745 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 746 } 747 748 /// addLegalFPImmediate - Indicate that this target can instruction select 749 /// the specified FP immediate natively. 750 void addLegalFPImmediate(double Imm) { 751 LegalFPImmediates.push_back(Imm); 752 } 753 754 /// setTargetDAGCombine - Targets should invoke this method for each target 755 /// independent node that they want to provide a custom DAG combiner for by 756 /// implementing the PerformDAGCombine virtual method. 757 void setTargetDAGCombine(ISD::NodeType NT) { 758 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 759 } 760 761 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 762 /// bytes); default is 200 763 void setJumpBufSize(unsigned Size) { 764 JumpBufSize = Size; 765 } 766 767 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 768 /// alignment (in bytes); default is 0 769 void setJumpBufAlignment(unsigned Align) { 770 JumpBufAlignment = Align; 771 } 772 773 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 774 /// limit (in number of instructions); default is 2. 775 void setIfCvtBlockSizeLimit(unsigned Limit) { 776 IfCvtBlockSizeLimit = Limit; 777 } 778 779 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 780 /// of instructions) to be considered for code duplication during 781 /// if-conversion; default is 2. 782 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 783 IfCvtDupBlockSizeLimit = Limit; 784 } 785 786public: 787 788 //===--------------------------------------------------------------------===// 789 // Lowering methods - These methods must be implemented by targets so that 790 // the SelectionDAGLowering code knows how to lower these. 791 // 792 793 /// LowerArguments - This hook must be implemented to indicate how we should 794 /// lower the arguments for the specified function, into the specified DAG. 795 virtual std::vector<SDOperand> 796 LowerArguments(Function &F, SelectionDAG &DAG); 797 798 /// LowerCallTo - This hook lowers an abstract call to a function into an 799 /// actual call. This returns a pair of operands. The first element is the 800 /// return value for the function (if RetTy is not VoidTy). The second 801 /// element is the outgoing token chain. 802 struct ArgListEntry { 803 SDOperand Node; 804 const Type* Ty; 805 bool isSExt; 806 bool isZExt; 807 bool isInReg; 808 bool isSRet; 809 810 ArgListEntry():isSExt(false), isZExt(false), isInReg(false), isSRet(false) { }; 811 }; 812 typedef std::vector<ArgListEntry> ArgListTy; 813 virtual std::pair<SDOperand, SDOperand> 814 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 815 bool isVarArg, unsigned CallingConv, bool isTailCall, 816 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 817 818 /// LowerOperation - This callback is invoked for operations that are 819 /// unsupported by the target, which are registered to use 'custom' lowering, 820 /// and whose defined values are all legal. 821 /// If the target has no operations that require custom lowering, it need not 822 /// implement this. The default implementation of this aborts. 823 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 824 825 /// CustomPromoteOperation - This callback is invoked for operations that are 826 /// unsupported by the target, are registered to use 'custom' lowering, and 827 /// whose type needs to be promoted. 828 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 829 830 /// getTargetNodeName() - This method returns the name of a target specific 831 /// DAG node. 832 virtual const char *getTargetNodeName(unsigned Opcode) const; 833 834 //===--------------------------------------------------------------------===// 835 // Inline Asm Support hooks 836 // 837 838 enum ConstraintType { 839 C_Register, // Constraint represents a single register. 840 C_RegisterClass, // Constraint represents one or more registers. 841 C_Memory, // Memory constraint. 842 C_Other, // Something else. 843 C_Unknown // Unsupported constraint. 844 }; 845 846 /// getConstraintType - Given a constraint, return the type of constraint it 847 /// is for this target. 848 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 849 850 851 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 852 /// return a list of registers that can be used to satisfy the constraint. 853 /// This should only be used for C_RegisterClass constraints. 854 virtual std::vector<unsigned> 855 getRegClassForInlineAsmConstraint(const std::string &Constraint, 856 MVT::ValueType VT) const; 857 858 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 859 /// {edx}), return the register number and the register class for the 860 /// register. 861 /// 862 /// Given a register class constraint, like 'r', if this corresponds directly 863 /// to an LLVM register class, return a register of 0 and the register class 864 /// pointer. 865 /// 866 /// This should only be used for C_Register constraints. On error, 867 /// this returns a register number of 0 and a null register class pointer.. 868 virtual std::pair<unsigned, const TargetRegisterClass*> 869 getRegForInlineAsmConstraint(const std::string &Constraint, 870 MVT::ValueType VT) const; 871 872 873 /// isOperandValidForConstraint - Return the specified operand (possibly 874 /// modified) if the specified SDOperand is valid for the specified target 875 /// constraint letter, otherwise return null. 876 virtual SDOperand 877 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter, 878 SelectionDAG &DAG); 879 880 //===--------------------------------------------------------------------===// 881 // Scheduler hooks 882 // 883 884 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 885 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 886 // instructions are special in various ways, which require special support to 887 // insert. The specified MachineInstr is created but not inserted into any 888 // basic blocks, and the scheduler passes ownership of it to this method. 889 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 890 MachineBasicBlock *MBB); 891 892 //===--------------------------------------------------------------------===// 893 // Addressing mode description hooks (used by LSR etc). 894 // 895 896 /// AddrMode - This represents an addressing mode of: 897 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 898 /// If BaseGV is null, there is no BaseGV. 899 /// If BaseOffs is zero, there is no base offset. 900 /// If HasBaseReg is false, there is no base register. 901 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 902 /// no scale. 903 /// 904 struct AddrMode { 905 GlobalValue *BaseGV; 906 int64_t BaseOffs; 907 bool HasBaseReg; 908 int64_t Scale; 909 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 910 }; 911 912 /// isLegalAddressingMode - Return true if the addressing mode represented by 913 /// AM is legal for this target, for a load/store of the specified type. 914 /// TODO: Handle pre/postinc as well. 915 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 916 917 //===--------------------------------------------------------------------===// 918 // Div utility functions 919 // 920 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 921 std::vector<SDNode*>* Created) const; 922 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 923 std::vector<SDNode*>* Created) const; 924 925 926 //===--------------------------------------------------------------------===// 927 // Runtime Library hooks 928 // 929 930 /// setLibcallName - Rename the default libcall routine name for the specified 931 /// libcall. 932 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 933 LibcallRoutineNames[Call] = Name; 934 } 935 936 /// getLibcallName - Get the libcall routine name for the specified libcall. 937 /// 938 const char *getLibcallName(RTLIB::Libcall Call) const { 939 return LibcallRoutineNames[Call]; 940 } 941 942 /// setCmpLibcallCC - Override the default CondCode to be used to test the 943 /// result of the comparison libcall against zero. 944 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 945 CmpLibcallCCs[Call] = CC; 946 } 947 948 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 949 /// the comparison libcall against zero. 950 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 951 return CmpLibcallCCs[Call]; 952 } 953 954private: 955 TargetMachine &TM; 956 const TargetData *TD; 957 958 /// IsLittleEndian - True if this is a little endian target. 959 /// 960 bool IsLittleEndian; 961 962 /// PointerTy - The type to use for pointers, usually i32 or i64. 963 /// 964 MVT::ValueType PointerTy; 965 966 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 967 /// 968 bool UsesGlobalOffsetTable; 969 970 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 971 /// PointerTy is. 972 MVT::ValueType ShiftAmountTy; 973 974 OutOfRangeShiftAmount ShiftAmtHandling; 975 976 /// SelectIsExpensive - Tells the code generator not to expand operations 977 /// into sequences that use the select operations if possible. 978 bool SelectIsExpensive; 979 980 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 981 /// constants into a sequence of muls, adds, and shifts. This is a hack until 982 /// a real cost model is in place. If we ever optimize for size, this will be 983 /// set to true unconditionally. 984 bool IntDivIsCheap; 985 986 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 987 /// srl/add/sra for a signed divide by power of two, and let the target handle 988 /// it. 989 bool Pow2DivIsCheap; 990 991 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 992 /// PointerTy. 993 MVT::ValueType SetCCResultTy; 994 995 /// SetCCResultContents - Information about the contents of the high-bits in 996 /// the result of a setcc comparison operation. 997 SetCCResultValue SetCCResultContents; 998 999 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1000 /// total cycles or lowest register usage. 1001 SchedPreference SchedPreferenceInfo; 1002 1003 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1004 /// llvm.setjmp. Defaults to false. 1005 bool UseUnderscoreSetJmp; 1006 1007 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1008 /// llvm.longjmp. Defaults to false. 1009 bool UseUnderscoreLongJmp; 1010 1011 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1012 unsigned JumpBufSize; 1013 1014 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1015 /// buffers 1016 unsigned JumpBufAlignment; 1017 1018 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1019 /// if-converted. 1020 unsigned IfCvtBlockSizeLimit; 1021 1022 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1023 /// duplicated during if-conversion. 1024 unsigned IfCvtDupBlockSizeLimit; 1025 1026 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1027 /// specifies the register that llvm.savestack/llvm.restorestack should save 1028 /// and restore. 1029 unsigned StackPointerRegisterToSaveRestore; 1030 1031 /// ExceptionPointerRegister - If set to a physical register, this specifies 1032 /// the register that receives the exception address on entry to a landing 1033 /// pad. 1034 unsigned ExceptionPointerRegister; 1035 1036 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1037 /// the register that receives the exception typeid on entry to a landing 1038 /// pad. 1039 unsigned ExceptionSelectorRegister; 1040 1041 /// RegClassForVT - This indicates the default register class to use for 1042 /// each ValueType the target supports natively. 1043 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1044 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1045 1046 /// TransformToType - For any value types we are promoting or expanding, this 1047 /// contains the value type that we are changing to. For Expanded types, this 1048 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1049 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1050 /// by the system, this holds the same type (e.g. i32 -> i32). 1051 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1052 1053 /// OpActions - For each operation and each value type, keep a LegalizeAction 1054 /// that indicates how instruction selection should deal with the operation. 1055 /// Most operations are Legal (aka, supported natively by the target), but 1056 /// operations that are not should be described. Note that operations on 1057 /// non-legal value types are not described here. 1058 uint64_t OpActions[156]; 1059 1060 /// LoadXActions - For each load of load extension type and each value type, 1061 /// keep a LegalizeAction that indicates how instruction selection should deal 1062 /// with the load. 1063 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1064 1065 /// StoreXActions - For each store with truncation of each value type, keep a 1066 /// LegalizeAction that indicates how instruction selection should deal with 1067 /// the store. 1068 uint64_t StoreXActions; 1069 1070 /// IndexedModeActions - For each indexed mode and each value type, keep a 1071 /// pair of LegalizeAction that indicates how instruction selection should 1072 /// deal with the load / store. 1073 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1074 1075 ValueTypeActionImpl ValueTypeActions; 1076 1077 std::vector<double> LegalFPImmediates; 1078 1079 std::vector<std::pair<MVT::ValueType, 1080 TargetRegisterClass*> > AvailableRegClasses; 1081 1082 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1083 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1084 /// which sets a bit in this array. 1085 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1086 1087 /// PromoteToType - For operations that must be promoted to a specific type, 1088 /// this holds the destination type. This map should be sparse, so don't hold 1089 /// it as an array. 1090 /// 1091 /// Targets add entries to this map with AddPromotedToType(..), clients access 1092 /// this with getTypeToPromoteTo(..). 1093 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1094 1095 /// LibcallRoutineNames - Stores the name each libcall. 1096 /// 1097 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1098 1099 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1100 /// of each of the comparison libcall against zero. 1101 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1102 1103protected: 1104 /// When lowering %llvm.memset this field specifies the maximum number of 1105 /// store operations that may be substituted for the call to memset. Targets 1106 /// must set this value based on the cost threshold for that target. Targets 1107 /// should assume that the memset will be done using as many of the largest 1108 /// store operations first, followed by smaller ones, if necessary, per 1109 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1110 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1111 /// store. This only applies to setting a constant array of a constant size. 1112 /// @brief Specify maximum number of store instructions per memset call. 1113 unsigned maxStoresPerMemset; 1114 1115 /// When lowering %llvm.memcpy this field specifies the maximum number of 1116 /// store operations that may be substituted for a call to memcpy. Targets 1117 /// must set this value based on the cost threshold for that target. Targets 1118 /// should assume that the memcpy will be done using as many of the largest 1119 /// store operations first, followed by smaller ones, if necessary, per 1120 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1121 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1122 /// and one 1-byte store. This only applies to copying a constant array of 1123 /// constant size. 1124 /// @brief Specify maximum bytes of store instructions per memcpy call. 1125 unsigned maxStoresPerMemcpy; 1126 1127 /// When lowering %llvm.memmove this field specifies the maximum number of 1128 /// store instructions that may be substituted for a call to memmove. Targets 1129 /// must set this value based on the cost threshold for that target. Targets 1130 /// should assume that the memmove will be done using as many of the largest 1131 /// store operations first, followed by smaller ones, if necessary, per 1132 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1133 /// with 8-bit alignment would result in nine 1-byte stores. This only 1134 /// applies to copying a constant array of constant size. 1135 /// @brief Specify maximum bytes of store instructions per memmove call. 1136 unsigned maxStoresPerMemmove; 1137 1138 /// This field specifies whether the target machine permits unaligned memory 1139 /// accesses. This is used, for example, to determine the size of store 1140 /// operations when copying small arrays and other similar tasks. 1141 /// @brief Indicate whether the target permits unaligned memory accesses. 1142 bool allowUnalignedMemoryAccesses; 1143}; 1144} // end llvm namespace 1145 1146#endif 1147