TargetLowering.h revision 8e59e163db8cd3e7b4c96e438fbedf78bff06707
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CodeGen/SelectionDAGNodes.h" 26#include "llvm/CodeGen/RuntimeLibcalls.h" 27#include <map> 28#include <vector> 29 30namespace llvm { 31 class Value; 32 class Function; 33 class TargetMachine; 34 class TargetData; 35 class TargetRegisterClass; 36 class SDNode; 37 class SDOperand; 38 class SelectionDAG; 39 class MachineBasicBlock; 40 class MachineInstr; 41 class VectorType; 42 43//===----------------------------------------------------------------------===// 44/// TargetLowering - This class defines information used to lower LLVM code to 45/// legal SelectionDAG operators that the target instruction selector can accept 46/// natively. 47/// 48/// This class also defines callbacks that targets must implement to lower 49/// target-specific constructs to SelectionDAG operators. 50/// 51class TargetLowering { 52public: 53 /// LegalizeAction - This enum indicates whether operations are valid for a 54 /// target, and if not, what action should be used to make them valid. 55 enum LegalizeAction { 56 Legal, // The target natively supports this operation. 57 Promote, // This operation should be executed in a larger type. 58 Expand, // Try to expand this to other ops, otherwise use a libcall. 59 Custom // Use the LowerOperation hook to implement custom lowering. 60 }; 61 62 enum OutOfRangeShiftAmount { 63 Undefined, // Oversized shift amounts are undefined (default). 64 Mask, // Shift amounts are auto masked (anded) to value size. 65 Extend // Oversized shift pulls in zeros or sign bits. 66 }; 67 68 enum SetCCResultValue { 69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 72 }; 73 74 enum SchedPreference { 75 SchedulingForLatency, // Scheduling for shortest total latency. 76 SchedulingForRegPressure // Scheduling for lowest register pressure. 77 }; 78 79 TargetLowering(TargetMachine &TM); 80 virtual ~TargetLowering(); 81 82 TargetMachine &getTargetMachine() const { return TM; } 83 const TargetData *getTargetData() const { return TD; } 84 85 bool isLittleEndian() const { return IsLittleEndian; } 86 MVT::ValueType getPointerTy() const { return PointerTy; } 87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 89 90 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 91 /// codegen. 92 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 93 94 /// isSelectExpensive - Return true if the select operation is expensive for 95 /// this target. 96 bool isSelectExpensive() const { return SelectIsExpensive; } 97 98 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 99 /// a sequence of several shifts, adds, and multiplies for this target. 100 bool isIntDivCheap() const { return IntDivIsCheap; } 101 102 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 103 /// srl/add/sra. 104 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 105 106 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 107 /// 108 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 109 110 /// getSetCCResultContents - For targets without boolean registers, this flag 111 /// returns information about the contents of the high-bits in the setcc 112 /// result register. 113 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 114 115 /// getSchedulingPreference - Return target scheduling preference. 116 SchedPreference getSchedulingPreference() const { 117 return SchedPreferenceInfo; 118 } 119 120 /// getRegClassFor - Return the register class that should be used for the 121 /// specified value type. This may only be called on legal types. 122 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 123 TargetRegisterClass *RC = RegClassForVT[VT]; 124 assert(RC && "This value type is not natively supported!"); 125 return RC; 126 } 127 128 /// isTypeLegal - Return true if the target has native support for the 129 /// specified value type. This means that it has a register that directly 130 /// holds it without promotions or expansions. 131 bool isTypeLegal(MVT::ValueType VT) const { 132 return RegClassForVT[VT] != 0; 133 } 134 135 class ValueTypeActionImpl { 136 /// ValueTypeActions - This is a bitvector that contains two bits for each 137 /// value type, where the two bits correspond to the LegalizeAction enum. 138 /// This can be queried with "getTypeAction(VT)". 139 uint32_t ValueTypeActions[2]; 140 public: 141 ValueTypeActionImpl() { 142 ValueTypeActions[0] = ValueTypeActions[1] = 0; 143 } 144 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 145 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 146 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 147 } 148 149 LegalizeAction getTypeAction(MVT::ValueType VT) const { 150 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 151 } 152 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 153 assert(unsigned(VT >> 4) < 154 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 155 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 156 } 157 }; 158 159 const ValueTypeActionImpl &getValueTypeActions() const { 160 return ValueTypeActions; 161 } 162 163 /// getTypeAction - Return how we should legalize values of this type, either 164 /// it is already legal (return 'Legal') or we need to promote it to a larger 165 /// type (return 'Promote'), or we need to expand it into multiple registers 166 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 167 LegalizeAction getTypeAction(MVT::ValueType VT) const { 168 return ValueTypeActions.getTypeAction(VT); 169 } 170 171 /// getTypeToTransformTo - For types supported by the target, this is an 172 /// identity function. For types that must be promoted to larger types, this 173 /// returns the larger type to promote to. For integer types that are larger 174 /// than the largest integer register, this contains one step in the expansion 175 /// to get to the smaller register. For illegal floating point types, this 176 /// returns the integer type to transform to. 177 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 178 return TransformToType[VT]; 179 } 180 181 /// getTypeToExpandTo - For types supported by the target, this is an 182 /// identity function. For types that must be expanded (i.e. integer types 183 /// that are larger than the largest integer register or illegal floating 184 /// point types), this returns the largest legal type it will be expanded to. 185 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 186 while (true) { 187 switch (getTypeAction(VT)) { 188 case Legal: 189 return VT; 190 case Expand: 191 VT = TransformToType[VT]; 192 break; 193 default: 194 assert(false && "Type is not legal nor is it to be expanded!"); 195 return VT; 196 } 197 } 198 return VT; 199 } 200 201 /// getVectorTypeBreakdown - Vector types are broken down into some number of 202 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32 203 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 204 /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86. 205 /// 206 /// This method returns the number of registers needed, and the VT for each 207 /// register. It also returns the VT of the VectorType elements before they 208 /// are promoted/expanded. 209 /// 210 unsigned getVectorTypeBreakdown(const VectorType *PTy, 211 MVT::ValueType &PTyElementVT, 212 MVT::ValueType &PTyLegalElementVT) const; 213 214 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 215 legal_fpimm_iterator legal_fpimm_begin() const { 216 return LegalFPImmediates.begin(); 217 } 218 legal_fpimm_iterator legal_fpimm_end() const { 219 return LegalFPImmediates.end(); 220 } 221 222 /// isShuffleMaskLegal - Targets can use this to indicate that they only 223 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 224 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 225 /// are assumed to be legal. 226 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 227 return true; 228 } 229 230 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 231 /// used by Targets can use this to indicate if there is a suitable 232 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 233 /// pool entry. 234 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 235 MVT::ValueType EVT, 236 SelectionDAG &DAG) const { 237 return false; 238 } 239 240 /// getOperationAction - Return how this operation should be treated: either 241 /// it is legal, needs to be promoted to a larger size, needs to be 242 /// expanded to some other code sequence, or the target has a custom expander 243 /// for it. 244 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 245 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 246 } 247 248 /// isOperationLegal - Return true if the specified operation is legal on this 249 /// target. 250 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 251 return getOperationAction(Op, VT) == Legal || 252 getOperationAction(Op, VT) == Custom; 253 } 254 255 /// getLoadXAction - Return how this load with extension should be treated: 256 /// either it is legal, needs to be promoted to a larger size, needs to be 257 /// expanded to some other code sequence, or the target has a custom expander 258 /// for it. 259 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 260 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3); 261 } 262 263 /// isLoadXLegal - Return true if the specified load with extension is legal 264 /// on this target. 265 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 266 return getLoadXAction(LType, VT) == Legal || 267 getLoadXAction(LType, VT) == Custom; 268 } 269 270 /// getStoreXAction - Return how this store with truncation should be treated: 271 /// either it is legal, needs to be promoted to a larger size, needs to be 272 /// expanded to some other code sequence, or the target has a custom expander 273 /// for it. 274 LegalizeAction getStoreXAction(MVT::ValueType VT) const { 275 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3); 276 } 277 278 /// isStoreXLegal - Return true if the specified store with truncation is 279 /// legal on this target. 280 bool isStoreXLegal(MVT::ValueType VT) const { 281 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom; 282 } 283 284 /// getIndexedLoadAction - Return how the indexed load should be treated: 285 /// either it is legal, needs to be promoted to a larger size, needs to be 286 /// expanded to some other code sequence, or the target has a custom expander 287 /// for it. 288 LegalizeAction 289 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 290 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3); 291 } 292 293 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 294 /// on this target. 295 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 296 return getIndexedLoadAction(IdxMode, VT) == Legal || 297 getIndexedLoadAction(IdxMode, VT) == Custom; 298 } 299 300 /// getIndexedStoreAction - Return how the indexed store should be treated: 301 /// either it is legal, needs to be promoted to a larger size, needs to be 302 /// expanded to some other code sequence, or the target has a custom expander 303 /// for it. 304 LegalizeAction 305 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 306 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3); 307 } 308 309 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 310 /// on this target. 311 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 312 return getIndexedStoreAction(IdxMode, VT) == Legal || 313 getIndexedStoreAction(IdxMode, VT) == Custom; 314 } 315 316 /// getTypeToPromoteTo - If the action for this operation is to promote, this 317 /// method returns the ValueType to promote to. 318 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 319 assert(getOperationAction(Op, VT) == Promote && 320 "This operation isn't promoted!"); 321 322 // See if this has an explicit type specified. 323 std::map<std::pair<unsigned, MVT::ValueType>, 324 MVT::ValueType>::const_iterator PTTI = 325 PromoteToType.find(std::make_pair(Op, VT)); 326 if (PTTI != PromoteToType.end()) return PTTI->second; 327 328 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 329 "Cannot autopromote this type, add it with AddPromotedToType."); 330 331 MVT::ValueType NVT = VT; 332 do { 333 NVT = (MVT::ValueType)(NVT+1); 334 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 335 "Didn't find type to promote to!"); 336 } while (!isTypeLegal(NVT) || 337 getOperationAction(Op, NVT) == Promote); 338 return NVT; 339 } 340 341 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 342 /// This is fixed by the LLVM operations except for the pointer size. 343 MVT::ValueType getValueType(const Type *Ty) const; 344 345 /// getNumElements - Return the number of registers that this ValueType will 346 /// eventually require. This is one for any types promoted to live in larger 347 /// registers, but may be more than one for types (like i64) that are split 348 /// into pieces. 349 unsigned getNumElements(MVT::ValueType VT) const { 350 return NumElementsForVT[VT]; 351 } 352 353 /// hasTargetDAGCombine - If true, the target has custom DAG combine 354 /// transformations that it can perform for the specified node. 355 bool hasTargetDAGCombine(ISD::NodeType NT) const { 356 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 357 } 358 359 /// This function returns the maximum number of store operations permitted 360 /// to replace a call to llvm.memset. The value is set by the target at the 361 /// performance threshold for such a replacement. 362 /// @brief Get maximum # of store operations permitted for llvm.memset 363 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 364 365 /// This function returns the maximum number of store operations permitted 366 /// to replace a call to llvm.memcpy. The value is set by the target at the 367 /// performance threshold for such a replacement. 368 /// @brief Get maximum # of store operations permitted for llvm.memcpy 369 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 370 371 /// This function returns the maximum number of store operations permitted 372 /// to replace a call to llvm.memmove. The value is set by the target at the 373 /// performance threshold for such a replacement. 374 /// @brief Get maximum # of store operations permitted for llvm.memmove 375 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 376 377 /// This function returns true if the target allows unaligned memory accesses. 378 /// This is used, for example, in situations where an array copy/move/set is 379 /// converted to a sequence of store operations. It's use helps to ensure that 380 /// such replacements don't generate code that causes an alignment error 381 /// (trap) on the target machine. 382 /// @brief Determine if the target supports unaligned memory accesses. 383 bool allowsUnalignedMemoryAccesses() const { 384 return allowUnalignedMemoryAccesses; 385 } 386 387 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 388 /// to implement llvm.setjmp. 389 bool usesUnderscoreSetJmp() const { 390 return UseUnderscoreSetJmp; 391 } 392 393 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 394 /// to implement llvm.longjmp. 395 bool usesUnderscoreLongJmp() const { 396 return UseUnderscoreLongJmp; 397 } 398 399 /// getStackPointerRegisterToSaveRestore - If a physical register, this 400 /// specifies the register that llvm.savestack/llvm.restorestack should save 401 /// and restore. 402 unsigned getStackPointerRegisterToSaveRestore() const { 403 return StackPointerRegisterToSaveRestore; 404 } 405 406 /// getExceptionAddressRegister - If a physical register, this returns 407 /// the register that receives the exception address on entry to a landing 408 /// pad. 409 unsigned getExceptionAddressRegister() const { 410 return ExceptionPointerRegister; 411 } 412 413 /// getExceptionSelectorRegister - If a physical register, this returns 414 /// the register that receives the exception typeid on entry to a landing 415 /// pad. 416 unsigned getExceptionSelectorRegister() const { 417 return ExceptionSelectorRegister; 418 } 419 420 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 421 /// set, the default is 200) 422 unsigned getJumpBufSize() const { 423 return JumpBufSize; 424 } 425 426 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 427 /// (if never set, the default is 0) 428 unsigned getJumpBufAlignment() const { 429 return JumpBufAlignment; 430 } 431 432 /// getPreIndexedAddressParts - returns true by value, base pointer and 433 /// offset pointer and addressing mode by reference if the node's address 434 /// can be legally represented as pre-indexed load / store address. 435 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 436 SDOperand &Offset, 437 ISD::MemIndexedMode &AM, 438 SelectionDAG &DAG) { 439 return false; 440 } 441 442 /// getPostIndexedAddressParts - returns true by value, base pointer and 443 /// offset pointer and addressing mode by reference if this node can be 444 /// combined with a load / store to form a post-indexed load / store. 445 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 446 SDOperand &Base, SDOperand &Offset, 447 ISD::MemIndexedMode &AM, 448 SelectionDAG &DAG) { 449 return false; 450 } 451 452 //===--------------------------------------------------------------------===// 453 // TargetLowering Optimization Methods 454 // 455 456 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 457 /// SDOperands for returning information from TargetLowering to its clients 458 /// that want to combine 459 struct TargetLoweringOpt { 460 SelectionDAG &DAG; 461 SDOperand Old; 462 SDOperand New; 463 464 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 465 466 bool CombineTo(SDOperand O, SDOperand N) { 467 Old = O; 468 New = N; 469 return true; 470 } 471 472 /// ShrinkDemandedConstant - Check to see if the specified operand of the 473 /// specified instruction is a constant integer. If so, check to see if there 474 /// are any bits set in the constant that are not demanded. If so, shrink the 475 /// constant and return true. 476 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 477 }; 478 479 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We 480 /// use this predicate to simplify operations downstream. Op and Mask are 481 /// known to be the same type. 482 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0) 483 const; 484 485 /// ComputeMaskedBits - Determine which of the bits specified in Mask are 486 /// known to be either zero or one and return them in the KnownZero/KnownOne 487 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit 488 /// processing. Targets can implement the computeMaskedBitsForTargetNode 489 /// method, to allow target nodes to be understood. 490 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, 491 uint64_t &KnownOne, unsigned Depth = 0) const; 492 493 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 494 /// DemandedMask bits of the result of Op are ever used downstream. If we can 495 /// use this information to simplify Op, create a new simplified DAG node and 496 /// return true, returning the original and new nodes in Old and New. 497 /// Otherwise, analyze the expression and return a mask of KnownOne and 498 /// KnownZero bits for the expression (used to simplify the caller). 499 /// The KnownZero/One bits may only be accurate for those bits in the 500 /// DemandedMask. 501 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 502 uint64_t &KnownZero, uint64_t &KnownOne, 503 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 504 505 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 506 /// Mask are known to be either zero or one and return them in the 507 /// KnownZero/KnownOne bitsets. 508 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 509 uint64_t Mask, 510 uint64_t &KnownZero, 511 uint64_t &KnownOne, 512 unsigned Depth = 0) const; 513 514 /// ComputeNumSignBits - Return the number of times the sign bit of the 515 /// register is replicated into the other bits. We know that at least 1 bit 516 /// is always equal to the sign bit (itself), but other cases can give us 517 /// information. For example, immediately after an "SRA X, 2", we know that 518 /// the top 3 bits are all equal to each other, so we return 3. 519 unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const; 520 521 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 522 /// targets that want to expose additional information about sign bits to the 523 /// DAG Combiner. 524 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 525 unsigned Depth = 0) const; 526 527 struct DAGCombinerInfo { 528 void *DC; // The DAG Combiner object. 529 bool BeforeLegalize; 530 bool CalledByLegalizer; 531 public: 532 SelectionDAG &DAG; 533 534 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 535 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 536 537 bool isBeforeLegalize() const { return BeforeLegalize; } 538 bool isCalledByLegalizer() const { return CalledByLegalizer; } 539 540 void AddToWorklist(SDNode *N); 541 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 542 SDOperand CombineTo(SDNode *N, SDOperand Res); 543 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 544 }; 545 546 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 547 /// and cc. If it is unable to simplify it, return a null SDOperand. 548 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 549 ISD::CondCode Cond, bool foldBooleans, 550 DAGCombinerInfo &DCI) const; 551 552 /// PerformDAGCombine - This method will be invoked for all target nodes and 553 /// for any target-independent nodes that the target has registered with 554 /// invoke it for. 555 /// 556 /// The semantics are as follows: 557 /// Return Value: 558 /// SDOperand.Val == 0 - No change was made 559 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 560 /// otherwise - N should be replaced by the returned Operand. 561 /// 562 /// In addition, methods provided by DAGCombinerInfo may be used to perform 563 /// more complex transformations. 564 /// 565 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 566 567 //===--------------------------------------------------------------------===// 568 // TargetLowering Configuration Methods - These methods should be invoked by 569 // the derived class constructor to configure this object for the target. 570 // 571 572protected: 573 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 574 /// GOT for PC-relative code. 575 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 576 577 /// setShiftAmountType - Describe the type that should be used for shift 578 /// amounts. This type defaults to the pointer type. 579 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 580 581 /// setSetCCResultType - Describe the type that shoudl be used as the result 582 /// of a setcc operation. This defaults to the pointer type. 583 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 584 585 /// setSetCCResultContents - Specify how the target extends the result of a 586 /// setcc operation in a register. 587 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 588 589 /// setSchedulingPreference - Specify the target scheduling preference. 590 void setSchedulingPreference(SchedPreference Pref) { 591 SchedPreferenceInfo = Pref; 592 } 593 594 /// setShiftAmountFlavor - Describe how the target handles out of range shift 595 /// amounts. 596 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 597 ShiftAmtHandling = OORSA; 598 } 599 600 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 601 /// use _setjmp to implement llvm.setjmp or the non _ version. 602 /// Defaults to false. 603 void setUseUnderscoreSetJmp(bool Val) { 604 UseUnderscoreSetJmp = Val; 605 } 606 607 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 608 /// use _longjmp to implement llvm.longjmp or the non _ version. 609 /// Defaults to false. 610 void setUseUnderscoreLongJmp(bool Val) { 611 UseUnderscoreLongJmp = Val; 612 } 613 614 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 615 /// specifies the register that llvm.savestack/llvm.restorestack should save 616 /// and restore. 617 void setStackPointerRegisterToSaveRestore(unsigned R) { 618 StackPointerRegisterToSaveRestore = R; 619 } 620 621 /// setExceptionPointerRegister - If set to a physical register, this sets 622 /// the register that receives the exception address on entry to a landing 623 /// pad. 624 void setExceptionPointerRegister(unsigned R) { 625 ExceptionPointerRegister = R; 626 } 627 628 /// setExceptionSelectorRegister - If set to a physical register, this sets 629 /// the register that receives the exception typeid on entry to a landing 630 /// pad. 631 void setExceptionSelectorRegister(unsigned R) { 632 ExceptionSelectorRegister = R; 633 } 634 635 /// SelectIsExpensive - Tells the code generator not to expand operations 636 /// into sequences that use the select operations if possible. 637 void setSelectIsExpensive() { SelectIsExpensive = true; } 638 639 /// setIntDivIsCheap - Tells the code generator that integer divide is 640 /// expensive, and if possible, should be replaced by an alternate sequence 641 /// of instructions not containing an integer divide. 642 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 643 644 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 645 /// srl/add/sra for a signed divide by power of two, and let the target handle 646 /// it. 647 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 648 649 /// addRegisterClass - Add the specified register class as an available 650 /// regclass for the specified value type. This indicates the selector can 651 /// handle values of that class natively. 652 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 653 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 654 RegClassForVT[VT] = RC; 655 } 656 657 /// computeRegisterProperties - Once all of the register classes are added, 658 /// this allows us to compute derived properties we expose. 659 void computeRegisterProperties(); 660 661 /// setOperationAction - Indicate that the specified operation does not work 662 /// with the specified type and indicate what to do about it. 663 void setOperationAction(unsigned Op, MVT::ValueType VT, 664 LegalizeAction Action) { 665 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 666 "Table isn't big enough!"); 667 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 668 OpActions[Op] |= (uint64_t)Action << VT*2; 669 } 670 671 /// setLoadXAction - Indicate that the specified load with extension does not 672 /// work with the with specified type and indicate what to do about it. 673 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 674 LegalizeAction Action) { 675 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) && 676 "Table isn't big enough!"); 677 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 678 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 679 } 680 681 /// setStoreXAction - Indicate that the specified store with truncation does 682 /// not work with the with specified type and indicate what to do about it. 683 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) { 684 assert(VT < 32 && "Table isn't big enough!"); 685 StoreXActions &= ~(uint64_t(3UL) << VT*2); 686 StoreXActions |= (uint64_t)Action << VT*2; 687 } 688 689 /// setIndexedLoadAction - Indicate that the specified indexed load does or 690 /// does not work with the with specified type and indicate what to do abort 691 /// it. NOTE: All indexed mode loads are initialized to Expand in 692 /// TargetLowering.cpp 693 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 694 LegalizeAction Action) { 695 assert(VT < 32 && IdxMode < 696 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) && 697 "Table isn't big enough!"); 698 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 699 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 700 } 701 702 /// setIndexedStoreAction - Indicate that the specified indexed store does or 703 /// does not work with the with specified type and indicate what to do about 704 /// it. NOTE: All indexed mode stores are initialized to Expand in 705 /// TargetLowering.cpp 706 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 707 LegalizeAction Action) { 708 assert(VT < 32 && IdxMode < 709 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) && 710 "Table isn't big enough!"); 711 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 712 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 713 } 714 715 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 716 /// promotion code defaults to trying a larger integer/fp until it can find 717 /// one that works. If that default is insufficient, this method can be used 718 /// by the target to override the default. 719 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 720 MVT::ValueType DestVT) { 721 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 722 } 723 724 /// addLegalFPImmediate - Indicate that this target can instruction select 725 /// the specified FP immediate natively. 726 void addLegalFPImmediate(double Imm) { 727 LegalFPImmediates.push_back(Imm); 728 } 729 730 /// setTargetDAGCombine - Targets should invoke this method for each target 731 /// independent node that they want to provide a custom DAG combiner for by 732 /// implementing the PerformDAGCombine virtual method. 733 void setTargetDAGCombine(ISD::NodeType NT) { 734 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 735 } 736 737 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 738 /// bytes); default is 200 739 void setJumpBufSize(unsigned Size) { 740 JumpBufSize = Size; 741 } 742 743 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 744 /// alignment (in bytes); default is 0 745 void setJumpBufAlignment(unsigned Align) { 746 JumpBufAlignment = Align; 747 } 748 749public: 750 751 //===--------------------------------------------------------------------===// 752 // Lowering methods - These methods must be implemented by targets so that 753 // the SelectionDAGLowering code knows how to lower these. 754 // 755 756 /// LowerArguments - This hook must be implemented to indicate how we should 757 /// lower the arguments for the specified function, into the specified DAG. 758 virtual std::vector<SDOperand> 759 LowerArguments(Function &F, SelectionDAG &DAG); 760 761 /// LowerCallTo - This hook lowers an abstract call to a function into an 762 /// actual call. This returns a pair of operands. The first element is the 763 /// return value for the function (if RetTy is not VoidTy). The second 764 /// element is the outgoing token chain. 765 struct ArgListEntry { 766 SDOperand Node; 767 const Type* Ty; 768 bool isSExt; 769 bool isZExt; 770 bool isInReg; 771 bool isSRet; 772 773 ArgListEntry():isSExt(false), isZExt(false), isInReg(false), isSRet(false) { }; 774 }; 775 typedef std::vector<ArgListEntry> ArgListTy; 776 virtual std::pair<SDOperand, SDOperand> 777 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 778 bool isVarArg, unsigned CallingConv, bool isTailCall, 779 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 780 781 /// LowerOperation - This callback is invoked for operations that are 782 /// unsupported by the target, which are registered to use 'custom' lowering, 783 /// and whose defined values are all legal. 784 /// If the target has no operations that require custom lowering, it need not 785 /// implement this. The default implementation of this aborts. 786 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 787 788 /// CustomPromoteOperation - This callback is invoked for operations that are 789 /// unsupported by the target, are registered to use 'custom' lowering, and 790 /// whose type needs to be promoted. 791 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 792 793 /// getTargetNodeName() - This method returns the name of a target specific 794 /// DAG node. 795 virtual const char *getTargetNodeName(unsigned Opcode) const; 796 797 //===--------------------------------------------------------------------===// 798 // Inline Asm Support hooks 799 // 800 801 enum ConstraintType { 802 C_Register, // Constraint represents a single register. 803 C_RegisterClass, // Constraint represents one or more registers. 804 C_Memory, // Memory constraint. 805 C_Other, // Something else. 806 C_Unknown // Unsupported constraint. 807 }; 808 809 /// getConstraintType - Given a constraint letter, return the type of 810 /// constraint it is for this target. 811 virtual ConstraintType getConstraintType(char ConstraintLetter) const; 812 813 814 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 815 /// return a list of registers that can be used to satisfy the constraint. 816 /// This should only be used for C_RegisterClass constraints. 817 virtual std::vector<unsigned> 818 getRegClassForInlineAsmConstraint(const std::string &Constraint, 819 MVT::ValueType VT) const; 820 821 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 822 /// {edx}), return the register number and the register class for the 823 /// register. 824 /// 825 /// Given a register class constraint, like 'r', if this corresponds directly 826 /// to an LLVM register class, return a register of 0 and the register class 827 /// pointer. 828 /// 829 /// This should only be used for C_Register constraints. On error, 830 /// this returns a register number of 0 and a null register class pointer.. 831 virtual std::pair<unsigned, const TargetRegisterClass*> 832 getRegForInlineAsmConstraint(const std::string &Constraint, 833 MVT::ValueType VT) const; 834 835 836 /// isOperandValidForConstraint - Return the specified operand (possibly 837 /// modified) if the specified SDOperand is valid for the specified target 838 /// constraint letter, otherwise return null. 839 virtual SDOperand 840 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter, 841 SelectionDAG &DAG); 842 843 //===--------------------------------------------------------------------===// 844 // Scheduler hooks 845 // 846 847 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 848 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 849 // instructions are special in various ways, which require special support to 850 // insert. The specified MachineInstr is created but not inserted into any 851 // basic blocks, and the scheduler passes ownership of it to this method. 852 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 853 MachineBasicBlock *MBB); 854 855 //===--------------------------------------------------------------------===// 856 // Loop Strength Reduction hooks 857 // 858 859 /// isLegalAddressExpression - Return true if the binary expression made up of 860 /// specified opcode, operands, and type can be folded into target addressing 861 /// mode for load / store of the given type. 862 virtual bool isLegalAddressExpression(unsigned Opc, Value *Op0, Value *Op1, 863 const Type *Ty) const; 864 865 /// isLegalAddressImmediate - Return true if the integer value can be used as 866 /// the offset of the target addressing mode for load / store of the given 867 /// type. 868 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const; 869 870 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 871 /// the offset of the target addressing mode. 872 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 873 874 /// isLegalAddressScale - Return true if the integer value can be used as the 875 /// scale of the target addressing mode for load / store of the given type. 876 virtual bool isLegalAddressScale(int64_t S, const Type *Ty) const; 877 878 /// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale 879 /// and V works for isLegalAddressImmediate _and_ both can be applied 880 /// simultaneously to the same instruction. 881 virtual bool isLegalAddressScaleAndImm(int64_t S, int64_t V, 882 const Type* Ty) const; 883 /// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale 884 /// and GV works for isLegalAddressImmediate _and_ both can be applied 885 /// simultaneously to the same instruction. 886 virtual bool isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV) const; 887 888 //===--------------------------------------------------------------------===// 889 // Div utility functions 890 // 891 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 892 std::vector<SDNode*>* Created) const; 893 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 894 std::vector<SDNode*>* Created) const; 895 896 897 //===--------------------------------------------------------------------===// 898 // Runtime Library hooks 899 // 900 901 /// setLibcallName - Rename the default libcall routine name for the specified 902 /// libcall. 903 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 904 LibcallRoutineNames[Call] = Name; 905 } 906 907 /// getLibcallName - Get the libcall routine name for the specified libcall. 908 /// 909 const char *getLibcallName(RTLIB::Libcall Call) const { 910 return LibcallRoutineNames[Call]; 911 } 912 913 /// setCmpLibcallCC - Override the default CondCode to be used to test the 914 /// result of the comparison libcall against zero. 915 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 916 CmpLibcallCCs[Call] = CC; 917 } 918 919 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 920 /// the comparison libcall against zero. 921 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 922 return CmpLibcallCCs[Call]; 923 } 924 925private: 926 TargetMachine &TM; 927 const TargetData *TD; 928 929 /// IsLittleEndian - True if this is a little endian target. 930 /// 931 bool IsLittleEndian; 932 933 /// PointerTy - The type to use for pointers, usually i32 or i64. 934 /// 935 MVT::ValueType PointerTy; 936 937 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 938 /// 939 bool UsesGlobalOffsetTable; 940 941 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 942 /// PointerTy is. 943 MVT::ValueType ShiftAmountTy; 944 945 OutOfRangeShiftAmount ShiftAmtHandling; 946 947 /// SelectIsExpensive - Tells the code generator not to expand operations 948 /// into sequences that use the select operations if possible. 949 bool SelectIsExpensive; 950 951 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 952 /// constants into a sequence of muls, adds, and shifts. This is a hack until 953 /// a real cost model is in place. If we ever optimize for size, this will be 954 /// set to true unconditionally. 955 bool IntDivIsCheap; 956 957 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 958 /// srl/add/sra for a signed divide by power of two, and let the target handle 959 /// it. 960 bool Pow2DivIsCheap; 961 962 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 963 /// PointerTy. 964 MVT::ValueType SetCCResultTy; 965 966 /// SetCCResultContents - Information about the contents of the high-bits in 967 /// the result of a setcc comparison operation. 968 SetCCResultValue SetCCResultContents; 969 970 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 971 /// total cycles or lowest register usage. 972 SchedPreference SchedPreferenceInfo; 973 974 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 975 /// llvm.setjmp. Defaults to false. 976 bool UseUnderscoreSetJmp; 977 978 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 979 /// llvm.longjmp. Defaults to false. 980 bool UseUnderscoreLongJmp; 981 982 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 983 unsigned JumpBufSize; 984 985 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 986 /// buffers 987 unsigned JumpBufAlignment; 988 989 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 990 /// specifies the register that llvm.savestack/llvm.restorestack should save 991 /// and restore. 992 unsigned StackPointerRegisterToSaveRestore; 993 994 /// ExceptionPointerRegister - If set to a physical register, this specifies 995 /// the register that receives the exception address on entry to a landing 996 /// pad. 997 unsigned ExceptionPointerRegister; 998 999 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1000 /// the register that receives the exception typeid on entry to a landing 1001 /// pad. 1002 unsigned ExceptionSelectorRegister; 1003 1004 /// RegClassForVT - This indicates the default register class to use for 1005 /// each ValueType the target supports natively. 1006 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1007 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE]; 1008 1009 /// TransformToType - For any value types we are promoting or expanding, this 1010 /// contains the value type that we are changing to. For Expanded types, this 1011 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1012 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1013 /// by the system, this holds the same type (e.g. i32 -> i32). 1014 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1015 1016 /// OpActions - For each operation and each value type, keep a LegalizeAction 1017 /// that indicates how instruction selection should deal with the operation. 1018 /// Most operations are Legal (aka, supported natively by the target), but 1019 /// operations that are not should be described. Note that operations on 1020 /// non-legal value types are not described here. 1021 uint64_t OpActions[156]; 1022 1023 /// LoadXActions - For each load of load extension type and each value type, 1024 /// keep a LegalizeAction that indicates how instruction selection should deal 1025 /// with the load. 1026 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1027 1028 /// StoreXActions - For each store with truncation of each value type, keep a 1029 /// LegalizeAction that indicates how instruction selection should deal with 1030 /// the store. 1031 uint64_t StoreXActions; 1032 1033 /// IndexedModeActions - For each indexed mode and each value type, keep a 1034 /// pair of LegalizeAction that indicates how instruction selection should 1035 /// deal with the load / store. 1036 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1037 1038 ValueTypeActionImpl ValueTypeActions; 1039 1040 std::vector<double> LegalFPImmediates; 1041 1042 std::vector<std::pair<MVT::ValueType, 1043 TargetRegisterClass*> > AvailableRegClasses; 1044 1045 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1046 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1047 /// which sets a bit in this array. 1048 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1049 1050 /// PromoteToType - For operations that must be promoted to a specific type, 1051 /// this holds the destination type. This map should be sparse, so don't hold 1052 /// it as an array. 1053 /// 1054 /// Targets add entries to this map with AddPromotedToType(..), clients access 1055 /// this with getTypeToPromoteTo(..). 1056 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1057 1058 /// LibcallRoutineNames - Stores the name each libcall. 1059 /// 1060 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1061 1062 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1063 /// of each of the comparison libcall against zero. 1064 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1065 1066protected: 1067 /// When lowering %llvm.memset this field specifies the maximum number of 1068 /// store operations that may be substituted for the call to memset. Targets 1069 /// must set this value based on the cost threshold for that target. Targets 1070 /// should assume that the memset will be done using as many of the largest 1071 /// store operations first, followed by smaller ones, if necessary, per 1072 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1073 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1074 /// store. This only applies to setting a constant array of a constant size. 1075 /// @brief Specify maximum number of store instructions per memset call. 1076 unsigned maxStoresPerMemset; 1077 1078 /// When lowering %llvm.memcpy this field specifies the maximum number of 1079 /// store operations that may be substituted for a call to memcpy. Targets 1080 /// must set this value based on the cost threshold for that target. Targets 1081 /// should assume that the memcpy will be done using as many of the largest 1082 /// store operations first, followed by smaller ones, if necessary, per 1083 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1084 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1085 /// and one 1-byte store. This only applies to copying a constant array of 1086 /// constant size. 1087 /// @brief Specify maximum bytes of store instructions per memcpy call. 1088 unsigned maxStoresPerMemcpy; 1089 1090 /// When lowering %llvm.memmove this field specifies the maximum number of 1091 /// store instructions that may be substituted for a call to memmove. Targets 1092 /// must set this value based on the cost threshold for that target. Targets 1093 /// should assume that the memmove will be done using as many of the largest 1094 /// store operations first, followed by smaller ones, if necessary, per 1095 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1096 /// with 8-bit alignment would result in nine 1-byte stores. This only 1097 /// applies to copying a constant array of constant size. 1098 /// @brief Specify maximum bytes of store instructions per memmove call. 1099 unsigned maxStoresPerMemmove; 1100 1101 /// This field specifies whether the target machine permits unaligned memory 1102 /// accesses. This is used, for example, to determine the size of store 1103 /// operations when copying small arrays and other similar tasks. 1104 /// @brief Indicate whether the target permits unaligned memory accesses. 1105 bool allowUnalignedMemoryAccesses; 1106}; 1107} // end llvm namespace 1108 1109#endif 1110