TargetLowering.h revision 97121ba2afb8d566ff1bf5c4e8fc5d4077940a7f
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/InlineAsm.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/CodeGen/RuntimeLibcalls.h" 28#include "llvm/ADT/APFloat.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallSet.h" 31#include "llvm/ADT/STLExtras.h" 32#include "llvm/CodeGen/DebugLoc.h" 33#include "llvm/Target/TargetMachine.h" 34#include <climits> 35#include <map> 36#include <vector> 37 38namespace llvm { 39 class AllocaInst; 40 class CallInst; 41 class Function; 42 class FastISel; 43 class MachineBasicBlock; 44 class MachineFunction; 45 class MachineFrameInfo; 46 class MachineInstr; 47 class MachineModuleInfo; 48 class DwarfWriter; 49 class SDNode; 50 class SDValue; 51 class SelectionDAG; 52 class TargetData; 53 class TargetMachine; 54 class TargetRegisterClass; 55 class TargetSubtarget; 56 class Value; 57 58 // FIXME: should this be here? 59 namespace TLSModel { 60 enum Model { 61 GeneralDynamic, 62 LocalDynamic, 63 InitialExec, 64 LocalExec 65 }; 66 } 67 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 68 69 70//===----------------------------------------------------------------------===// 71/// TargetLowering - This class defines information used to lower LLVM code to 72/// legal SelectionDAG operators that the target instruction selector can accept 73/// natively. 74/// 75/// This class also defines callbacks that targets must implement to lower 76/// target-specific constructs to SelectionDAG operators. 77/// 78class TargetLowering { 79public: 80 /// LegalizeAction - This enum indicates whether operations are valid for a 81 /// target, and if not, what action should be used to make them valid. 82 enum LegalizeAction { 83 Legal, // The target natively supports this operation. 84 Promote, // This operation should be executed in a larger type. 85 Expand, // Try to expand this to other ops, otherwise use a libcall. 86 Custom // Use the LowerOperation hook to implement custom lowering. 87 }; 88 89 enum OutOfRangeShiftAmount { 90 Undefined, // Oversized shift amounts are undefined (default). 91 Mask, // Shift amounts are auto masked (anded) to value size. 92 Extend // Oversized shift pulls in zeros or sign bits. 93 }; 94 95 enum BooleanContent { // How the target represents true/false values. 96 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 97 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 98 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 99 }; 100 101 enum SchedPreference { 102 SchedulingForLatency, // Scheduling for shortest total latency. 103 SchedulingForRegPressure // Scheduling for lowest register pressure. 104 }; 105 106 explicit TargetLowering(TargetMachine &TM); 107 virtual ~TargetLowering(); 108 109 TargetMachine &getTargetMachine() const { return TM; } 110 const TargetData *getTargetData() const { return TD; } 111 112 bool isBigEndian() const { return !IsLittleEndian; } 113 bool isLittleEndian() const { return IsLittleEndian; } 114 MVT getPointerTy() const { return PointerTy; } 115 MVT getShiftAmountTy() const { return ShiftAmountTy; } 116 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 117 118 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 119 /// codegen. 120 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 121 122 /// isSelectExpensive - Return true if the select operation is expensive for 123 /// this target. 124 bool isSelectExpensive() const { return SelectIsExpensive; } 125 126 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 127 /// a sequence of several shifts, adds, and multiplies for this target. 128 bool isIntDivCheap() const { return IntDivIsCheap; } 129 130 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 131 /// srl/add/sra. 132 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 133 134 /// getSetCCResultType - Return the ValueType of the result of SETCC 135 /// operations. Also used to obtain the target's preferred type for 136 /// the condition operand of SELECT and BRCOND nodes. In the case of 137 /// BRCOND the argument passed is MVT::Other since there are no other 138 /// operands to get a type hint from. 139 virtual MVT getSetCCResultType(MVT VT) const; 140 141 /// getBooleanContents - For targets without i1 registers, this gives the 142 /// nature of the high-bits of boolean values held in types wider than i1. 143 /// "Boolean values" are special true/false values produced by nodes like 144 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 145 /// Not to be confused with general values promoted from i1. 146 BooleanContent getBooleanContents() const { return BooleanContents;} 147 148 /// getSchedulingPreference - Return target scheduling preference. 149 SchedPreference getSchedulingPreference() const { 150 return SchedPreferenceInfo; 151 } 152 153 /// getRegClassFor - Return the register class that should be used for the 154 /// specified value type. This may only be called on legal types. 155 TargetRegisterClass *getRegClassFor(MVT VT) const { 156 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 157 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()]; 158 assert(RC && "This value type is not natively supported!"); 159 return RC; 160 } 161 162 /// isTypeLegal - Return true if the target has native support for the 163 /// specified value type. This means that it has a register that directly 164 /// holds it without promotions or expansions. 165 bool isTypeLegal(MVT VT) const { 166 assert(!VT.isSimple() || 167 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 168 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0; 169 } 170 171 class ValueTypeActionImpl { 172 /// ValueTypeActions - This is a bitvector that contains two bits for each 173 /// value type, where the two bits correspond to the LegalizeAction enum. 174 /// This can be queried with "getTypeAction(VT)". 175 uint32_t ValueTypeActions[2]; 176 public: 177 ValueTypeActionImpl() { 178 ValueTypeActions[0] = ValueTypeActions[1] = 0; 179 } 180 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 181 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 182 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 183 } 184 185 LegalizeAction getTypeAction(MVT VT) const { 186 if (VT.isExtended()) { 187 if (VT.isVector()) { 188 return VT.isPow2VectorType() ? Expand : Promote; 189 } 190 if (VT.isInteger()) 191 // First promote to a power-of-two size, then expand if necessary. 192 return VT == VT.getRoundIntegerType() ? Expand : Promote; 193 assert(0 && "Unsupported extended type!"); 194 return Legal; 195 } 196 unsigned I = VT.getSimpleVT(); 197 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 198 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 199 } 200 void setTypeAction(MVT VT, LegalizeAction Action) { 201 unsigned I = VT.getSimpleVT(); 202 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 203 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 204 } 205 }; 206 207 const ValueTypeActionImpl &getValueTypeActions() const { 208 return ValueTypeActions; 209 } 210 211 /// getTypeAction - Return how we should legalize values of this type, either 212 /// it is already legal (return 'Legal') or we need to promote it to a larger 213 /// type (return 'Promote'), or we need to expand it into multiple registers 214 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 215 LegalizeAction getTypeAction(MVT VT) const { 216 return ValueTypeActions.getTypeAction(VT); 217 } 218 219 /// getTypeToTransformTo - For types supported by the target, this is an 220 /// identity function. For types that must be promoted to larger types, this 221 /// returns the larger type to promote to. For integer types that are larger 222 /// than the largest integer register, this contains one step in the expansion 223 /// to get to the smaller register. For illegal floating point types, this 224 /// returns the integer type to transform to. 225 MVT getTypeToTransformTo(MVT VT) const { 226 if (VT.isSimple()) { 227 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType)); 228 MVT NVT = TransformToType[VT.getSimpleVT()]; 229 assert(getTypeAction(NVT) != Promote && 230 "Promote may not follow Expand or Promote"); 231 return NVT; 232 } 233 234 if (VT.isVector()) { 235 MVT NVT = VT.getPow2VectorType(); 236 if (NVT == VT) { 237 // Vector length is a power of 2 - split to half the size. 238 unsigned NumElts = VT.getVectorNumElements(); 239 MVT EltVT = VT.getVectorElementType(); 240 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2); 241 } 242 // Promote to a power of two size, avoiding multi-step promotion. 243 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 244 } else if (VT.isInteger()) { 245 MVT NVT = VT.getRoundIntegerType(); 246 if (NVT == VT) 247 // Size is a power of two - expand to half the size. 248 return MVT::getIntegerVT(VT.getSizeInBits() / 2); 249 else 250 // Promote to a power of two size, avoiding multi-step promotion. 251 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 252 } 253 assert(0 && "Unsupported extended type!"); 254 return MVT(); // Not reached 255 } 256 257 /// getTypeToExpandTo - For types supported by the target, this is an 258 /// identity function. For types that must be expanded (i.e. integer types 259 /// that are larger than the largest integer register or illegal floating 260 /// point types), this returns the largest legal type it will be expanded to. 261 MVT getTypeToExpandTo(MVT VT) const { 262 assert(!VT.isVector()); 263 while (true) { 264 switch (getTypeAction(VT)) { 265 case Legal: 266 return VT; 267 case Expand: 268 VT = getTypeToTransformTo(VT); 269 break; 270 default: 271 assert(false && "Type is not legal nor is it to be expanded!"); 272 return VT; 273 } 274 } 275 return VT; 276 } 277 278 /// getVectorTypeBreakdown - Vector types are broken down into some number of 279 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 280 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 281 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 282 /// 283 /// This method returns the number of registers needed, and the VT for each 284 /// register. It also returns the VT and quantity of the intermediate values 285 /// before they are promoted/expanded. 286 /// 287 unsigned getVectorTypeBreakdown(MVT VT, 288 MVT &IntermediateVT, 289 unsigned &NumIntermediates, 290 MVT &RegisterVT) const; 291 292 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 293 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 294 /// this is the case, it returns true and store the intrinsic 295 /// information into the IntrinsicInfo that was passed to the function. 296 typedef struct IntrinsicInfo { 297 unsigned opc; // target opcode 298 MVT memVT; // memory VT 299 const Value* ptrVal; // value representing memory location 300 int offset; // offset off of ptrVal 301 unsigned align; // alignment 302 bool vol; // is volatile? 303 bool readMem; // reads memory? 304 bool writeMem; // writes memory? 305 } IntrinisicInfo; 306 307 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 308 CallInst &I, unsigned Intrinsic) { 309 return false; 310 } 311 312 /// getWidenVectorType: given a vector type, returns the type to widen to 313 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 314 /// If there is no vector type that we want to widen to, returns MVT::Other 315 /// When and were to widen is target dependent based on the cost of 316 /// scalarizing vs using the wider vector type. 317 virtual MVT getWidenVectorType(MVT VT) const; 318 319 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 320 legal_fpimm_iterator legal_fpimm_begin() const { 321 return LegalFPImmediates.begin(); 322 } 323 legal_fpimm_iterator legal_fpimm_end() const { 324 return LegalFPImmediates.end(); 325 } 326 327 /// isShuffleMaskLegal - Targets can use this to indicate that they only 328 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 329 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 330 /// are assumed to be legal. 331 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const { 332 return true; 333 } 334 335 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 336 /// used by Targets can use this to indicate if there is a suitable 337 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 338 /// pool entry. 339 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, 340 MVT EVT, 341 SelectionDAG &DAG) const { 342 return false; 343 } 344 345 /// getOperationAction - Return how this operation should be treated: either 346 /// it is legal, needs to be promoted to a larger size, needs to be 347 /// expanded to some other code sequence, or the target has a custom expander 348 /// for it. 349 LegalizeAction getOperationAction(unsigned Op, MVT VT) const { 350 if (VT.isExtended()) return Expand; 351 assert(Op < array_lengthof(OpActions) && 352 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 353 "Table isn't big enough!"); 354 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3); 355 } 356 357 /// isOperationLegalOrCustom - Return true if the specified operation is 358 /// legal on this target or can be made legal with custom lowering. This 359 /// is used to help guide high-level lowering decisions. 360 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const { 361 return (VT == MVT::Other || isTypeLegal(VT)) && 362 (getOperationAction(Op, VT) == Legal || 363 getOperationAction(Op, VT) == Custom); 364 } 365 366 /// isOperationLegal - Return true if the specified operation is legal on this 367 /// target. 368 bool isOperationLegal(unsigned Op, MVT VT) const { 369 return (VT == MVT::Other || isTypeLegal(VT)) && 370 getOperationAction(Op, VT) == Legal; 371 } 372 373 /// getLoadExtAction - Return how this load with extension should be treated: 374 /// either it is legal, needs to be promoted to a larger size, needs to be 375 /// expanded to some other code sequence, or the target has a custom expander 376 /// for it. 377 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const { 378 assert(LType < array_lengthof(LoadExtActions) && 379 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 380 "Table isn't big enough!"); 381 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3); 382 } 383 384 /// isLoadExtLegal - Return true if the specified load with extension is legal 385 /// on this target. 386 bool isLoadExtLegal(unsigned LType, MVT VT) const { 387 return VT.isSimple() && 388 (getLoadExtAction(LType, VT) == Legal || 389 getLoadExtAction(LType, VT) == Custom); 390 } 391 392 /// getTruncStoreAction - Return how this store with truncation should be 393 /// treated: either it is legal, needs to be promoted to a larger size, needs 394 /// to be expanded to some other code sequence, or the target has a custom 395 /// expander for it. 396 LegalizeAction getTruncStoreAction(MVT ValVT, 397 MVT MemVT) const { 398 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 399 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 400 "Table isn't big enough!"); 401 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >> 402 (2*MemVT.getSimpleVT())) & 3); 403 } 404 405 /// isTruncStoreLegal - Return true if the specified store with truncation is 406 /// legal on this target. 407 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const { 408 return isTypeLegal(ValVT) && MemVT.isSimple() && 409 (getTruncStoreAction(ValVT, MemVT) == Legal || 410 getTruncStoreAction(ValVT, MemVT) == Custom); 411 } 412 413 /// getIndexedLoadAction - Return how the indexed load should be treated: 414 /// either it is legal, needs to be promoted to a larger size, needs to be 415 /// expanded to some other code sequence, or the target has a custom expander 416 /// for it. 417 LegalizeAction 418 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 419 assert(IdxMode < array_lengthof(IndexedModeActions[0]) && 420 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 && 421 "Table isn't big enough!"); 422 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> 423 (2*VT.getSimpleVT())) & 3); 424 } 425 426 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 427 /// on this target. 428 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const { 429 return VT.isSimple() && 430 (getIndexedLoadAction(IdxMode, VT) == Legal || 431 getIndexedLoadAction(IdxMode, VT) == Custom); 432 } 433 434 /// getIndexedStoreAction - Return how the indexed store should be treated: 435 /// either it is legal, needs to be promoted to a larger size, needs to be 436 /// expanded to some other code sequence, or the target has a custom expander 437 /// for it. 438 LegalizeAction 439 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 440 assert(IdxMode < array_lengthof(IndexedModeActions[1]) && 441 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 442 "Table isn't big enough!"); 443 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> 444 (2*VT.getSimpleVT())) & 3); 445 } 446 447 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 448 /// on this target. 449 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const { 450 return VT.isSimple() && 451 (getIndexedStoreAction(IdxMode, VT) == Legal || 452 getIndexedStoreAction(IdxMode, VT) == Custom); 453 } 454 455 /// getConvertAction - Return how the conversion should be treated: 456 /// either it is legal, needs to be promoted to a larger size, needs to be 457 /// expanded to some other code sequence, or the target has a custom expander 458 /// for it. 459 LegalizeAction 460 getConvertAction(MVT FromVT, MVT ToVT) const { 461 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 462 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 463 "Table isn't big enough!"); 464 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >> 465 (2*ToVT.getSimpleVT())) & 3); 466 } 467 468 /// isConvertLegal - Return true if the specified conversion is legal 469 /// on this target. 470 bool isConvertLegal(MVT FromVT, MVT ToVT) const { 471 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 472 (getConvertAction(FromVT, ToVT) == Legal || 473 getConvertAction(FromVT, ToVT) == Custom); 474 } 475 476 /// getCondCodeAction - Return how the condition code should be treated: 477 /// either it is legal, needs to be expanded to some other code sequence, 478 /// or the target has a custom expander for it. 479 LegalizeAction 480 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 481 assert((unsigned)CC < array_lengthof(CondCodeActions) && 482 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 483 "Table isn't big enough!"); 484 LegalizeAction Action = (LegalizeAction) 485 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3); 486 assert(Action != Promote && "Can't promote condition code!"); 487 return Action; 488 } 489 490 /// isCondCodeLegal - Return true if the specified condition code is legal 491 /// on this target. 492 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 493 return getCondCodeAction(CC, VT) == Legal || 494 getCondCodeAction(CC, VT) == Custom; 495 } 496 497 498 /// getTypeToPromoteTo - If the action for this operation is to promote, this 499 /// method returns the ValueType to promote to. 500 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 501 assert(getOperationAction(Op, VT) == Promote && 502 "This operation isn't promoted!"); 503 504 // See if this has an explicit type specified. 505 std::map<std::pair<unsigned, MVT::SimpleValueType>, 506 MVT::SimpleValueType>::const_iterator PTTI = 507 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT())); 508 if (PTTI != PromoteToType.end()) return PTTI->second; 509 510 assert((VT.isInteger() || VT.isFloatingPoint()) && 511 "Cannot autopromote this type, add it with AddPromotedToType."); 512 513 MVT NVT = VT; 514 do { 515 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1); 516 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 517 "Didn't find type to promote to!"); 518 } while (!isTypeLegal(NVT) || 519 getOperationAction(Op, NVT) == Promote); 520 return NVT; 521 } 522 523 /// getValueType - Return the MVT corresponding to this LLVM type. 524 /// This is fixed by the LLVM operations except for the pointer size. If 525 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 526 /// counterpart (e.g. structs), otherwise it will assert. 527 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 528 MVT VT = MVT::getMVT(Ty, AllowUnknown); 529 return VT == MVT::iPTR ? PointerTy : VT; 530 } 531 532 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 533 /// function arguments in the caller parameter area. This is the actual 534 /// alignment, not its logarithm. 535 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 536 537 /// getRegisterType - Return the type of registers that this ValueType will 538 /// eventually require. 539 MVT getRegisterType(MVT VT) const { 540 if (VT.isSimple()) { 541 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT)); 542 return RegisterTypeForVT[VT.getSimpleVT()]; 543 } 544 if (VT.isVector()) { 545 MVT VT1, RegisterVT; 546 unsigned NumIntermediates; 547 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 548 return RegisterVT; 549 } 550 if (VT.isInteger()) { 551 return getRegisterType(getTypeToTransformTo(VT)); 552 } 553 assert(0 && "Unsupported extended type!"); 554 return MVT(); // Not reached 555 } 556 557 /// getNumRegisters - Return the number of registers that this ValueType will 558 /// eventually require. This is one for any types promoted to live in larger 559 /// registers, but may be more than one for types (like i64) that are split 560 /// into pieces. For types like i140, which are first promoted then expanded, 561 /// it is the number of registers needed to hold all the bits of the original 562 /// type. For an i140 on a 32 bit machine this means 5 registers. 563 unsigned getNumRegisters(MVT VT) const { 564 if (VT.isSimple()) { 565 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT)); 566 return NumRegistersForVT[VT.getSimpleVT()]; 567 } 568 if (VT.isVector()) { 569 MVT VT1, VT2; 570 unsigned NumIntermediates; 571 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 572 } 573 if (VT.isInteger()) { 574 unsigned BitWidth = VT.getSizeInBits(); 575 unsigned RegWidth = getRegisterType(VT).getSizeInBits(); 576 return (BitWidth + RegWidth - 1) / RegWidth; 577 } 578 assert(0 && "Unsupported extended type!"); 579 return 0; // Not reached 580 } 581 582 /// ShouldShrinkFPConstant - If true, then instruction selection should 583 /// seek to shrink the FP constant of the specified type to a smaller type 584 /// in order to save space and / or reduce runtime. 585 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; } 586 587 /// hasTargetDAGCombine - If true, the target has custom DAG combine 588 /// transformations that it can perform for the specified node. 589 bool hasTargetDAGCombine(ISD::NodeType NT) const { 590 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 591 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 592 } 593 594 /// This function returns the maximum number of store operations permitted 595 /// to replace a call to llvm.memset. The value is set by the target at the 596 /// performance threshold for such a replacement. 597 /// @brief Get maximum # of store operations permitted for llvm.memset 598 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 599 600 /// This function returns the maximum number of store operations permitted 601 /// to replace a call to llvm.memcpy. The value is set by the target at the 602 /// performance threshold for such a replacement. 603 /// @brief Get maximum # of store operations permitted for llvm.memcpy 604 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 605 606 /// This function returns the maximum number of store operations permitted 607 /// to replace a call to llvm.memmove. The value is set by the target at the 608 /// performance threshold for such a replacement. 609 /// @brief Get maximum # of store operations permitted for llvm.memmove 610 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 611 612 /// This function returns true if the target allows unaligned memory accesses. 613 /// This is used, for example, in situations where an array copy/move/set is 614 /// converted to a sequence of store operations. It's use helps to ensure that 615 /// such replacements don't generate code that causes an alignment error 616 /// (trap) on the target machine. 617 /// @brief Determine if the target supports unaligned memory accesses. 618 bool allowsUnalignedMemoryAccesses() const { 619 return allowUnalignedMemoryAccesses; 620 } 621 622 /// getOptimalMemOpType - Returns the target specific optimal type for load 623 /// and store operations as a result of memset, memcpy, and memmove lowering. 624 /// It returns MVT::iAny if SelectionDAG should be responsible for 625 /// determining it. 626 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, 627 bool isSrcConst, bool isSrcStr) const { 628 return MVT::iAny; 629 } 630 631 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 632 /// to implement llvm.setjmp. 633 bool usesUnderscoreSetJmp() const { 634 return UseUnderscoreSetJmp; 635 } 636 637 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 638 /// to implement llvm.longjmp. 639 bool usesUnderscoreLongJmp() const { 640 return UseUnderscoreLongJmp; 641 } 642 643 /// getStackPointerRegisterToSaveRestore - If a physical register, this 644 /// specifies the register that llvm.savestack/llvm.restorestack should save 645 /// and restore. 646 unsigned getStackPointerRegisterToSaveRestore() const { 647 return StackPointerRegisterToSaveRestore; 648 } 649 650 /// getExceptionAddressRegister - If a physical register, this returns 651 /// the register that receives the exception address on entry to a landing 652 /// pad. 653 unsigned getExceptionAddressRegister() const { 654 return ExceptionPointerRegister; 655 } 656 657 /// getExceptionSelectorRegister - If a physical register, this returns 658 /// the register that receives the exception typeid on entry to a landing 659 /// pad. 660 unsigned getExceptionSelectorRegister() const { 661 return ExceptionSelectorRegister; 662 } 663 664 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 665 /// set, the default is 200) 666 unsigned getJumpBufSize() const { 667 return JumpBufSize; 668 } 669 670 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 671 /// (if never set, the default is 0) 672 unsigned getJumpBufAlignment() const { 673 return JumpBufAlignment; 674 } 675 676 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 677 /// limit. Any block whose size is greater should not be predicated. 678 unsigned getIfCvtBlockSizeLimit() const { 679 return IfCvtBlockSizeLimit; 680 } 681 682 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 683 /// block to be considered for duplication. Any block whose size is greater 684 /// should not be duplicated to facilitate its predication. 685 unsigned getIfCvtDupBlockSizeLimit() const { 686 return IfCvtDupBlockSizeLimit; 687 } 688 689 /// getPrefLoopAlignment - return the preferred loop alignment. 690 /// 691 unsigned getPrefLoopAlignment() const { 692 return PrefLoopAlignment; 693 } 694 695 /// getPreIndexedAddressParts - returns true by value, base pointer and 696 /// offset pointer and addressing mode by reference if the node's address 697 /// can be legally represented as pre-indexed load / store address. 698 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 699 SDValue &Offset, 700 ISD::MemIndexedMode &AM, 701 SelectionDAG &DAG) const { 702 return false; 703 } 704 705 /// getPostIndexedAddressParts - returns true by value, base pointer and 706 /// offset pointer and addressing mode by reference if this node can be 707 /// combined with a load / store to form a post-indexed load / store. 708 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 709 SDValue &Base, SDValue &Offset, 710 ISD::MemIndexedMode &AM, 711 SelectionDAG &DAG) const { 712 return false; 713 } 714 715 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 716 /// jumptable. 717 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 718 SelectionDAG &DAG) const; 719 720 /// isOffsetFoldingLegal - Return true if folding a constant offset 721 /// with the given GlobalAddress is legal. It is frequently not legal in 722 /// PIC relocation models. 723 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 724 725 //===--------------------------------------------------------------------===// 726 // TargetLowering Optimization Methods 727 // 728 729 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 730 /// SDValues for returning information from TargetLowering to its clients 731 /// that want to combine 732 struct TargetLoweringOpt { 733 SelectionDAG &DAG; 734 SDValue Old; 735 SDValue New; 736 737 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 738 739 bool CombineTo(SDValue O, SDValue N) { 740 Old = O; 741 New = N; 742 return true; 743 } 744 745 /// ShrinkDemandedConstant - Check to see if the specified operand of the 746 /// specified instruction is a constant integer. If so, check to see if 747 /// there are any bits set in the constant that are not demanded. If so, 748 /// shrink the constant and return true. 749 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 750 751 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 752 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 753 /// cast, but it could be generalized for targets with other types of 754 /// implicit widening casts. 755 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 756 DebugLoc dl); 757 }; 758 759 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 760 /// DemandedMask bits of the result of Op are ever used downstream. If we can 761 /// use this information to simplify Op, create a new simplified DAG node and 762 /// return true, returning the original and new nodes in Old and New. 763 /// Otherwise, analyze the expression and return a mask of KnownOne and 764 /// KnownZero bits for the expression (used to simplify the caller). 765 /// The KnownZero/One bits may only be accurate for those bits in the 766 /// DemandedMask. 767 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 768 APInt &KnownZero, APInt &KnownOne, 769 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 770 771 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 772 /// Mask are known to be either zero or one and return them in the 773 /// KnownZero/KnownOne bitsets. 774 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 775 const APInt &Mask, 776 APInt &KnownZero, 777 APInt &KnownOne, 778 const SelectionDAG &DAG, 779 unsigned Depth = 0) const; 780 781 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 782 /// targets that want to expose additional information about sign bits to the 783 /// DAG Combiner. 784 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 785 unsigned Depth = 0) const; 786 787 struct DAGCombinerInfo { 788 void *DC; // The DAG Combiner object. 789 bool BeforeLegalize; 790 bool CalledByLegalizer; 791 public: 792 SelectionDAG &DAG; 793 794 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 795 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 796 797 bool isBeforeLegalize() const { return BeforeLegalize; } 798 bool isCalledByLegalizer() const { return CalledByLegalizer; } 799 800 void AddToWorklist(SDNode *N); 801 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 802 bool AddTo = true); 803 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 804 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 805 806 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 807 }; 808 809 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 810 /// and cc. If it is unable to simplify it, return a null SDValue. 811 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 812 ISD::CondCode Cond, bool foldBooleans, 813 DAGCombinerInfo &DCI, DebugLoc dl) const; 814 815 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 816 /// node is a GlobalAddress + offset. 817 virtual bool 818 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 819 820 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 821 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the 822 /// location that the 'Base' load is loading from. 823 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist, 824 const MachineFrameInfo *MFI) const; 825 826 /// PerformDAGCombine - This method will be invoked for all target nodes and 827 /// for any target-independent nodes that the target has registered with 828 /// invoke it for. 829 /// 830 /// The semantics are as follows: 831 /// Return Value: 832 /// SDValue.Val == 0 - No change was made 833 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 834 /// otherwise - N should be replaced by the returned Operand. 835 /// 836 /// In addition, methods provided by DAGCombinerInfo may be used to perform 837 /// more complex transformations. 838 /// 839 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 840 841 //===--------------------------------------------------------------------===// 842 // TargetLowering Configuration Methods - These methods should be invoked by 843 // the derived class constructor to configure this object for the target. 844 // 845 846protected: 847 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 848 /// GOT for PC-relative code. 849 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 850 851 /// setShiftAmountType - Describe the type that should be used for shift 852 /// amounts. This type defaults to the pointer type. 853 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 854 855 /// setBooleanContents - Specify how the target extends the result of a 856 /// boolean value from i1 to a wider type. See getBooleanContents. 857 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 858 859 /// setSchedulingPreference - Specify the target scheduling preference. 860 void setSchedulingPreference(SchedPreference Pref) { 861 SchedPreferenceInfo = Pref; 862 } 863 864 /// setShiftAmountFlavor - Describe how the target handles out of range shift 865 /// amounts. 866 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 867 ShiftAmtHandling = OORSA; 868 } 869 870 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 871 /// use _setjmp to implement llvm.setjmp or the non _ version. 872 /// Defaults to false. 873 void setUseUnderscoreSetJmp(bool Val) { 874 UseUnderscoreSetJmp = Val; 875 } 876 877 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 878 /// use _longjmp to implement llvm.longjmp or the non _ version. 879 /// Defaults to false. 880 void setUseUnderscoreLongJmp(bool Val) { 881 UseUnderscoreLongJmp = Val; 882 } 883 884 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 885 /// specifies the register that llvm.savestack/llvm.restorestack should save 886 /// and restore. 887 void setStackPointerRegisterToSaveRestore(unsigned R) { 888 StackPointerRegisterToSaveRestore = R; 889 } 890 891 /// setExceptionPointerRegister - If set to a physical register, this sets 892 /// the register that receives the exception address on entry to a landing 893 /// pad. 894 void setExceptionPointerRegister(unsigned R) { 895 ExceptionPointerRegister = R; 896 } 897 898 /// setExceptionSelectorRegister - If set to a physical register, this sets 899 /// the register that receives the exception typeid on entry to a landing 900 /// pad. 901 void setExceptionSelectorRegister(unsigned R) { 902 ExceptionSelectorRegister = R; 903 } 904 905 /// SelectIsExpensive - Tells the code generator not to expand operations 906 /// into sequences that use the select operations if possible. 907 void setSelectIsExpensive() { SelectIsExpensive = true; } 908 909 /// setIntDivIsCheap - Tells the code generator that integer divide is 910 /// expensive, and if possible, should be replaced by an alternate sequence 911 /// of instructions not containing an integer divide. 912 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 913 914 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 915 /// srl/add/sra for a signed divide by power of two, and let the target handle 916 /// it. 917 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 918 919 /// addRegisterClass - Add the specified register class as an available 920 /// regclass for the specified value type. This indicates the selector can 921 /// handle values of that class natively. 922 void addRegisterClass(MVT VT, TargetRegisterClass *RC) { 923 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 924 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 925 RegClassForVT[VT.getSimpleVT()] = RC; 926 } 927 928 /// computeRegisterProperties - Once all of the register classes are added, 929 /// this allows us to compute derived properties we expose. 930 void computeRegisterProperties(); 931 932 /// setOperationAction - Indicate that the specified operation does not work 933 /// with the specified type and indicate what to do about it. 934 void setOperationAction(unsigned Op, MVT VT, 935 LegalizeAction Action) { 936 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && 937 Op < array_lengthof(OpActions) && "Table isn't big enough!"); 938 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 939 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2; 940 } 941 942 /// setLoadExtAction - Indicate that the specified load with extension does 943 /// not work with the with specified type and indicate what to do about it. 944 void setLoadExtAction(unsigned ExtType, MVT VT, 945 LegalizeAction Action) { 946 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 947 ExtType < array_lengthof(LoadExtActions) && 948 "Table isn't big enough!"); 949 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 950 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2; 951 } 952 953 /// setTruncStoreAction - Indicate that the specified truncating store does 954 /// not work with the with specified type and indicate what to do about it. 955 void setTruncStoreAction(MVT ValVT, MVT MemVT, 956 LegalizeAction Action) { 957 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 958 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 959 "Table isn't big enough!"); 960 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) << 961 MemVT.getSimpleVT()*2); 962 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action << 963 MemVT.getSimpleVT()*2; 964 } 965 966 /// setIndexedLoadAction - Indicate that the specified indexed load does or 967 /// does not work with the with specified type and indicate what to do abort 968 /// it. NOTE: All indexed mode loads are initialized to Expand in 969 /// TargetLowering.cpp 970 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 971 LegalizeAction Action) { 972 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 && 973 IdxMode < array_lengthof(IndexedModeActions[0]) && 974 "Table isn't big enough!"); 975 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 976 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 977 } 978 979 /// setIndexedStoreAction - Indicate that the specified indexed store does or 980 /// does not work with the with specified type and indicate what to do about 981 /// it. NOTE: All indexed mode stores are initialized to Expand in 982 /// TargetLowering.cpp 983 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 984 LegalizeAction Action) { 985 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && 986 IdxMode < array_lengthof(IndexedModeActions[1]) && 987 "Table isn't big enough!"); 988 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 989 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; 990 } 991 992 /// setConvertAction - Indicate that the specified conversion does or does 993 /// not work with the with specified type and indicate what to do about it. 994 void setConvertAction(MVT FromVT, MVT ToVT, 995 LegalizeAction Action) { 996 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 997 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 998 "Table isn't big enough!"); 999 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) << 1000 ToVT.getSimpleVT()*2); 1001 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action << 1002 ToVT.getSimpleVT()*2; 1003 } 1004 1005 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1006 /// supported on the target and indicate what to do about it. 1007 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { 1008 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 1009 (unsigned)CC < array_lengthof(CondCodeActions) && 1010 "Table isn't big enough!"); 1011 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 1012 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2; 1013 } 1014 1015 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1016 /// promotion code defaults to trying a larger integer/fp until it can find 1017 /// one that works. If that default is insufficient, this method can be used 1018 /// by the target to override the default. 1019 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1020 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] = 1021 DestVT.getSimpleVT(); 1022 } 1023 1024 /// addLegalFPImmediate - Indicate that this target can instruction select 1025 /// the specified FP immediate natively. 1026 void addLegalFPImmediate(const APFloat& Imm) { 1027 LegalFPImmediates.push_back(Imm); 1028 } 1029 1030 /// setTargetDAGCombine - Targets should invoke this method for each target 1031 /// independent node that they want to provide a custom DAG combiner for by 1032 /// implementing the PerformDAGCombine virtual method. 1033 void setTargetDAGCombine(ISD::NodeType NT) { 1034 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1035 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1036 } 1037 1038 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1039 /// bytes); default is 200 1040 void setJumpBufSize(unsigned Size) { 1041 JumpBufSize = Size; 1042 } 1043 1044 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1045 /// alignment (in bytes); default is 0 1046 void setJumpBufAlignment(unsigned Align) { 1047 JumpBufAlignment = Align; 1048 } 1049 1050 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1051 /// limit (in number of instructions); default is 2. 1052 void setIfCvtBlockSizeLimit(unsigned Limit) { 1053 IfCvtBlockSizeLimit = Limit; 1054 } 1055 1056 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1057 /// of instructions) to be considered for code duplication during 1058 /// if-conversion; default is 2. 1059 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1060 IfCvtDupBlockSizeLimit = Limit; 1061 } 1062 1063 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1064 /// alignment is zero, it means the target does not care about loop alignment. 1065 void setPrefLoopAlignment(unsigned Align) { 1066 PrefLoopAlignment = Align; 1067 } 1068 1069public: 1070 1071 virtual const TargetSubtarget *getSubtarget() { 1072 assert(0 && "Not Implemented"); 1073 return NULL; // this is here to silence compiler errors 1074 } 1075 //===--------------------------------------------------------------------===// 1076 // Lowering methods - These methods must be implemented by targets so that 1077 // the SelectionDAGLowering code knows how to lower these. 1078 // 1079 1080 /// LowerArguments - This hook must be implemented to indicate how we should 1081 /// lower the arguments for the specified function, into the specified DAG. 1082 virtual void 1083 LowerArguments(Function &F, SelectionDAG &DAG, 1084 SmallVectorImpl<SDValue>& ArgValues, DebugLoc dl); 1085 1086 /// LowerCallTo - This hook lowers an abstract call to a function into an 1087 /// actual call. This returns a pair of operands. The first element is the 1088 /// return value for the function (if RetTy is not VoidTy). The second 1089 /// element is the outgoing token chain. 1090 struct ArgListEntry { 1091 SDValue Node; 1092 const Type* Ty; 1093 bool isSExt : 1; 1094 bool isZExt : 1; 1095 bool isInReg : 1; 1096 bool isSRet : 1; 1097 bool isNest : 1; 1098 bool isByVal : 1; 1099 uint16_t Alignment; 1100 1101 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1102 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1103 }; 1104 typedef std::vector<ArgListEntry> ArgListTy; 1105 virtual std::pair<SDValue, SDValue> 1106 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1107 bool isVarArg, bool isInreg, unsigned CallingConv, 1108 bool isTailCall, SDValue Callee, ArgListTy &Args, 1109 SelectionDAG &DAG, DebugLoc dl); 1110 1111 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1112 /// memcpy. This can be used by targets to provide code sequences for cases 1113 /// that don't fit the target's parameters for simple loads/stores and can be 1114 /// more efficient than using a library call. This function can return a null 1115 /// SDValue if the target declines to use custom code and a different 1116 /// lowering strategy should be used. 1117 /// 1118 /// If AlwaysInline is true, the size is constant and the target should not 1119 /// emit any calls and is strongly encouraged to attempt to emit inline code 1120 /// even if it is beyond the usual threshold because this intrinsic is being 1121 /// expanded in a place where calls are not feasible (e.g. within the prologue 1122 /// for another call). If the target chooses to decline an AlwaysInline 1123 /// request here, legalize will resort to using simple loads and stores. 1124 virtual SDValue 1125 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1126 SDValue Chain, 1127 SDValue Op1, SDValue Op2, 1128 SDValue Op3, unsigned Align, 1129 bool AlwaysInline, 1130 const Value *DstSV, uint64_t DstOff, 1131 const Value *SrcSV, uint64_t SrcOff) { 1132 return SDValue(); 1133 } 1134 1135 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1136 /// memmove. This can be used by targets to provide code sequences for cases 1137 /// that don't fit the target's parameters for simple loads/stores and can be 1138 /// more efficient than using a library call. This function can return a null 1139 /// SDValue if the target declines to use custom code and a different 1140 /// lowering strategy should be used. 1141 virtual SDValue 1142 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, 1143 SDValue Chain, 1144 SDValue Op1, SDValue Op2, 1145 SDValue Op3, unsigned Align, 1146 const Value *DstSV, uint64_t DstOff, 1147 const Value *SrcSV, uint64_t SrcOff) { 1148 return SDValue(); 1149 } 1150 1151 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1152 /// memset. This can be used by targets to provide code sequences for cases 1153 /// that don't fit the target's parameters for simple stores and can be more 1154 /// efficient than using a library call. This function can return a null 1155 /// SDValue if the target declines to use custom code and a different 1156 /// lowering strategy should be used. 1157 virtual SDValue 1158 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 1159 SDValue Chain, 1160 SDValue Op1, SDValue Op2, 1161 SDValue Op3, unsigned Align, 1162 const Value *DstSV, uint64_t DstOff) { 1163 return SDValue(); 1164 } 1165 1166 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1167 /// to legalize nodes with an illegal operand type but legal result types. 1168 /// It replaces the LowerOperation callback in the type Legalizer. 1169 /// The reason we can not do away with LowerOperation entirely is that 1170 /// LegalizeDAG isn't yet ready to use this callback. 1171 /// TODO: Consider merging with ReplaceNodeResults. 1172 1173 /// The target places new result values for the node in Results (their number 1174 /// and types must exactly match those of the original return values of 1175 /// the node), or leaves Results empty, which indicates that the node is not 1176 /// to be custom lowered after all. 1177 /// The default implementation calls LowerOperation. 1178 virtual void LowerOperationWrapper(SDNode *N, 1179 SmallVectorImpl<SDValue> &Results, 1180 SelectionDAG &DAG); 1181 1182 /// LowerOperation - This callback is invoked for operations that are 1183 /// unsupported by the target, which are registered to use 'custom' lowering, 1184 /// and whose defined values are all legal. 1185 /// If the target has no operations that require custom lowering, it need not 1186 /// implement this. The default implementation of this aborts. 1187 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1188 1189 /// ReplaceNodeResults - This callback is invoked when a node result type is 1190 /// illegal for the target, and the operation was registered to use 'custom' 1191 /// lowering for that result type. The target places new result values for 1192 /// the node in Results (their number and types must exactly match those of 1193 /// the original return values of the node), or leaves Results empty, which 1194 /// indicates that the node is not to be custom lowered after all. 1195 /// 1196 /// If the target has no operations that require custom lowering, it need not 1197 /// implement this. The default implementation aborts. 1198 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1199 SelectionDAG &DAG) { 1200 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1201 } 1202 1203 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1204 /// tail call optimization. Targets which want to do tail call optimization 1205 /// should override this function. 1206 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call, 1207 SDValue Ret, 1208 SelectionDAG &DAG) const { 1209 return false; 1210 } 1211 1212 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly 1213 /// preceeds the RET node and whether the return uses the result of the node 1214 /// or is a void return. This function can be used by the target to determine 1215 /// eligiblity of tail call optimization. 1216 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret); 1217 1218 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if 1219 /// it exists. Skip a possible ISD::TokenFactor. 1220 static SDValue GetPossiblePreceedingTailCall(SDValue Chain, 1221 unsigned TailCallNodeOpCode) { 1222 if (Chain.getOpcode() == TailCallNodeOpCode) { 1223 return Chain; 1224 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1225 if (Chain.getNumOperands() && 1226 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode) 1227 return Chain.getOperand(0); 1228 } 1229 return Chain; 1230 } 1231 1232 /// getTargetNodeName() - This method returns the name of a target specific 1233 /// DAG node. 1234 virtual const char *getTargetNodeName(unsigned Opcode) const; 1235 1236 /// createFastISel - This method returns a target specific FastISel object, 1237 /// or null if the target does not support "fast" ISel. 1238 virtual FastISel * 1239 createFastISel(MachineFunction &, 1240 MachineModuleInfo *, DwarfWriter *, 1241 DenseMap<const Value *, unsigned> &, 1242 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1243 DenseMap<const AllocaInst *, int> & 1244#ifndef NDEBUG 1245 , SmallSet<Instruction*, 8> &CatchInfoLost 1246#endif 1247 ) { 1248 return 0; 1249 } 1250 1251 //===--------------------------------------------------------------------===// 1252 // Inline Asm Support hooks 1253 // 1254 1255 enum ConstraintType { 1256 C_Register, // Constraint represents specific register(s). 1257 C_RegisterClass, // Constraint represents any of register(s) in class. 1258 C_Memory, // Memory constraint. 1259 C_Other, // Something else. 1260 C_Unknown // Unsupported constraint. 1261 }; 1262 1263 /// AsmOperandInfo - This contains information for each constraint that we are 1264 /// lowering. 1265 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1266 /// ConstraintCode - This contains the actual string for the code, like "m". 1267 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1268 /// most closely matches the operand. 1269 std::string ConstraintCode; 1270 1271 /// ConstraintType - Information about the constraint code, e.g. Register, 1272 /// RegisterClass, Memory, Other, Unknown. 1273 TargetLowering::ConstraintType ConstraintType; 1274 1275 /// CallOperandval - If this is the result output operand or a 1276 /// clobber, this is null, otherwise it is the incoming operand to the 1277 /// CallInst. This gets modified as the asm is processed. 1278 Value *CallOperandVal; 1279 1280 /// ConstraintVT - The ValueType for the operand value. 1281 MVT ConstraintVT; 1282 1283 /// isMatchingInputConstraint - Return true of this is an input operand that 1284 /// is a matching constraint like "4". 1285 bool isMatchingInputConstraint() const; 1286 1287 /// getMatchedOperand - If this is an input matching constraint, this method 1288 /// returns the output operand it matches. 1289 unsigned getMatchedOperand() const; 1290 1291 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1292 : InlineAsm::ConstraintInfo(info), 1293 ConstraintType(TargetLowering::C_Unknown), 1294 CallOperandVal(0), ConstraintVT(MVT::Other) { 1295 } 1296 }; 1297 1298 /// ComputeConstraintToUse - Determines the constraint code and constraint 1299 /// type to use for the specific AsmOperandInfo, setting 1300 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1301 /// being passed in is available, it can be passed in as Op, otherwise an 1302 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1303 /// constraint of the inline asm instruction being processed is 'm'. 1304 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1305 SDValue Op, 1306 bool hasMemory, 1307 SelectionDAG *DAG = 0) const; 1308 1309 /// getConstraintType - Given a constraint, return the type of constraint it 1310 /// is for this target. 1311 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1312 1313 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1314 /// return a list of registers that can be used to satisfy the constraint. 1315 /// This should only be used for C_RegisterClass constraints. 1316 virtual std::vector<unsigned> 1317 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1318 MVT VT) const; 1319 1320 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1321 /// {edx}), return the register number and the register class for the 1322 /// register. 1323 /// 1324 /// Given a register class constraint, like 'r', if this corresponds directly 1325 /// to an LLVM register class, return a register of 0 and the register class 1326 /// pointer. 1327 /// 1328 /// This should only be used for C_Register constraints. On error, 1329 /// this returns a register number of 0 and a null register class pointer.. 1330 virtual std::pair<unsigned, const TargetRegisterClass*> 1331 getRegForInlineAsmConstraint(const std::string &Constraint, 1332 MVT VT) const; 1333 1334 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1335 /// with another that has more specific requirements based on the type of the 1336 /// corresponding operand. This returns null if there is no replacement to 1337 /// make. 1338 virtual const char *LowerXConstraint(MVT ConstraintVT) const; 1339 1340 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1341 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1342 /// it means one of the asm constraint of the inline asm instruction being 1343 /// processed is 'm'. 1344 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1345 bool hasMemory, 1346 std::vector<SDValue> &Ops, 1347 SelectionDAG &DAG) const; 1348 1349 //===--------------------------------------------------------------------===// 1350 // Scheduler hooks 1351 // 1352 1353 // EmitInstrWithCustomInserter - This method should be implemented by targets 1354 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1355 // instructions are special in various ways, which require special support to 1356 // insert. The specified MachineInstr is created but not inserted into any 1357 // basic blocks, and the scheduler passes ownership of it to this method. 1358 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1359 MachineBasicBlock *MBB) const; 1360 1361 //===--------------------------------------------------------------------===// 1362 // Addressing mode description hooks (used by LSR etc). 1363 // 1364 1365 /// AddrMode - This represents an addressing mode of: 1366 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1367 /// If BaseGV is null, there is no BaseGV. 1368 /// If BaseOffs is zero, there is no base offset. 1369 /// If HasBaseReg is false, there is no base register. 1370 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1371 /// no scale. 1372 /// 1373 struct AddrMode { 1374 GlobalValue *BaseGV; 1375 int64_t BaseOffs; 1376 bool HasBaseReg; 1377 int64_t Scale; 1378 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1379 }; 1380 1381 /// isLegalAddressingMode - Return true if the addressing mode represented by 1382 /// AM is legal for this target, for a load/store of the specified type. 1383 /// TODO: Handle pre/postinc as well. 1384 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1385 1386 /// isTruncateFree - Return true if it's free to truncate a value of 1387 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1388 /// register EAX to i16 by referencing its sub-register AX. 1389 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1390 return false; 1391 } 1392 1393 virtual bool isTruncateFree(MVT VT1, MVT VT2) const { 1394 return false; 1395 } 1396 1397 /// isZExtFree - Return true if any actual instruction that defines a 1398 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 1399 /// register. This does not necessarily include registers defined in 1400 /// unknown ways, such as incoming arguments, or copies from unknown 1401 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1402 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1403 /// all instructions that define 32-bit values implicit zero-extend the 1404 /// result out to 64 bits. 1405 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1406 return false; 1407 } 1408 1409 virtual bool isZExtFree(MVT VT1, MVT VT2) const { 1410 return false; 1411 } 1412 1413 //===--------------------------------------------------------------------===// 1414 // Div utility functions 1415 // 1416 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1417 std::vector<SDNode*>* Created) const; 1418 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1419 std::vector<SDNode*>* Created) const; 1420 1421 1422 //===--------------------------------------------------------------------===// 1423 // Runtime Library hooks 1424 // 1425 1426 /// setLibcallName - Rename the default libcall routine name for the specified 1427 /// libcall. 1428 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1429 LibcallRoutineNames[Call] = Name; 1430 } 1431 1432 /// getLibcallName - Get the libcall routine name for the specified libcall. 1433 /// 1434 const char *getLibcallName(RTLIB::Libcall Call) const { 1435 return LibcallRoutineNames[Call]; 1436 } 1437 1438 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1439 /// result of the comparison libcall against zero. 1440 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1441 CmpLibcallCCs[Call] = CC; 1442 } 1443 1444 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1445 /// the comparison libcall against zero. 1446 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1447 return CmpLibcallCCs[Call]; 1448 } 1449 1450private: 1451 TargetMachine &TM; 1452 const TargetData *TD; 1453 1454 /// PointerTy - The type to use for pointers, usually i32 or i64. 1455 /// 1456 MVT PointerTy; 1457 1458 /// IsLittleEndian - True if this is a little endian target. 1459 /// 1460 bool IsLittleEndian; 1461 1462 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1463 /// 1464 bool UsesGlobalOffsetTable; 1465 1466 /// SelectIsExpensive - Tells the code generator not to expand operations 1467 /// into sequences that use the select operations if possible. 1468 bool SelectIsExpensive; 1469 1470 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1471 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1472 /// a real cost model is in place. If we ever optimize for size, this will be 1473 /// set to true unconditionally. 1474 bool IntDivIsCheap; 1475 1476 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1477 /// srl/add/sra for a signed divide by power of two, and let the target handle 1478 /// it. 1479 bool Pow2DivIsCheap; 1480 1481 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1482 /// llvm.setjmp. Defaults to false. 1483 bool UseUnderscoreSetJmp; 1484 1485 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1486 /// llvm.longjmp. Defaults to false. 1487 bool UseUnderscoreLongJmp; 1488 1489 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1490 /// PointerTy is. 1491 MVT ShiftAmountTy; 1492 1493 OutOfRangeShiftAmount ShiftAmtHandling; 1494 1495 /// BooleanContents - Information about the contents of the high-bits in 1496 /// boolean values held in a type wider than i1. See getBooleanContents. 1497 BooleanContent BooleanContents; 1498 1499 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1500 /// total cycles or lowest register usage. 1501 SchedPreference SchedPreferenceInfo; 1502 1503 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1504 unsigned JumpBufSize; 1505 1506 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1507 /// buffers 1508 unsigned JumpBufAlignment; 1509 1510 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1511 /// if-converted. 1512 unsigned IfCvtBlockSizeLimit; 1513 1514 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1515 /// duplicated during if-conversion. 1516 unsigned IfCvtDupBlockSizeLimit; 1517 1518 /// PrefLoopAlignment - The perferred loop alignment. 1519 /// 1520 unsigned PrefLoopAlignment; 1521 1522 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1523 /// specifies the register that llvm.savestack/llvm.restorestack should save 1524 /// and restore. 1525 unsigned StackPointerRegisterToSaveRestore; 1526 1527 /// ExceptionPointerRegister - If set to a physical register, this specifies 1528 /// the register that receives the exception address on entry to a landing 1529 /// pad. 1530 unsigned ExceptionPointerRegister; 1531 1532 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1533 /// the register that receives the exception typeid on entry to a landing 1534 /// pad. 1535 unsigned ExceptionSelectorRegister; 1536 1537 /// RegClassForVT - This indicates the default register class to use for 1538 /// each ValueType the target supports natively. 1539 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1540 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1541 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1542 1543 /// TransformToType - For any value types we are promoting or expanding, this 1544 /// contains the value type that we are changing to. For Expanded types, this 1545 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1546 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1547 /// by the system, this holds the same type (e.g. i32 -> i32). 1548 MVT TransformToType[MVT::LAST_VALUETYPE]; 1549 1550 /// OpActions - For each operation and each value type, keep a LegalizeAction 1551 /// that indicates how instruction selection should deal with the operation. 1552 /// Most operations are Legal (aka, supported natively by the target), but 1553 /// operations that are not should be described. Note that operations on 1554 /// non-legal value types are not described here. 1555 uint64_t OpActions[ISD::BUILTIN_OP_END]; 1556 1557 /// LoadExtActions - For each load of load extension type and each value type, 1558 /// keep a LegalizeAction that indicates how instruction selection should deal 1559 /// with the load. 1560 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1561 1562 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1563 /// indicates how instruction selection should deal with the store. 1564 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1565 1566 /// IndexedModeActions - For each indexed mode and each value type, keep a 1567 /// pair of LegalizeAction that indicates how instruction selection should 1568 /// deal with the load / store. 1569 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1570 1571 /// ConvertActions - For each conversion from source type to destination type, 1572 /// keep a LegalizeAction that indicates how instruction selection should 1573 /// deal with the conversion. 1574 /// Currently, this is used only for floating->floating conversions 1575 /// (FP_EXTEND and FP_ROUND). 1576 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1577 1578 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1579 /// LegalizeAction that indicates how instruction selection should 1580 /// deal with the condition code. 1581 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1582 1583 ValueTypeActionImpl ValueTypeActions; 1584 1585 std::vector<APFloat> LegalFPImmediates; 1586 1587 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses; 1588 1589 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1590 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1591 /// which sets a bit in this array. 1592 unsigned char 1593 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1594 1595 /// PromoteToType - For operations that must be promoted to a specific type, 1596 /// this holds the destination type. This map should be sparse, so don't hold 1597 /// it as an array. 1598 /// 1599 /// Targets add entries to this map with AddPromotedToType(..), clients access 1600 /// this with getTypeToPromoteTo(..). 1601 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1602 PromoteToType; 1603 1604 /// LibcallRoutineNames - Stores the name each libcall. 1605 /// 1606 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1607 1608 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1609 /// of each of the comparison libcall against zero. 1610 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1611 1612protected: 1613 /// When lowering \@llvm.memset this field specifies the maximum number of 1614 /// store operations that may be substituted for the call to memset. Targets 1615 /// must set this value based on the cost threshold for that target. Targets 1616 /// should assume that the memset will be done using as many of the largest 1617 /// store operations first, followed by smaller ones, if necessary, per 1618 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1619 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1620 /// store. This only applies to setting a constant array of a constant size. 1621 /// @brief Specify maximum number of store instructions per memset call. 1622 unsigned maxStoresPerMemset; 1623 1624 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1625 /// store operations that may be substituted for a call to memcpy. Targets 1626 /// must set this value based on the cost threshold for that target. Targets 1627 /// should assume that the memcpy will be done using as many of the largest 1628 /// store operations first, followed by smaller ones, if necessary, per 1629 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1630 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1631 /// and one 1-byte store. This only applies to copying a constant array of 1632 /// constant size. 1633 /// @brief Specify maximum bytes of store instructions per memcpy call. 1634 unsigned maxStoresPerMemcpy; 1635 1636 /// When lowering \@llvm.memmove this field specifies the maximum number of 1637 /// store instructions that may be substituted for a call to memmove. Targets 1638 /// must set this value based on the cost threshold for that target. Targets 1639 /// should assume that the memmove will be done using as many of the largest 1640 /// store operations first, followed by smaller ones, if necessary, per 1641 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1642 /// with 8-bit alignment would result in nine 1-byte stores. This only 1643 /// applies to copying a constant array of constant size. 1644 /// @brief Specify maximum bytes of store instructions per memmove call. 1645 unsigned maxStoresPerMemmove; 1646 1647 /// This field specifies whether the target machine permits unaligned memory 1648 /// accesses. This is used, for example, to determine the size of store 1649 /// operations when copying small arrays and other similar tasks. 1650 /// @brief Indicate whether the target permits unaligned memory accesses. 1651 bool allowUnalignedMemoryAccesses; 1652}; 1653} // end llvm namespace 1654 1655#endif 1656