TargetLowering.h revision a61b17c18a67f1b3faef2f2108379c4337ce9bb7
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/ADT/DenseMap.h" 26#include "llvm/AddressingMode.h" 27#include "llvm/Attributes.h" 28#include "llvm/CallingConv.h" 29#include "llvm/CodeGen/RuntimeLibcalls.h" 30#include "llvm/CodeGen/SelectionDAGNodes.h" 31#include "llvm/InlineAsm.h" 32#include "llvm/Support/CallSite.h" 33#include "llvm/Support/DebugLoc.h" 34#include "llvm/Target/TargetCallingConv.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class CallInst; 42 class CCState; 43 class FastISel; 44 class FunctionLoweringInfo; 45 class ImmutableCallSite; 46 class IntrinsicInst; 47 class MachineBasicBlock; 48 class MachineFunction; 49 class MachineInstr; 50 class MachineJumpTableInfo; 51 class MCContext; 52 class MCExpr; 53 template<typename T> class SmallVectorImpl; 54 class DataLayout; 55 class TargetRegisterClass; 56 class TargetLibraryInfo; 57 class TargetLoweringObjectFile; 58 class Value; 59 60 namespace Sched { 61 enum Preference { 62 None, // No preference 63 Source, // Follow source order. 64 RegPressure, // Scheduling for lowest register pressure. 65 Hybrid, // Scheduling for both latency and register pressure. 66 ILP, // Scheduling for ILP in low register pressure mode. 67 VLIW // Scheduling for VLIW targets. 68 }; 69 } 70 71 72//===----------------------------------------------------------------------===// 73/// TargetLowering - This class defines information used to lower LLVM code to 74/// legal SelectionDAG operators that the target instruction selector can accept 75/// natively. 76/// 77/// This class also defines callbacks that targets must implement to lower 78/// target-specific constructs to SelectionDAG operators. 79/// 80class TargetLowering { 81 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION; 82 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION; 83public: 84 /// LegalizeAction - This enum indicates whether operations are valid for a 85 /// target, and if not, what action should be used to make them valid. 86 enum LegalizeAction { 87 Legal, // The target natively supports this operation. 88 Promote, // This operation should be executed in a larger type. 89 Expand, // Try to expand this to other ops, otherwise use a libcall. 90 Custom // Use the LowerOperation hook to implement custom lowering. 91 }; 92 93 /// LegalizeTypeAction - This enum indicates whether a types are legal for a 94 /// target, and if not, what action should be used to make them valid. 95 enum LegalizeTypeAction { 96 TypeLegal, // The target natively supports this type. 97 TypePromoteInteger, // Replace this integer with a larger one. 98 TypeExpandInteger, // Split this integer into two of half the size. 99 TypeSoftenFloat, // Convert this float to a same size integer type. 100 TypeExpandFloat, // Split this float into two of half the size. 101 TypeScalarizeVector, // Replace this one-element vector with its element. 102 TypeSplitVector, // Split this vector into two of half the size. 103 TypeWidenVector // This vector should be widened into a larger vector. 104 }; 105 106 /// LegalizeKind holds the legalization kind that needs to happen to EVT 107 /// in order to type-legalize it. 108 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; 109 110 enum BooleanContent { // How the target represents true/false values. 111 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 112 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 113 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 114 }; 115 116 enum SelectSupportKind { 117 ScalarValSelect, // The target supports scalar selects (ex: cmov). 118 ScalarCondVectorVal, // The target supports selects with a scalar condition 119 // and vector values (ex: cmov). 120 VectorMaskSelect // The target supports vector selects with a vector 121 // mask (ex: x86 blends). 122 }; 123 124 static ISD::NodeType getExtendForContent(BooleanContent Content) { 125 switch (Content) { 126 case UndefinedBooleanContent: 127 // Extend by adding rubbish bits. 128 return ISD::ANY_EXTEND; 129 case ZeroOrOneBooleanContent: 130 // Extend by adding zero bits. 131 return ISD::ZERO_EXTEND; 132 case ZeroOrNegativeOneBooleanContent: 133 // Extend by copying the sign bit. 134 return ISD::SIGN_EXTEND; 135 } 136 llvm_unreachable("Invalid content kind"); 137 } 138 139 /// NOTE: The constructor takes ownership of TLOF. 140 explicit TargetLowering(const TargetMachine &TM, 141 const TargetLoweringObjectFile *TLOF); 142 virtual ~TargetLowering(); 143 144 const TargetMachine &getTargetMachine() const { return TM; } 145 const DataLayout *getDataLayout() const { return TD; } 146 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 147 148 bool isBigEndian() const { return !IsLittleEndian; } 149 bool isLittleEndian() const { return IsLittleEndian; } 150 // Return the pointer type for the given address space, defaults to 151 // the pointer type from the data layout. 152 // FIXME: The default needs to be removed once all the code is updated. 153 virtual MVT getPointerTy(uint32_t AS = 0) const { return PointerTy; } 154 virtual MVT getShiftAmountTy(EVT LHSTy) const; 155 156 /// isSelectExpensive - Return true if the select operation is expensive for 157 /// this target. 158 bool isSelectExpensive() const { return SelectIsExpensive; } 159 160 virtual bool isSelectSupported(SelectSupportKind kind) const { return true; } 161 162 /// shouldSplitVectorElementType - Return true if a vector of the given type 163 /// should be split (TypeSplitVector) instead of promoted 164 /// (TypePromoteInteger) during type legalization. 165 virtual bool shouldSplitVectorElementType(EVT VT) const { return false; } 166 167 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 168 /// a sequence of several shifts, adds, and multiplies for this target. 169 bool isIntDivCheap() const { return IntDivIsCheap; } 170 171 /// isSlowDivBypassed - Returns true if target has indicated at least one 172 /// type should be bypassed. 173 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); } 174 175 /// getBypassSlowDivTypes - Returns map of slow types for division or 176 /// remainder with corresponding fast types 177 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const { 178 return BypassSlowDivWidths; 179 } 180 181 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 182 /// srl/add/sra. 183 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 184 185 /// isJumpExpensive() - Return true if Flow Control is an expensive operation 186 /// that should be avoided. 187 bool isJumpExpensive() const { return JumpIsExpensive; } 188 189 /// isPredictableSelectExpensive - Return true if selects are only cheaper 190 /// than branches if the branch is unlikely to be predicted right. 191 bool isPredictableSelectExpensive() const { 192 return predictableSelectIsExpensive; 193 } 194 195 /// getSetCCResultType - Return the ValueType of the result of SETCC 196 /// operations. Also used to obtain the target's preferred type for 197 /// the condition operand of SELECT and BRCOND nodes. In the case of 198 /// BRCOND the argument passed is MVT::Other since there are no other 199 /// operands to get a type hint from. 200 virtual EVT getSetCCResultType(EVT VT) const; 201 202 /// getCmpLibcallReturnType - Return the ValueType for comparison 203 /// libcalls. Comparions libcalls include floating point comparion calls, 204 /// and Ordered/Unordered check calls on floating point numbers. 205 virtual 206 MVT::SimpleValueType getCmpLibcallReturnType() const; 207 208 /// getBooleanContents - For targets without i1 registers, this gives the 209 /// nature of the high-bits of boolean values held in types wider than i1. 210 /// "Boolean values" are special true/false values produced by nodes like 211 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 212 /// Not to be confused with general values promoted from i1. 213 /// Some cpus distinguish between vectors of boolean and scalars; the isVec 214 /// parameter selects between the two kinds. For example on X86 a scalar 215 /// boolean should be zero extended from i1, while the elements of a vector 216 /// of booleans should be sign extended from i1. 217 BooleanContent getBooleanContents(bool isVec) const { 218 return isVec ? BooleanVectorContents : BooleanContents; 219 } 220 221 /// getSchedulingPreference - Return target scheduling preference. 222 Sched::Preference getSchedulingPreference() const { 223 return SchedPreferenceInfo; 224 } 225 226 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 227 /// different scheduling heuristics for different nodes. This function returns 228 /// the preference (or none) for the given node. 229 virtual Sched::Preference getSchedulingPreference(SDNode *) const { 230 return Sched::None; 231 } 232 233 /// getRegClassFor - Return the register class that should be used for the 234 /// specified value type. 235 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { 236 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 237 assert(RC && "This value type is not natively supported!"); 238 return RC; 239 } 240 241 /// getRepRegClassFor - Return the 'representative' register class for the 242 /// specified value type. The 'representative' register class is the largest 243 /// legal super-reg register class for the register class of the value type. 244 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 245 /// while the rep register class is GR64 on x86_64. 246 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { 247 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!"); 248 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; 249 return RC; 250 } 251 252 /// getRepRegClassCostFor - Return the cost of the 'representative' register 253 /// class for the specified value type. 254 virtual uint8_t getRepRegClassCostFor(EVT VT) const { 255 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!"); 256 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; 257 } 258 259 /// isTypeLegal - Return true if the target has native support for the 260 /// specified value type. This means that it has a register that directly 261 /// holds it without promotions or expansions. 262 bool isTypeLegal(EVT VT) const { 263 assert(!VT.isSimple() || 264 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 265 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 266 } 267 268 class ValueTypeActionImpl { 269 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum 270 /// that indicates how instruction selection should deal with the type. 271 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 272 273 public: 274 ValueTypeActionImpl() { 275 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 276 } 277 278 LegalizeTypeAction getTypeAction(MVT VT) const { 279 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; 280 } 281 282 void setTypeAction(EVT VT, LegalizeTypeAction Action) { 283 unsigned I = VT.getSimpleVT().SimpleTy; 284 ValueTypeActions[I] = Action; 285 } 286 }; 287 288 const ValueTypeActionImpl &getValueTypeActions() const { 289 return ValueTypeActions; 290 } 291 292 /// getTypeAction - Return how we should legalize values of this type, either 293 /// it is already legal (return 'Legal') or we need to promote it to a larger 294 /// type (return 'Promote'), or we need to expand it into multiple registers 295 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 296 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { 297 return getTypeConversion(Context, VT).first; 298 } 299 LegalizeTypeAction getTypeAction(MVT VT) const { 300 return ValueTypeActions.getTypeAction(VT); 301 } 302 303 /// getTypeToTransformTo - For types supported by the target, this is an 304 /// identity function. For types that must be promoted to larger types, this 305 /// returns the larger type to promote to. For integer types that are larger 306 /// than the largest integer register, this contains one step in the expansion 307 /// to get to the smaller register. For illegal floating point types, this 308 /// returns the integer type to transform to. 309 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 310 return getTypeConversion(Context, VT).second; 311 } 312 313 /// getTypeToExpandTo - For types supported by the target, this is an 314 /// identity function. For types that must be expanded (i.e. integer types 315 /// that are larger than the largest integer register or illegal floating 316 /// point types), this returns the largest legal type it will be expanded to. 317 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 318 assert(!VT.isVector()); 319 while (true) { 320 switch (getTypeAction(Context, VT)) { 321 case TypeLegal: 322 return VT; 323 case TypeExpandInteger: 324 VT = getTypeToTransformTo(Context, VT); 325 break; 326 default: 327 llvm_unreachable("Type is not legal nor is it to be expanded!"); 328 } 329 } 330 } 331 332 /// getVectorTypeBreakdown - Vector types are broken down into some number of 333 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 334 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 335 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 336 /// 337 /// This method returns the number of registers needed, and the VT for each 338 /// register. It also returns the VT and quantity of the intermediate values 339 /// before they are promoted/expanded. 340 /// 341 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 342 EVT &IntermediateVT, 343 unsigned &NumIntermediates, 344 EVT &RegisterVT) const; 345 346 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 347 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 348 /// this is the case, it returns true and store the intrinsic 349 /// information into the IntrinsicInfo that was passed to the function. 350 struct IntrinsicInfo { 351 unsigned opc; // target opcode 352 EVT memVT; // memory VT 353 const Value* ptrVal; // value representing memory location 354 int offset; // offset off of ptrVal 355 unsigned align; // alignment 356 bool vol; // is volatile? 357 bool readMem; // reads memory? 358 bool writeMem; // writes memory? 359 }; 360 361 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 362 unsigned /*Intrinsic*/) const { 363 return false; 364 } 365 366 /// isFPImmLegal - Returns true if the target can instruction select the 367 /// specified FP immediate natively. If false, the legalizer will materialize 368 /// the FP immediate as a load from a constant pool. 369 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const { 370 return false; 371 } 372 373 /// isShuffleMaskLegal - Targets can use this to indicate that they only 374 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 375 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 376 /// are assumed to be legal. 377 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 378 EVT /*VT*/) const { 379 return true; 380 } 381 382 /// canOpTrap - Returns true if the operation can trap for the value type. 383 /// VT must be a legal type. By default, we optimistically assume most 384 /// operations don't trap except for divide and remainder. 385 virtual bool canOpTrap(unsigned Op, EVT VT) const; 386 387 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 388 /// used by Targets can use this to indicate if there is a suitable 389 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 390 /// pool entry. 391 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 392 EVT /*VT*/) const { 393 return false; 394 } 395 396 /// getOperationAction - Return how this operation should be treated: either 397 /// it is legal, needs to be promoted to a larger size, needs to be 398 /// expanded to some other code sequence, or the target has a custom expander 399 /// for it. 400 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 401 if (VT.isExtended()) return Expand; 402 // If a target-specific SDNode requires legalization, require the target 403 // to provide custom legalization for it. 404 if (Op > array_lengthof(OpActions[0])) return Custom; 405 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 406 return (LegalizeAction)OpActions[I][Op]; 407 } 408 409 /// isOperationLegalOrCustom - Return true if the specified operation is 410 /// legal on this target or can be made legal with custom lowering. This 411 /// is used to help guide high-level lowering decisions. 412 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 413 return (VT == MVT::Other || isTypeLegal(VT)) && 414 (getOperationAction(Op, VT) == Legal || 415 getOperationAction(Op, VT) == Custom); 416 } 417 418 /// isOperationExpand - Return true if the specified operation is illegal on 419 /// this target or unlikely to be made legal with custom lowering. This is 420 /// used to help guide high-level lowering decisions. 421 bool isOperationExpand(unsigned Op, EVT VT) const { 422 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); 423 } 424 425 /// isOperationLegal - Return true if the specified operation is legal on this 426 /// target. 427 bool isOperationLegal(unsigned Op, EVT VT) const { 428 return (VT == MVT::Other || isTypeLegal(VT)) && 429 getOperationAction(Op, VT) == Legal; 430 } 431 432 /// getLoadExtAction - Return how this load with extension should be treated: 433 /// either it is legal, needs to be promoted to a larger size, needs to be 434 /// expanded to some other code sequence, or the target has a custom expander 435 /// for it. 436 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { 437 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 438 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 439 "Table isn't big enough!"); 440 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 441 } 442 443 /// isLoadExtLegal - Return true if the specified load with extension is legal 444 /// on this target. 445 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 446 return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal; 447 } 448 449 /// getTruncStoreAction - Return how this store with truncation should be 450 /// treated: either it is legal, needs to be promoted to a larger size, needs 451 /// to be expanded to some other code sequence, or the target has a custom 452 /// expander for it. 453 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 454 assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE && 455 MemVT.getSimpleVT() < MVT::LAST_VALUETYPE && 456 "Table isn't big enough!"); 457 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] 458 [MemVT.getSimpleVT().SimpleTy]; 459 } 460 461 /// isTruncStoreLegal - Return true if the specified store with truncation is 462 /// legal on this target. 463 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 464 return isTypeLegal(ValVT) && MemVT.isSimple() && 465 getTruncStoreAction(ValVT, MemVT) == Legal; 466 } 467 468 /// getIndexedLoadAction - Return how the indexed load should be treated: 469 /// either it is legal, needs to be promoted to a larger size, needs to be 470 /// expanded to some other code sequence, or the target has a custom expander 471 /// for it. 472 LegalizeAction 473 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 474 assert(IdxMode < ISD::LAST_INDEXED_MODE && 475 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 476 "Table isn't big enough!"); 477 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 478 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 479 } 480 481 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 482 /// on this target. 483 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 484 return VT.isSimple() && 485 (getIndexedLoadAction(IdxMode, VT) == Legal || 486 getIndexedLoadAction(IdxMode, VT) == Custom); 487 } 488 489 /// getIndexedStoreAction - Return how the indexed store should be treated: 490 /// either it is legal, needs to be promoted to a larger size, needs to be 491 /// expanded to some other code sequence, or the target has a custom expander 492 /// for it. 493 LegalizeAction 494 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 495 assert(IdxMode < ISD::LAST_INDEXED_MODE && 496 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 497 "Table isn't big enough!"); 498 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 499 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 500 } 501 502 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 503 /// on this target. 504 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 505 return VT.isSimple() && 506 (getIndexedStoreAction(IdxMode, VT) == Legal || 507 getIndexedStoreAction(IdxMode, VT) == Custom); 508 } 509 510 /// getCondCodeAction - Return how the condition code should be treated: 511 /// either it is legal, needs to be expanded to some other code sequence, 512 /// or the target has a custom expander for it. 513 LegalizeAction 514 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 515 assert((unsigned)CC < array_lengthof(CondCodeActions) && 516 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 517 "Table isn't big enough!"); 518 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 519 /// value and the upper 27 bits index into the second dimension of the 520 /// array to select what 64bit value to use. 521 LegalizeAction Action = (LegalizeAction) 522 ((CondCodeActions[CC][VT.getSimpleVT().SimpleTy >> 5] 523 >> (2*(VT.getSimpleVT().SimpleTy & 0x1F))) & 3); 524 assert(Action != Promote && "Can't promote condition code!"); 525 return Action; 526 } 527 528 /// isCondCodeLegal - Return true if the specified condition code is legal 529 /// on this target. 530 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 531 return getCondCodeAction(CC, VT) == Legal || 532 getCondCodeAction(CC, VT) == Custom; 533 } 534 535 536 /// getTypeToPromoteTo - If the action for this operation is to promote, this 537 /// method returns the ValueType to promote to. 538 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 539 assert(getOperationAction(Op, VT) == Promote && 540 "This operation isn't promoted!"); 541 542 // See if this has an explicit type specified. 543 std::map<std::pair<unsigned, MVT::SimpleValueType>, 544 MVT::SimpleValueType>::const_iterator PTTI = 545 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 546 if (PTTI != PromoteToType.end()) return PTTI->second; 547 548 assert((VT.isInteger() || VT.isFloatingPoint()) && 549 "Cannot autopromote this type, add it with AddPromotedToType."); 550 551 EVT NVT = VT; 552 do { 553 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 554 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 555 "Didn't find type to promote to!"); 556 } while (!isTypeLegal(NVT) || 557 getOperationAction(Op, NVT) == Promote); 558 return NVT; 559 } 560 561 /// getValueType - Return the EVT corresponding to this LLVM type. 562 /// This is fixed by the LLVM operations except for the pointer size. If 563 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 564 /// counterpart (e.g. structs), otherwise it will assert. 565 EVT getValueType(Type *Ty, bool AllowUnknown = false) const { 566 // Lower scalar pointers to native pointer types. 567 if (Ty->isPointerTy()) return PointerTy; 568 569 if (Ty->isVectorTy()) { 570 VectorType *VTy = cast<VectorType>(Ty); 571 Type *Elm = VTy->getElementType(); 572 // Lower vectors of pointers to native pointer types. 573 if (Elm->isPointerTy()) 574 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext()); 575 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), 576 VTy->getNumElements()); 577 } 578 return EVT::getEVT(Ty, AllowUnknown); 579 } 580 581 /// Return the MVT corresponding to this LLVM type. See getValueType. 582 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const { 583 return getValueType(Ty, AllowUnknown).getSimpleVT(); 584 } 585 586 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 587 /// function arguments in the caller parameter area. This is the actual 588 /// alignment, not its logarithm. 589 virtual unsigned getByValTypeAlignment(Type *Ty) const; 590 591 /// getRegisterType - Return the type of registers that this ValueType will 592 /// eventually require. 593 EVT getRegisterType(MVT VT) const { 594 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 595 return RegisterTypeForVT[VT.SimpleTy]; 596 } 597 598 /// getRegisterType - Return the type of registers that this ValueType will 599 /// eventually require. 600 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 601 if (VT.isSimple()) { 602 assert((unsigned)VT.getSimpleVT().SimpleTy < 603 array_lengthof(RegisterTypeForVT)); 604 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 605 } 606 if (VT.isVector()) { 607 EVT VT1, RegisterVT; 608 unsigned NumIntermediates; 609 (void)getVectorTypeBreakdown(Context, VT, VT1, 610 NumIntermediates, RegisterVT); 611 return RegisterVT; 612 } 613 if (VT.isInteger()) { 614 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 615 } 616 llvm_unreachable("Unsupported extended type!"); 617 } 618 619 /// getNumRegisters - Return the number of registers that this ValueType will 620 /// eventually require. This is one for any types promoted to live in larger 621 /// registers, but may be more than one for types (like i64) that are split 622 /// into pieces. For types like i140, which are first promoted then expanded, 623 /// it is the number of registers needed to hold all the bits of the original 624 /// type. For an i140 on a 32 bit machine this means 5 registers. 625 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 626 if (VT.isSimple()) { 627 assert((unsigned)VT.getSimpleVT().SimpleTy < 628 array_lengthof(NumRegistersForVT)); 629 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 630 } 631 if (VT.isVector()) { 632 EVT VT1, VT2; 633 unsigned NumIntermediates; 634 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 635 } 636 if (VT.isInteger()) { 637 unsigned BitWidth = VT.getSizeInBits(); 638 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 639 return (BitWidth + RegWidth - 1) / RegWidth; 640 } 641 llvm_unreachable("Unsupported extended type!"); 642 } 643 644 /// ShouldShrinkFPConstant - If true, then instruction selection should 645 /// seek to shrink the FP constant of the specified type to a smaller type 646 /// in order to save space and / or reduce runtime. 647 virtual bool ShouldShrinkFPConstant(EVT) const { return true; } 648 649 /// hasTargetDAGCombine - If true, the target has custom DAG combine 650 /// transformations that it can perform for the specified node. 651 bool hasTargetDAGCombine(ISD::NodeType NT) const { 652 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 653 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 654 } 655 656 /// This function returns the maximum number of store operations permitted 657 /// to replace a call to llvm.memset. The value is set by the target at the 658 /// performance threshold for such a replacement. If OptSize is true, 659 /// return the limit for functions that have OptSize attribute. 660 /// @brief Get maximum # of store operations permitted for llvm.memset 661 unsigned getMaxStoresPerMemset(bool OptSize) const { 662 return OptSize ? maxStoresPerMemsetOptSize : maxStoresPerMemset; 663 } 664 665 /// This function returns the maximum number of store operations permitted 666 /// to replace a call to llvm.memcpy. The value is set by the target at the 667 /// performance threshold for such a replacement. If OptSize is true, 668 /// return the limit for functions that have OptSize attribute. 669 /// @brief Get maximum # of store operations permitted for llvm.memcpy 670 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 671 return OptSize ? maxStoresPerMemcpyOptSize : maxStoresPerMemcpy; 672 } 673 674 /// This function returns the maximum number of store operations permitted 675 /// to replace a call to llvm.memmove. The value is set by the target at the 676 /// performance threshold for such a replacement. If OptSize is true, 677 /// return the limit for functions that have OptSize attribute. 678 /// @brief Get maximum # of store operations permitted for llvm.memmove 679 unsigned getMaxStoresPerMemmove(bool OptSize) const { 680 return OptSize ? maxStoresPerMemmoveOptSize : maxStoresPerMemmove; 681 } 682 683 /// This function returns true if the target allows unaligned memory accesses. 684 /// of the specified type. If true, it also returns whether the unaligned 685 /// memory access is "fast" in the second argument by reference. This is used, 686 /// for example, in situations where an array copy/move/set is converted to a 687 /// sequence of store operations. It's use helps to ensure that such 688 /// replacements don't generate code that causes an alignment error (trap) on 689 /// the target machine. 690 /// @brief Determine if the target supports unaligned memory accesses. 691 virtual bool allowsUnalignedMemoryAccesses(EVT, bool *Fast = 0) const { 692 return false; 693 } 694 695 /// This function returns true if the target would benefit from code placement 696 /// optimization. 697 /// @brief Determine if the target should perform code placement optimization. 698 bool shouldOptimizeCodePlacement() const { 699 return benefitFromCodePlacementOpt; 700 } 701 702 /// getOptimalMemOpType - Returns the target specific optimal type for load 703 /// and store operations as a result of memset, memcpy, and memmove 704 /// lowering. If DstAlign is zero that means it's safe to destination 705 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 706 /// means there isn't a need to check it against alignment requirement, 707 /// probably because the source does not need to be loaded. If 'IsMemset' is 708 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 709 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 710 /// source is constant so it does not need to be loaded. 711 /// It returns EVT::Other if the type should be determined using generic 712 /// target-independent logic. 713 virtual EVT getOptimalMemOpType(uint64_t /*Size*/, 714 unsigned /*DstAlign*/, unsigned /*SrcAlign*/, 715 bool /*IsMemset*/, 716 bool /*ZeroMemset*/, 717 bool /*MemcpyStrSrc*/, 718 MachineFunction &/*MF*/) const { 719 return MVT::Other; 720 } 721 722 /// isSafeMemOpType - Returns true if it's safe to use load / store of the 723 /// specified type to expand memcpy / memset inline. This is mostly true 724 /// for all types except for some special cases. For example, on X86 725 /// targets without SSE2 f64 load / store are done with fldl / fstpl which 726 /// also does type conversion. Note the specified type doesn't have to be 727 /// legal as the hook is used before type legalization. 728 virtual bool isSafeMemOpType(MVT VT) const { 729 return true; 730 } 731 732 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 733 /// to implement llvm.setjmp. 734 bool usesUnderscoreSetJmp() const { 735 return UseUnderscoreSetJmp; 736 } 737 738 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 739 /// to implement llvm.longjmp. 740 bool usesUnderscoreLongJmp() const { 741 return UseUnderscoreLongJmp; 742 } 743 744 /// supportJumpTables - return whether the target can generate code for 745 /// jump tables. 746 bool supportJumpTables() const { 747 return SupportJumpTables; 748 } 749 750 /// getMinimumJumpTableEntries - return integer threshold on number of 751 /// blocks to use jump tables rather than if sequence. 752 int getMinimumJumpTableEntries() const { 753 return MinimumJumpTableEntries; 754 } 755 756 /// getStackPointerRegisterToSaveRestore - If a physical register, this 757 /// specifies the register that llvm.savestack/llvm.restorestack should save 758 /// and restore. 759 unsigned getStackPointerRegisterToSaveRestore() const { 760 return StackPointerRegisterToSaveRestore; 761 } 762 763 /// getExceptionPointerRegister - If a physical register, this returns 764 /// the register that receives the exception address on entry to a landing 765 /// pad. 766 unsigned getExceptionPointerRegister() const { 767 return ExceptionPointerRegister; 768 } 769 770 /// getExceptionSelectorRegister - If a physical register, this returns 771 /// the register that receives the exception typeid on entry to a landing 772 /// pad. 773 unsigned getExceptionSelectorRegister() const { 774 return ExceptionSelectorRegister; 775 } 776 777 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 778 /// set, the default is 200) 779 unsigned getJumpBufSize() const { 780 return JumpBufSize; 781 } 782 783 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 784 /// (if never set, the default is 0) 785 unsigned getJumpBufAlignment() const { 786 return JumpBufAlignment; 787 } 788 789 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 790 /// argument. 791 unsigned getMinStackArgumentAlignment() const { 792 return MinStackArgumentAlignment; 793 } 794 795 /// getMinFunctionAlignment - return the minimum function alignment. 796 /// 797 unsigned getMinFunctionAlignment() const { 798 return MinFunctionAlignment; 799 } 800 801 /// getPrefFunctionAlignment - return the preferred function alignment. 802 /// 803 unsigned getPrefFunctionAlignment() const { 804 return PrefFunctionAlignment; 805 } 806 807 /// getPrefLoopAlignment - return the preferred loop alignment. 808 /// 809 unsigned getPrefLoopAlignment() const { 810 return PrefLoopAlignment; 811 } 812 813 /// getShouldFoldAtomicFences - return whether the combiner should fold 814 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 815 /// 816 bool getShouldFoldAtomicFences() const { 817 return ShouldFoldAtomicFences; 818 } 819 820 /// getInsertFencesFor - return whether the DAG builder should automatically 821 /// insert fences and reduce ordering for atomics. 822 /// 823 bool getInsertFencesForAtomic() const { 824 return InsertFencesForAtomic; 825 } 826 827 /// getPreIndexedAddressParts - returns true by value, base pointer and 828 /// offset pointer and addressing mode by reference if the node's address 829 /// can be legally represented as pre-indexed load / store address. 830 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, 831 SDValue &/*Offset*/, 832 ISD::MemIndexedMode &/*AM*/, 833 SelectionDAG &/*DAG*/) const { 834 return false; 835 } 836 837 /// getPostIndexedAddressParts - returns true by value, base pointer and 838 /// offset pointer and addressing mode by reference if this node can be 839 /// combined with a load / store to form a post-indexed load / store. 840 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, 841 SDValue &/*Base*/, SDValue &/*Offset*/, 842 ISD::MemIndexedMode &/*AM*/, 843 SelectionDAG &/*DAG*/) const { 844 return false; 845 } 846 847 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 848 /// current function. The returned value is a member of the 849 /// MachineJumpTableInfo::JTEntryKind enum. 850 virtual unsigned getJumpTableEncoding() const; 851 852 virtual const MCExpr * 853 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/, 854 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/, 855 MCContext &/*Ctx*/) const { 856 llvm_unreachable("Need to implement this hook if target has custom JTIs"); 857 } 858 859 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 860 /// jumptable. 861 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 862 SelectionDAG &DAG) const; 863 864 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 865 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 866 /// MCExpr. 867 virtual const MCExpr * 868 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 869 unsigned JTI, MCContext &Ctx) const; 870 871 /// isOffsetFoldingLegal - Return true if folding a constant offset 872 /// with the given GlobalAddress is legal. It is frequently not legal in 873 /// PIC relocation models. 874 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 875 876 /// getStackCookieLocation - Return true if the target stores stack 877 /// protector cookies at a fixed offset in some non-standard address 878 /// space, and populates the address space and offset as 879 /// appropriate. 880 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/, 881 unsigned &/*Offset*/) const { 882 return false; 883 } 884 885 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be 886 /// used for loads / stores from the global. 887 virtual unsigned getMaximalGlobalOffset() const { 888 return 0; 889 } 890 891 //===--------------------------------------------------------------------===// 892 // TargetLowering Optimization Methods 893 // 894 895 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 896 /// SDValues for returning information from TargetLowering to its clients 897 /// that want to combine 898 struct TargetLoweringOpt { 899 SelectionDAG &DAG; 900 bool LegalTys; 901 bool LegalOps; 902 SDValue Old; 903 SDValue New; 904 905 explicit TargetLoweringOpt(SelectionDAG &InDAG, 906 bool LT, bool LO) : 907 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 908 909 bool LegalTypes() const { return LegalTys; } 910 bool LegalOperations() const { return LegalOps; } 911 912 bool CombineTo(SDValue O, SDValue N) { 913 Old = O; 914 New = N; 915 return true; 916 } 917 918 /// ShrinkDemandedConstant - Check to see if the specified operand of the 919 /// specified instruction is a constant integer. If so, check to see if 920 /// there are any bits set in the constant that are not demanded. If so, 921 /// shrink the constant and return true. 922 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 923 924 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 925 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 926 /// cast, but it could be generalized for targets with other types of 927 /// implicit widening casts. 928 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 929 DebugLoc dl); 930 }; 931 932 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 933 /// DemandedMask bits of the result of Op are ever used downstream. If we can 934 /// use this information to simplify Op, create a new simplified DAG node and 935 /// return true, returning the original and new nodes in Old and New. 936 /// Otherwise, analyze the expression and return a mask of KnownOne and 937 /// KnownZero bits for the expression (used to simplify the caller). 938 /// The KnownZero/One bits may only be accurate for those bits in the 939 /// DemandedMask. 940 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 941 APInt &KnownZero, APInt &KnownOne, 942 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 943 944 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 945 /// Mask are known to be either zero or one and return them in the 946 /// KnownZero/KnownOne bitsets. 947 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 948 APInt &KnownZero, 949 APInt &KnownOne, 950 const SelectionDAG &DAG, 951 unsigned Depth = 0) const; 952 953 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 954 /// targets that want to expose additional information about sign bits to the 955 /// DAG Combiner. 956 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 957 unsigned Depth = 0) const; 958 959 struct DAGCombinerInfo { 960 void *DC; // The DAG Combiner object. 961 bool BeforeLegalize; 962 bool BeforeLegalizeOps; 963 bool CalledByLegalizer; 964 public: 965 SelectionDAG &DAG; 966 967 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 968 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 969 CalledByLegalizer(cl), DAG(dag) {} 970 971 bool isBeforeLegalize() const { return BeforeLegalize; } 972 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 973 bool isCalledByLegalizer() const { return CalledByLegalizer; } 974 975 void AddToWorklist(SDNode *N); 976 void RemoveFromWorklist(SDNode *N); 977 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 978 bool AddTo = true); 979 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 980 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 981 982 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 983 }; 984 985 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 986 /// and cc. If it is unable to simplify it, return a null SDValue. 987 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 988 ISD::CondCode Cond, bool foldBooleans, 989 DAGCombinerInfo &DCI, DebugLoc dl) const; 990 991 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 992 /// node is a GlobalAddress + offset. 993 virtual bool 994 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 995 996 /// PerformDAGCombine - This method will be invoked for all target nodes and 997 /// for any target-independent nodes that the target has registered with 998 /// invoke it for. 999 /// 1000 /// The semantics are as follows: 1001 /// Return Value: 1002 /// SDValue.Val == 0 - No change was made 1003 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 1004 /// otherwise - N should be replaced by the returned Operand. 1005 /// 1006 /// In addition, methods provided by DAGCombinerInfo may be used to perform 1007 /// more complex transformations. 1008 /// 1009 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 1010 1011 /// isTypeDesirableForOp - Return true if the target has native support for 1012 /// the specified value type and it is 'desirable' to use the type for the 1013 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 1014 /// instruction encodings are longer and some i16 instructions are slow. 1015 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { 1016 // By default, assume all legal types are desirable. 1017 return isTypeLegal(VT); 1018 } 1019 1020 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner 1021 /// to transform a floating point op of specified opcode to a equivalent op of 1022 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM. 1023 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, 1024 EVT /*VT*/) const { 1025 return false; 1026 } 1027 1028 /// IsDesirableToPromoteOp - This method query the target whether it is 1029 /// beneficial for dag combiner to promote the specified node. If true, it 1030 /// should return the desired promotion type by reference. 1031 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { 1032 return false; 1033 } 1034 1035 //===--------------------------------------------------------------------===// 1036 // TargetLowering Configuration Methods - These methods should be invoked by 1037 // the derived class constructor to configure this object for the target. 1038 // 1039 1040protected: 1041 /// setBooleanContents - Specify how the target extends the result of a 1042 /// boolean value from i1 to a wider type. See getBooleanContents. 1043 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 1044 /// setBooleanVectorContents - Specify how the target extends the result 1045 /// of a vector boolean value from a vector of i1 to a wider type. See 1046 /// getBooleanContents. 1047 void setBooleanVectorContents(BooleanContent Ty) { 1048 BooleanVectorContents = Ty; 1049 } 1050 1051 /// setSchedulingPreference - Specify the target scheduling preference. 1052 void setSchedulingPreference(Sched::Preference Pref) { 1053 SchedPreferenceInfo = Pref; 1054 } 1055 1056 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 1057 /// use _setjmp to implement llvm.setjmp or the non _ version. 1058 /// Defaults to false. 1059 void setUseUnderscoreSetJmp(bool Val) { 1060 UseUnderscoreSetJmp = Val; 1061 } 1062 1063 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 1064 /// use _longjmp to implement llvm.longjmp or the non _ version. 1065 /// Defaults to false. 1066 void setUseUnderscoreLongJmp(bool Val) { 1067 UseUnderscoreLongJmp = Val; 1068 } 1069 1070 /// setSupportJumpTables - Indicate whether the target can generate code for 1071 /// jump tables. 1072 void setSupportJumpTables(bool Val) { 1073 SupportJumpTables = Val; 1074 } 1075 1076 /// setMinimumJumpTableEntries - Indicate the number of blocks to generate 1077 /// jump tables rather than if sequence. 1078 void setMinimumJumpTableEntries(int Val) { 1079 MinimumJumpTableEntries = Val; 1080 } 1081 1082 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 1083 /// specifies the register that llvm.savestack/llvm.restorestack should save 1084 /// and restore. 1085 void setStackPointerRegisterToSaveRestore(unsigned R) { 1086 StackPointerRegisterToSaveRestore = R; 1087 } 1088 1089 /// setExceptionPointerRegister - If set to a physical register, this sets 1090 /// the register that receives the exception address on entry to a landing 1091 /// pad. 1092 void setExceptionPointerRegister(unsigned R) { 1093 ExceptionPointerRegister = R; 1094 } 1095 1096 /// setExceptionSelectorRegister - If set to a physical register, this sets 1097 /// the register that receives the exception typeid on entry to a landing 1098 /// pad. 1099 void setExceptionSelectorRegister(unsigned R) { 1100 ExceptionSelectorRegister = R; 1101 } 1102 1103 /// SelectIsExpensive - Tells the code generator not to expand operations 1104 /// into sequences that use the select operations if possible. 1105 void setSelectIsExpensive(bool isExpensive = true) { 1106 SelectIsExpensive = isExpensive; 1107 } 1108 1109 /// JumpIsExpensive - Tells the code generator not to expand sequence of 1110 /// operations into a separate sequences that increases the amount of 1111 /// flow control. 1112 void setJumpIsExpensive(bool isExpensive = true) { 1113 JumpIsExpensive = isExpensive; 1114 } 1115 1116 /// setIntDivIsCheap - Tells the code generator that integer divide is 1117 /// expensive, and if possible, should be replaced by an alternate sequence 1118 /// of instructions not containing an integer divide. 1119 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 1120 1121 /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass. 1122 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { 1123 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; 1124 } 1125 1126 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 1127 /// srl/add/sra for a signed divide by power of two, and let the target handle 1128 /// it. 1129 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 1130 1131 /// addRegisterClass - Add the specified register class as an available 1132 /// regclass for the specified value type. This indicates the selector can 1133 /// handle values of that class natively. 1134 void addRegisterClass(EVT VT, const TargetRegisterClass *RC) { 1135 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 1136 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 1137 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 1138 } 1139 1140 /// findRepresentativeClass - Return the largest legal super-reg register class 1141 /// of the register class for the specified type and its associated "cost". 1142 virtual std::pair<const TargetRegisterClass*, uint8_t> 1143 findRepresentativeClass(EVT VT) const; 1144 1145 /// computeRegisterProperties - Once all of the register classes are added, 1146 /// this allows us to compute derived properties we expose. 1147 void computeRegisterProperties(); 1148 1149 /// setOperationAction - Indicate that the specified operation does not work 1150 /// with the specified type and indicate what to do about it. 1151 void setOperationAction(unsigned Op, MVT VT, 1152 LegalizeAction Action) { 1153 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 1154 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 1155 } 1156 1157 /// setLoadExtAction - Indicate that the specified load with extension does 1158 /// not work with the specified type and indicate what to do about it. 1159 void setLoadExtAction(unsigned ExtType, MVT VT, 1160 LegalizeAction Action) { 1161 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 1162 "Table isn't big enough!"); 1163 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 1164 } 1165 1166 /// setTruncStoreAction - Indicate that the specified truncating store does 1167 /// not work with the specified type and indicate what to do about it. 1168 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1169 LegalizeAction Action) { 1170 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 1171 "Table isn't big enough!"); 1172 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 1173 } 1174 1175 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1176 /// does not work with the specified type and indicate what to do abort 1177 /// it. NOTE: All indexed mode loads are initialized to Expand in 1178 /// TargetLowering.cpp 1179 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1180 LegalizeAction Action) { 1181 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1182 (unsigned)Action < 0xf && "Table isn't big enough!"); 1183 // Load action are kept in the upper half. 1184 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1185 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1186 } 1187 1188 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1189 /// does not work with the specified type and indicate what to do about 1190 /// it. NOTE: All indexed mode stores are initialized to Expand in 1191 /// TargetLowering.cpp 1192 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1193 LegalizeAction Action) { 1194 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1195 (unsigned)Action < 0xf && "Table isn't big enough!"); 1196 // Store action are kept in the lower half. 1197 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1198 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1199 } 1200 1201 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1202 /// supported on the target and indicate what to do about it. 1203 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1204 LegalizeAction Action) { 1205 assert(VT < MVT::LAST_VALUETYPE && 1206 (unsigned)CC < array_lengthof(CondCodeActions) && 1207 "Table isn't big enough!"); 1208 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 1209 /// value and the upper 27 bits index into the second dimension of the 1210 /// array to select what 64bit value to use. 1211 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1212 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2); 1213 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1214 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2; 1215 } 1216 1217 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1218 /// promotion code defaults to trying a larger integer/fp until it can find 1219 /// one that works. If that default is insufficient, this method can be used 1220 /// by the target to override the default. 1221 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1222 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1223 } 1224 1225 /// setTargetDAGCombine - Targets should invoke this method for each target 1226 /// independent node that they want to provide a custom DAG combiner for by 1227 /// implementing the PerformDAGCombine virtual method. 1228 void setTargetDAGCombine(ISD::NodeType NT) { 1229 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1230 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1231 } 1232 1233 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1234 /// bytes); default is 200 1235 void setJumpBufSize(unsigned Size) { 1236 JumpBufSize = Size; 1237 } 1238 1239 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1240 /// alignment (in bytes); default is 0 1241 void setJumpBufAlignment(unsigned Align) { 1242 JumpBufAlignment = Align; 1243 } 1244 1245 /// setMinFunctionAlignment - Set the target's minimum function alignment (in 1246 /// log2(bytes)) 1247 void setMinFunctionAlignment(unsigned Align) { 1248 MinFunctionAlignment = Align; 1249 } 1250 1251 /// setPrefFunctionAlignment - Set the target's preferred function alignment. 1252 /// This should be set if there is a performance benefit to 1253 /// higher-than-minimum alignment (in log2(bytes)) 1254 void setPrefFunctionAlignment(unsigned Align) { 1255 PrefFunctionAlignment = Align; 1256 } 1257 1258 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1259 /// alignment is zero, it means the target does not care about loop alignment. 1260 /// The alignment is specified in log2(bytes). 1261 void setPrefLoopAlignment(unsigned Align) { 1262 PrefLoopAlignment = Align; 1263 } 1264 1265 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1266 /// argument (in log2(bytes)). 1267 void setMinStackArgumentAlignment(unsigned Align) { 1268 MinStackArgumentAlignment = Align; 1269 } 1270 1271 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1272 /// atomic operation intrinsics includes locking. Default is false. 1273 void setShouldFoldAtomicFences(bool fold) { 1274 ShouldFoldAtomicFences = fold; 1275 } 1276 1277 /// setInsertFencesForAtomic - Set if the DAG builder should 1278 /// automatically insert fences and reduce the order of atomic memory 1279 /// operations to Monotonic. 1280 void setInsertFencesForAtomic(bool fence) { 1281 InsertFencesForAtomic = fence; 1282 } 1283 1284public: 1285 //===--------------------------------------------------------------------===// 1286 // Lowering methods - These methods must be implemented by targets so that 1287 // the SelectionDAGBuilder code knows how to lower these. 1288 // 1289 1290 /// LowerFormalArguments - This hook must be implemented to lower the 1291 /// incoming (formal) arguments, described by the Ins array, into the 1292 /// specified DAG. The implementation should fill in the InVals array 1293 /// with legal-type argument values, and return the resulting token 1294 /// chain value. 1295 /// 1296 virtual SDValue 1297 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1298 bool /*isVarArg*/, 1299 const SmallVectorImpl<ISD::InputArg> &/*Ins*/, 1300 DebugLoc /*dl*/, SelectionDAG &/*DAG*/, 1301 SmallVectorImpl<SDValue> &/*InVals*/) const { 1302 llvm_unreachable("Not Implemented"); 1303 } 1304 1305 struct ArgListEntry { 1306 SDValue Node; 1307 Type* Ty; 1308 bool isSExt : 1; 1309 bool isZExt : 1; 1310 bool isInReg : 1; 1311 bool isSRet : 1; 1312 bool isNest : 1; 1313 bool isByVal : 1; 1314 uint16_t Alignment; 1315 1316 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1317 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1318 }; 1319 typedef std::vector<ArgListEntry> ArgListTy; 1320 1321 /// CallLoweringInfo - This structure contains all information that is 1322 /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the 1323 /// SelectionDAG builder needs to lower a call, and targets will see this 1324 /// struct in their LowerCall implementation. 1325 struct CallLoweringInfo { 1326 SDValue Chain; 1327 Type *RetTy; 1328 bool RetSExt : 1; 1329 bool RetZExt : 1; 1330 bool IsVarArg : 1; 1331 bool IsInReg : 1; 1332 bool DoesNotReturn : 1; 1333 bool IsReturnValueUsed : 1; 1334 1335 // IsTailCall should be modified by implementations of 1336 // TargetLowering::LowerCall that perform tail call conversions. 1337 bool IsTailCall; 1338 1339 unsigned NumFixedArgs; 1340 CallingConv::ID CallConv; 1341 SDValue Callee; 1342 ArgListTy &Args; 1343 SelectionDAG &DAG; 1344 DebugLoc DL; 1345 ImmutableCallSite *CS; 1346 SmallVector<ISD::OutputArg, 32> Outs; 1347 SmallVector<SDValue, 32> OutVals; 1348 SmallVector<ISD::InputArg, 32> Ins; 1349 1350 1351 /// CallLoweringInfo - Constructs a call lowering context based on the 1352 /// ImmutableCallSite \p cs. 1353 CallLoweringInfo(SDValue chain, Type *retTy, 1354 FunctionType *FTy, bool isTailCall, SDValue callee, 1355 ArgListTy &args, SelectionDAG &dag, DebugLoc dl, 1356 ImmutableCallSite &cs) 1357 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attributes::SExt)), 1358 RetZExt(cs.paramHasAttr(0, Attributes::ZExt)), IsVarArg(FTy->isVarArg()), 1359 IsInReg(cs.paramHasAttr(0, Attributes::InReg)), 1360 DoesNotReturn(cs.doesNotReturn()), 1361 IsReturnValueUsed(!cs.getInstruction()->use_empty()), 1362 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()), 1363 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag), 1364 DL(dl), CS(&cs) {} 1365 1366 /// CallLoweringInfo - Constructs a call lowering context based on the 1367 /// provided call information. 1368 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt, 1369 bool isVarArg, bool isInReg, unsigned numFixedArgs, 1370 CallingConv::ID callConv, bool isTailCall, 1371 bool doesNotReturn, bool isReturnValueUsed, SDValue callee, 1372 ArgListTy &args, SelectionDAG &dag, DebugLoc dl) 1373 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt), 1374 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn), 1375 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall), 1376 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee), 1377 Args(args), DAG(dag), DL(dl), CS(NULL) {} 1378 }; 1379 1380 /// LowerCallTo - This function lowers an abstract call to a function into an 1381 /// actual call. This returns a pair of operands. The first element is the 1382 /// return value for the function (if RetTy is not VoidTy). The second 1383 /// element is the outgoing token chain. It calls LowerCall to do the actual 1384 /// lowering. 1385 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const; 1386 1387 /// LowerCall - This hook must be implemented to lower calls into the 1388 /// the specified DAG. The outgoing arguments to the call are described 1389 /// by the Outs array, and the values to be returned by the call are 1390 /// described by the Ins array. The implementation should fill in the 1391 /// InVals array with legal-type return values from the call, and return 1392 /// the resulting token chain value. 1393 virtual SDValue 1394 LowerCall(CallLoweringInfo &/*CLI*/, 1395 SmallVectorImpl<SDValue> &/*InVals*/) const { 1396 llvm_unreachable("Not Implemented"); 1397 } 1398 1399 /// HandleByVal - Target-specific cleanup for formal ByVal parameters. 1400 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {} 1401 1402 /// CanLowerReturn - This hook should be implemented to check whether the 1403 /// return values described by the Outs array can fit into the return 1404 /// registers. If false is returned, an sret-demotion is performed. 1405 /// 1406 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, 1407 MachineFunction &/*MF*/, bool /*isVarArg*/, 1408 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 1409 LLVMContext &/*Context*/) const 1410 { 1411 // Return true by default to get preexisting behavior. 1412 return true; 1413 } 1414 1415 /// LowerReturn - This hook must be implemented to lower outgoing 1416 /// return values, described by the Outs array, into the specified 1417 /// DAG. The implementation should return the resulting token chain 1418 /// value. 1419 /// 1420 virtual SDValue 1421 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1422 bool /*isVarArg*/, 1423 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 1424 const SmallVectorImpl<SDValue> &/*OutVals*/, 1425 DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const { 1426 llvm_unreachable("Not Implemented"); 1427 } 1428 1429 /// isUsedByReturnOnly - Return true if result of the specified node is used 1430 /// by a return node only. It also compute and return the input chain for the 1431 /// tail call. 1432 /// This is used to determine whether it is possible 1433 /// to codegen a libcall as tail call at legalization time. 1434 virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const { 1435 return false; 1436 } 1437 1438 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the 1439 /// call instruction as a tail call. This is used by optimization passes to 1440 /// determine if it's profitable to duplicate return instructions to enable 1441 /// tailcall optimization. 1442 virtual bool mayBeEmittedAsTailCall(CallInst *) const { 1443 return false; 1444 } 1445 1446 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or 1447 /// sign extend a zeroext/signext integer argument or return value. 1448 /// FIXME: Most C calling convention requires the return type to be promoted, 1449 /// but this is not true all the time, e.g. i1 on x86-64. It is also not 1450 /// necessary for non-C calling conventions. The frontend should handle this 1451 /// and include all of the necessary information. 1452 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1453 ISD::NodeType /*ExtendKind*/) const { 1454 EVT MinVT = getRegisterType(Context, MVT::i32); 1455 return VT.bitsLT(MinVT) ? MinVT : VT; 1456 } 1457 1458 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1459 /// to legalize nodes with an illegal operand type but legal result types. 1460 /// It replaces the LowerOperation callback in the type Legalizer. 1461 /// The reason we can not do away with LowerOperation entirely is that 1462 /// LegalizeDAG isn't yet ready to use this callback. 1463 /// TODO: Consider merging with ReplaceNodeResults. 1464 1465 /// The target places new result values for the node in Results (their number 1466 /// and types must exactly match those of the original return values of 1467 /// the node), or leaves Results empty, which indicates that the node is not 1468 /// to be custom lowered after all. 1469 /// The default implementation calls LowerOperation. 1470 virtual void LowerOperationWrapper(SDNode *N, 1471 SmallVectorImpl<SDValue> &Results, 1472 SelectionDAG &DAG) const; 1473 1474 /// LowerOperation - This callback is invoked for operations that are 1475 /// unsupported by the target, which are registered to use 'custom' lowering, 1476 /// and whose defined values are all legal. 1477 /// If the target has no operations that require custom lowering, it need not 1478 /// implement this. The default implementation of this aborts. 1479 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1480 1481 /// ReplaceNodeResults - This callback is invoked when a node result type is 1482 /// illegal for the target, and the operation was registered to use 'custom' 1483 /// lowering for that result type. The target places new result values for 1484 /// the node in Results (their number and types must exactly match those of 1485 /// the original return values of the node), or leaves Results empty, which 1486 /// indicates that the node is not to be custom lowered after all. 1487 /// 1488 /// If the target has no operations that require custom lowering, it need not 1489 /// implement this. The default implementation aborts. 1490 virtual void ReplaceNodeResults(SDNode * /*N*/, 1491 SmallVectorImpl<SDValue> &/*Results*/, 1492 SelectionDAG &/*DAG*/) const { 1493 llvm_unreachable("ReplaceNodeResults not implemented for this target!"); 1494 } 1495 1496 /// getTargetNodeName() - This method returns the name of a target specific 1497 /// DAG node. 1498 virtual const char *getTargetNodeName(unsigned Opcode) const; 1499 1500 /// createFastISel - This method returns a target specific FastISel object, 1501 /// or null if the target does not support "fast" ISel. 1502 virtual FastISel *createFastISel(FunctionLoweringInfo &, 1503 const TargetLibraryInfo *) const { 1504 return 0; 1505 } 1506 1507 //===--------------------------------------------------------------------===// 1508 // Inline Asm Support hooks 1509 // 1510 1511 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1512 /// call to be explicit llvm code if it wants to. This is useful for 1513 /// turning simple inline asms into LLVM intrinsics, which gives the 1514 /// compiler more information about the behavior of the code. 1515 virtual bool ExpandInlineAsm(CallInst *) const { 1516 return false; 1517 } 1518 1519 enum ConstraintType { 1520 C_Register, // Constraint represents specific register(s). 1521 C_RegisterClass, // Constraint represents any of register(s) in class. 1522 C_Memory, // Memory constraint. 1523 C_Other, // Something else. 1524 C_Unknown // Unsupported constraint. 1525 }; 1526 1527 enum ConstraintWeight { 1528 // Generic weights. 1529 CW_Invalid = -1, // No match. 1530 CW_Okay = 0, // Acceptable. 1531 CW_Good = 1, // Good weight. 1532 CW_Better = 2, // Better weight. 1533 CW_Best = 3, // Best weight. 1534 1535 // Well-known weights. 1536 CW_SpecificReg = CW_Okay, // Specific register operands. 1537 CW_Register = CW_Good, // Register operands. 1538 CW_Memory = CW_Better, // Memory operands. 1539 CW_Constant = CW_Best, // Constant operand. 1540 CW_Default = CW_Okay // Default or don't know type. 1541 }; 1542 1543 /// AsmOperandInfo - This contains information for each constraint that we are 1544 /// lowering. 1545 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1546 /// ConstraintCode - This contains the actual string for the code, like "m". 1547 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1548 /// most closely matches the operand. 1549 std::string ConstraintCode; 1550 1551 /// ConstraintType - Information about the constraint code, e.g. Register, 1552 /// RegisterClass, Memory, Other, Unknown. 1553 TargetLowering::ConstraintType ConstraintType; 1554 1555 /// CallOperandval - If this is the result output operand or a 1556 /// clobber, this is null, otherwise it is the incoming operand to the 1557 /// CallInst. This gets modified as the asm is processed. 1558 Value *CallOperandVal; 1559 1560 /// ConstraintVT - The ValueType for the operand value. 1561 EVT ConstraintVT; 1562 1563 /// isMatchingInputConstraint - Return true of this is an input operand that 1564 /// is a matching constraint like "4". 1565 bool isMatchingInputConstraint() const; 1566 1567 /// getMatchedOperand - If this is an input matching constraint, this method 1568 /// returns the output operand it matches. 1569 unsigned getMatchedOperand() const; 1570 1571 /// Copy constructor for copying from an AsmOperandInfo. 1572 AsmOperandInfo(const AsmOperandInfo &info) 1573 : InlineAsm::ConstraintInfo(info), 1574 ConstraintCode(info.ConstraintCode), 1575 ConstraintType(info.ConstraintType), 1576 CallOperandVal(info.CallOperandVal), 1577 ConstraintVT(info.ConstraintVT) { 1578 } 1579 1580 /// Copy constructor for copying from a ConstraintInfo. 1581 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1582 : InlineAsm::ConstraintInfo(info), 1583 ConstraintType(TargetLowering::C_Unknown), 1584 CallOperandVal(0), ConstraintVT(MVT::Other) { 1585 } 1586 }; 1587 1588 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; 1589 1590 /// ParseConstraints - Split up the constraint string from the inline 1591 /// assembly value into the specific constraints and their prefixes, 1592 /// and also tie in the associated operand values. 1593 /// If this returns an empty vector, and if the constraint string itself 1594 /// isn't empty, there was an error parsing. 1595 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; 1596 1597 /// Examine constraint type and operand type and determine a weight value. 1598 /// The operand object must already have been set up with the operand type. 1599 virtual ConstraintWeight getMultipleConstraintMatchWeight( 1600 AsmOperandInfo &info, int maIndex) const; 1601 1602 /// Examine constraint string and operand type and determine a weight value. 1603 /// The operand object must already have been set up with the operand type. 1604 virtual ConstraintWeight getSingleConstraintMatchWeight( 1605 AsmOperandInfo &info, const char *constraint) const; 1606 1607 /// ComputeConstraintToUse - Determines the constraint code and constraint 1608 /// type to use for the specific AsmOperandInfo, setting 1609 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1610 /// being passed in is available, it can be passed in as Op, otherwise an 1611 /// empty SDValue can be passed. 1612 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1613 SDValue Op, 1614 SelectionDAG *DAG = 0) const; 1615 1616 /// getConstraintType - Given a constraint, return the type of constraint it 1617 /// is for this target. 1618 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1619 1620 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1621 /// {edx}), return the register number and the register class for the 1622 /// register. 1623 /// 1624 /// Given a register class constraint, like 'r', if this corresponds directly 1625 /// to an LLVM register class, return a register of 0 and the register class 1626 /// pointer. 1627 /// 1628 /// This should only be used for C_Register constraints. On error, 1629 /// this returns a register number of 0 and a null register class pointer.. 1630 virtual std::pair<unsigned, const TargetRegisterClass*> 1631 getRegForInlineAsmConstraint(const std::string &Constraint, 1632 EVT VT) const; 1633 1634 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1635 /// with another that has more specific requirements based on the type of the 1636 /// corresponding operand. This returns null if there is no replacement to 1637 /// make. 1638 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1639 1640 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1641 /// vector. If it is invalid, don't add anything to Ops. 1642 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 1643 std::vector<SDValue> &Ops, 1644 SelectionDAG &DAG) const; 1645 1646 //===--------------------------------------------------------------------===// 1647 // Instruction Emitting Hooks 1648 // 1649 1650 // EmitInstrWithCustomInserter - This method should be implemented by targets 1651 // that mark instructions with the 'usesCustomInserter' flag. These 1652 // instructions are special in various ways, which require special support to 1653 // insert. The specified MachineInstr is created but not inserted into any 1654 // basic blocks, and this method is called to expand it into a sequence of 1655 // instructions, potentially also creating new basic blocks and control flow. 1656 virtual MachineBasicBlock * 1657 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 1658 1659 /// AdjustInstrPostInstrSelection - This method should be implemented by 1660 /// targets that mark instructions with the 'hasPostISelHook' flag. These 1661 /// instructions must be adjusted after instruction selection by target hooks. 1662 /// e.g. To fill in optional defs for ARM 's' setting instructions. 1663 virtual void 1664 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 1665 1666 //===--------------------------------------------------------------------===// 1667 // Addressing mode description hooks (used by LSR etc). 1668 // 1669 1670 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the 1671 /// same BB as Load/Store instructions reading the address. This allows as 1672 /// much computation as possible to be done in the address mode for that 1673 /// operand. This hook lets targets also pass back when this should be done 1674 /// on intrinsics which load/store. 1675 virtual bool GetAddrModeArguments(IntrinsicInst *I, 1676 SmallVectorImpl<Value*> &Ops, 1677 Type *&AccessTy) const { 1678 return false; 1679 } 1680 1681 /// isLegalAddressingMode - Return true if the addressing mode represented by 1682 /// AM is legal for this target, for a load/store of the specified type. 1683 /// The type may be VoidTy, in which case only return true if the addressing 1684 /// mode is legal for a load/store of any legal type. 1685 /// TODO: Handle pre/postinc as well. 1686 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 1687 1688 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1689 /// icmp immediate, that is the target has icmp instructions which can compare 1690 /// a register against the immediate without having to materialize the 1691 /// immediate into a register. 1692 virtual bool isLegalICmpImmediate(int64_t) const { 1693 return true; 1694 } 1695 1696 /// isLegalAddImmediate - Return true if the specified immediate is legal 1697 /// add immediate, that is the target has add instructions which can add 1698 /// a register with the immediate without having to materialize the 1699 /// immediate into a register. 1700 virtual bool isLegalAddImmediate(int64_t) const { 1701 return true; 1702 } 1703 1704 /// isTruncateFree - Return true if it's free to truncate a value of 1705 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1706 /// register EAX to i16 by referencing its sub-register AX. 1707 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1708 return false; 1709 } 1710 1711 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const { 1712 return false; 1713 } 1714 1715 /// isZExtFree - Return true if any actual instruction that defines a 1716 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1717 /// register. This does not necessarily include registers defined in 1718 /// unknown ways, such as incoming arguments, or copies from unknown 1719 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1720 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1721 /// all instructions that define 32-bit values implicit zero-extend the 1722 /// result out to 64 bits. 1723 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1724 return false; 1725 } 1726 1727 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const { 1728 return false; 1729 } 1730 1731 /// isZExtFree - Return true if zero-extending the specific node Val to type 1732 /// VT2 is free (either because it's implicitly zero-extended such as ARM 1733 /// ldrb / ldrh or because it's folded such as X86 zero-extending loads). 1734 virtual bool isZExtFree(SDValue Val, EVT VT2) const { 1735 return isZExtFree(Val.getValueType(), VT2); 1736 } 1737 1738 /// isFNegFree - Return true if an fneg operation is free to the point where 1739 /// it is never worthwhile to replace it with a bitwise operation. 1740 virtual bool isFNegFree(EVT) const { 1741 return false; 1742 } 1743 1744 /// isFAbsFree - Return true if an fneg operation is free to the point where 1745 /// it is never worthwhile to replace it with a bitwise operation. 1746 virtual bool isFAbsFree(EVT) const { 1747 return false; 1748 } 1749 1750 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 1751 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 1752 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 1753 /// is expanded to mul + add. 1754 virtual bool isFMAFasterThanMulAndAdd(EVT) const { 1755 return false; 1756 } 1757 1758 /// isNarrowingProfitable - Return true if it's profitable to narrow 1759 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1760 /// from i32 to i8 but not from i32 to i16. 1761 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { 1762 return false; 1763 } 1764 1765 //===--------------------------------------------------------------------===// 1766 // Div utility functions 1767 // 1768 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 1769 SelectionDAG &DAG) const; 1770 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 1771 std::vector<SDNode*> *Created) const; 1772 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 1773 std::vector<SDNode*> *Created) const; 1774 1775 1776 //===--------------------------------------------------------------------===// 1777 // Runtime Library hooks 1778 // 1779 1780 /// setLibcallName - Rename the default libcall routine name for the specified 1781 /// libcall. 1782 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1783 LibcallRoutineNames[Call] = Name; 1784 } 1785 1786 /// getLibcallName - Get the libcall routine name for the specified libcall. 1787 /// 1788 const char *getLibcallName(RTLIB::Libcall Call) const { 1789 return LibcallRoutineNames[Call]; 1790 } 1791 1792 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1793 /// result of the comparison libcall against zero. 1794 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1795 CmpLibcallCCs[Call] = CC; 1796 } 1797 1798 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1799 /// the comparison libcall against zero. 1800 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1801 return CmpLibcallCCs[Call]; 1802 } 1803 1804 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1805 /// specified libcall. 1806 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1807 LibcallCallingConvs[Call] = CC; 1808 } 1809 1810 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1811 /// specified libcall. 1812 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1813 return LibcallCallingConvs[Call]; 1814 } 1815 1816private: 1817 const TargetMachine &TM; 1818 const DataLayout *TD; 1819 const TargetLoweringObjectFile &TLOF; 1820 1821 /// PointerTy - The type to use for pointers for the default address space, 1822 /// usually i32 or i64. 1823 /// 1824 MVT PointerTy; 1825 1826 /// IsLittleEndian - True if this is a little endian target. 1827 /// 1828 bool IsLittleEndian; 1829 1830 /// SelectIsExpensive - Tells the code generator not to expand operations 1831 /// into sequences that use the select operations if possible. 1832 bool SelectIsExpensive; 1833 1834 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1835 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1836 /// a real cost model is in place. If we ever optimize for size, this will be 1837 /// set to true unconditionally. 1838 bool IntDivIsCheap; 1839 1840 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or 1841 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the 1842 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned 1843 /// integer div/rem when the operands are positive and less than 256. 1844 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths; 1845 1846 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1847 /// srl/add/sra for a signed divide by power of two, and let the target handle 1848 /// it. 1849 bool Pow2DivIsCheap; 1850 1851 /// JumpIsExpensive - Tells the code generator that it shouldn't generate 1852 /// extra flow control instructions and should attempt to combine flow 1853 /// control instructions via predication. 1854 bool JumpIsExpensive; 1855 1856 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1857 /// llvm.setjmp. Defaults to false. 1858 bool UseUnderscoreSetJmp; 1859 1860 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1861 /// llvm.longjmp. Defaults to false. 1862 bool UseUnderscoreLongJmp; 1863 1864 /// SupportJumpTables - Whether the target can generate code for jumptables. 1865 /// If it's not true, then each jumptable must be lowered into if-then-else's. 1866 bool SupportJumpTables; 1867 1868 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables. 1869 int MinimumJumpTableEntries; 1870 1871 /// BooleanContents - Information about the contents of the high-bits in 1872 /// boolean values held in a type wider than i1. See getBooleanContents. 1873 BooleanContent BooleanContents; 1874 /// BooleanVectorContents - Information about the contents of the high-bits 1875 /// in boolean vector values when the element type is wider than i1. See 1876 /// getBooleanContents. 1877 BooleanContent BooleanVectorContents; 1878 1879 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1880 /// total cycles or lowest register usage. 1881 Sched::Preference SchedPreferenceInfo; 1882 1883 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1884 unsigned JumpBufSize; 1885 1886 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1887 /// buffers 1888 unsigned JumpBufAlignment; 1889 1890 /// MinStackArgumentAlignment - The minimum alignment that any argument 1891 /// on the stack needs to have. 1892 /// 1893 unsigned MinStackArgumentAlignment; 1894 1895 /// MinFunctionAlignment - The minimum function alignment (used when 1896 /// optimizing for size, and to prevent explicitly provided alignment 1897 /// from leading to incorrect code). 1898 /// 1899 unsigned MinFunctionAlignment; 1900 1901 /// PrefFunctionAlignment - The preferred function alignment (used when 1902 /// alignment unspecified and optimizing for speed). 1903 /// 1904 unsigned PrefFunctionAlignment; 1905 1906 /// PrefLoopAlignment - The preferred loop alignment. 1907 /// 1908 unsigned PrefLoopAlignment; 1909 1910 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1911 /// be folded into the enclosed atomic intrinsic instruction by the 1912 /// combiner. 1913 bool ShouldFoldAtomicFences; 1914 1915 /// InsertFencesForAtomic - Whether the DAG builder should automatically 1916 /// insert fences and reduce ordering for atomics. (This will be set for 1917 /// for most architectures with weak memory ordering.) 1918 bool InsertFencesForAtomic; 1919 1920 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1921 /// specifies the register that llvm.savestack/llvm.restorestack should save 1922 /// and restore. 1923 unsigned StackPointerRegisterToSaveRestore; 1924 1925 /// ExceptionPointerRegister - If set to a physical register, this specifies 1926 /// the register that receives the exception address on entry to a landing 1927 /// pad. 1928 unsigned ExceptionPointerRegister; 1929 1930 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1931 /// the register that receives the exception typeid on entry to a landing 1932 /// pad. 1933 unsigned ExceptionSelectorRegister; 1934 1935 /// RegClassForVT - This indicates the default register class to use for 1936 /// each ValueType the target supports natively. 1937 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1938 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1939 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1940 1941 /// RepRegClassForVT - This indicates the "representative" register class to 1942 /// use for each ValueType the target supports natively. This information is 1943 /// used by the scheduler to track register pressure. By default, the 1944 /// representative register class is the largest legal super-reg register 1945 /// class of the register class of the specified type. e.g. On x86, i8, i16, 1946 /// and i32's representative class would be GR32. 1947 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1948 1949 /// RepRegClassCostForVT - This indicates the "cost" of the "representative" 1950 /// register class for each ValueType. The cost is used by the scheduler to 1951 /// approximate register pressure. 1952 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1953 1954 /// TransformToType - For any value types we are promoting or expanding, this 1955 /// contains the value type that we are changing to. For Expanded types, this 1956 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1957 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1958 /// by the system, this holds the same type (e.g. i32 -> i32). 1959 EVT TransformToType[MVT::LAST_VALUETYPE]; 1960 1961 /// OpActions - For each operation and each value type, keep a LegalizeAction 1962 /// that indicates how instruction selection should deal with the operation. 1963 /// Most operations are Legal (aka, supported natively by the target), but 1964 /// operations that are not should be described. Note that operations on 1965 /// non-legal value types are not described here. 1966 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1967 1968 /// LoadExtActions - For each load extension type and each value type, 1969 /// keep a LegalizeAction that indicates how instruction selection should deal 1970 /// with a load of a specific value type and extension type. 1971 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1972 1973 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1974 /// indicates whether a truncating store of a specific value type and 1975 /// truncating type is legal. 1976 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1977 1978 /// IndexedModeActions - For each indexed mode and each value type, 1979 /// keep a pair of LegalizeAction that indicates how instruction 1980 /// selection should deal with the load / store. The first dimension is the 1981 /// value_type for the reference. The second dimension represents the various 1982 /// modes for load store. 1983 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1984 1985 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1986 /// LegalizeAction that indicates how instruction selection should 1987 /// deal with the condition code. 1988 /// Because each CC action takes up 2 bits, we need to have the array size 1989 /// be large enough to fit all of the value types. This can be done by 1990 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one. 1991 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1]; 1992 1993 ValueTypeActionImpl ValueTypeActions; 1994 1995public: 1996 LegalizeKind 1997 getTypeConversion(LLVMContext &Context, EVT VT) const { 1998 // If this is a simple type, use the ComputeRegisterProp mechanism. 1999 if (VT.isSimple()) { 2000 assert((unsigned)VT.getSimpleVT().SimpleTy < 2001 array_lengthof(TransformToType)); 2002 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 2003 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT()); 2004 2005 assert( 2006 (!(NVT.isSimple() && LA != TypeLegal) || 2007 ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != TypePromoteInteger) 2008 && "Promote may not follow Expand or Promote"); 2009 2010 if (LA == TypeSplitVector) 2011 NVT = EVT::getVectorVT(Context, VT.getVectorElementType(), 2012 VT.getVectorNumElements() / 2); 2013 return LegalizeKind(LA, NVT); 2014 } 2015 2016 // Handle Extended Scalar Types. 2017 if (!VT.isVector()) { 2018 assert(VT.isInteger() && "Float types must be simple"); 2019 unsigned BitSize = VT.getSizeInBits(); 2020 // First promote to a power-of-two size, then expand if necessary. 2021 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 2022 EVT NVT = VT.getRoundIntegerType(Context); 2023 assert(NVT != VT && "Unable to round integer VT"); 2024 LegalizeKind NextStep = getTypeConversion(Context, NVT); 2025 // Avoid multi-step promotion. 2026 if (NextStep.first == TypePromoteInteger) return NextStep; 2027 // Return rounded integer type. 2028 return LegalizeKind(TypePromoteInteger, NVT); 2029 } 2030 2031 return LegalizeKind(TypeExpandInteger, 2032 EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); 2033 } 2034 2035 // Handle vector types. 2036 unsigned NumElts = VT.getVectorNumElements(); 2037 EVT EltVT = VT.getVectorElementType(); 2038 2039 // Vectors with only one element are always scalarized. 2040 if (NumElts == 1) 2041 return LegalizeKind(TypeScalarizeVector, EltVT); 2042 2043 // Try to widen vector elements until a legal type is found. 2044 if (EltVT.isInteger()) { 2045 // Vectors with a number of elements that is not a power of two are always 2046 // widened, for example <3 x float> -> <4 x float>. 2047 if (!VT.isPow2VectorType()) { 2048 NumElts = (unsigned)NextPowerOf2(NumElts); 2049 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 2050 return LegalizeKind(TypeWidenVector, NVT); 2051 } 2052 2053 // Examine the element type. 2054 LegalizeKind LK = getTypeConversion(Context, EltVT); 2055 2056 // If type is to be expanded, split the vector. 2057 // <4 x i140> -> <2 x i140> 2058 if (LK.first == TypeExpandInteger) 2059 return LegalizeKind(TypeSplitVector, 2060 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 2061 2062 // Promote the integer element types until a legal vector type is found 2063 // or until the element integer type is too big. If a legal type was not 2064 // found, fallback to the usual mechanism of widening/splitting the 2065 // vector. 2066 while (1) { 2067 // Increase the bitwidth of the element to the next pow-of-two 2068 // (which is greater than 8 bits). 2069 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() 2070 ).getRoundIntegerType(Context); 2071 2072 // Stop trying when getting a non-simple element type. 2073 // Note that vector elements may be greater than legal vector element 2074 // types. Example: X86 XMM registers hold 64bit element on 32bit systems. 2075 if (!EltVT.isSimple()) break; 2076 2077 // Build a new vector type and check if it is legal. 2078 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 2079 // Found a legal promoted vector type. 2080 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 2081 return LegalizeKind(TypePromoteInteger, 2082 EVT::getVectorVT(Context, EltVT, NumElts)); 2083 } 2084 } 2085 2086 // Try to widen the vector until a legal type is found. 2087 // If there is no wider legal type, split the vector. 2088 while (1) { 2089 // Round up to the next power of 2. 2090 NumElts = (unsigned)NextPowerOf2(NumElts); 2091 2092 // If there is no simple vector type with this many elements then there 2093 // cannot be a larger legal vector type. Note that this assumes that 2094 // there are no skipped intermediate vector types in the simple types. 2095 if (!EltVT.isSimple()) break; 2096 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 2097 if (LargerVector == MVT()) break; 2098 2099 // If this type is legal then widen the vector. 2100 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 2101 return LegalizeKind(TypeWidenVector, LargerVector); 2102 } 2103 2104 // Widen odd vectors to next power of two. 2105 if (!VT.isPow2VectorType()) { 2106 EVT NVT = VT.getPow2VectorType(Context); 2107 return LegalizeKind(TypeWidenVector, NVT); 2108 } 2109 2110 // Vectors with illegal element types are expanded. 2111 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 2112 return LegalizeKind(TypeSplitVector, NVT); 2113 } 2114 2115private: 2116 std::vector<std::pair<EVT, const TargetRegisterClass*> > AvailableRegClasses; 2117 2118 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 2119 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 2120 /// which sets a bit in this array. 2121 unsigned char 2122 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 2123 2124 /// PromoteToType - For operations that must be promoted to a specific type, 2125 /// this holds the destination type. This map should be sparse, so don't hold 2126 /// it as an array. 2127 /// 2128 /// Targets add entries to this map with AddPromotedToType(..), clients access 2129 /// this with getTypeToPromoteTo(..). 2130 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 2131 PromoteToType; 2132 2133 /// LibcallRoutineNames - Stores the name each libcall. 2134 /// 2135 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 2136 2137 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 2138 /// of each of the comparison libcall against zero. 2139 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 2140 2141 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 2142 /// libcall. 2143 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 2144 2145protected: 2146 /// When lowering \@llvm.memset this field specifies the maximum number of 2147 /// store operations that may be substituted for the call to memset. Targets 2148 /// must set this value based on the cost threshold for that target. Targets 2149 /// should assume that the memset will be done using as many of the largest 2150 /// store operations first, followed by smaller ones, if necessary, per 2151 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 2152 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 2153 /// store. This only applies to setting a constant array of a constant size. 2154 /// @brief Specify maximum number of store instructions per memset call. 2155 unsigned maxStoresPerMemset; 2156 2157 /// Maximum number of stores operations that may be substituted for the call 2158 /// to memset, used for functions with OptSize attribute. 2159 unsigned maxStoresPerMemsetOptSize; 2160 2161 /// When lowering \@llvm.memcpy this field specifies the maximum number of 2162 /// store operations that may be substituted for a call to memcpy. Targets 2163 /// must set this value based on the cost threshold for that target. Targets 2164 /// should assume that the memcpy will be done using as many of the largest 2165 /// store operations first, followed by smaller ones, if necessary, per 2166 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 2167 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 2168 /// and one 1-byte store. This only applies to copying a constant array of 2169 /// constant size. 2170 /// @brief Specify maximum bytes of store instructions per memcpy call. 2171 unsigned maxStoresPerMemcpy; 2172 2173 /// Maximum number of store operations that may be substituted for a call 2174 /// to memcpy, used for functions with OptSize attribute. 2175 unsigned maxStoresPerMemcpyOptSize; 2176 2177 /// When lowering \@llvm.memmove this field specifies the maximum number of 2178 /// store instructions that may be substituted for a call to memmove. Targets 2179 /// must set this value based on the cost threshold for that target. Targets 2180 /// should assume that the memmove will be done using as many of the largest 2181 /// store operations first, followed by smaller ones, if necessary, per 2182 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 2183 /// with 8-bit alignment would result in nine 1-byte stores. This only 2184 /// applies to copying a constant array of constant size. 2185 /// @brief Specify maximum bytes of store instructions per memmove call. 2186 unsigned maxStoresPerMemmove; 2187 2188 /// Maximum number of store instructions that may be substituted for a call 2189 /// to memmove, used for functions with OpSize attribute. 2190 unsigned maxStoresPerMemmoveOptSize; 2191 2192 /// This field specifies whether the target can benefit from code placement 2193 /// optimization. 2194 bool benefitFromCodePlacementOpt; 2195 2196 /// predictableSelectIsExpensive - Tells the code generator that select is 2197 /// more expensive than a branch if the branch is usually predicted right. 2198 bool predictableSelectIsExpensive; 2199 2200private: 2201 /// isLegalRC - Return true if the value types that can be represented by the 2202 /// specified register class are all legal. 2203 bool isLegalRC(const TargetRegisterClass *RC) const; 2204}; 2205 2206/// GetReturnInfo - Given an LLVM IR type and return type attributes, 2207/// compute the return value EVTs and flags, and optionally also 2208/// the offsets, if the return value is being lowered to memory. 2209void GetReturnInfo(Type* ReturnType, Attributes attr, 2210 SmallVectorImpl<ISD::OutputArg> &Outs, 2211 const TargetLowering &TLI); 2212 2213} // end llvm namespace 2214 2215#endif 2216