TargetLowering.h revision c34693f6efc670b71e11f3479844c36d9696b535
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// 10/// \file 11/// This file describes how to lower LLVM code to machine code. This has two 12/// main components: 13/// 14/// 1. Which ValueTypes are natively supported by the target. 15/// 2. Which operations are supported for supported ValueTypes. 16/// 3. Cost thresholds for alternative implementations of certain operations. 17/// 18/// In addition it has a few other components, like information about FP 19/// immediates. 20/// 21//===----------------------------------------------------------------------===// 22 23#ifndef LLVM_TARGET_TARGETLOWERING_H 24#define LLVM_TARGET_TARGETLOWERING_H 25 26#include "llvm/ADT/DenseMap.h" 27#include "llvm/CodeGen/DAGCombine.h" 28#include "llvm/CodeGen/RuntimeLibcalls.h" 29#include "llvm/CodeGen/SelectionDAGNodes.h" 30#include "llvm/IR/Attributes.h" 31#include "llvm/IR/CallingConv.h" 32#include "llvm/IR/InlineAsm.h" 33#include "llvm/Support/CallSite.h" 34#include "llvm/Target/TargetCallingConv.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class CallInst; 42 class CCState; 43 class FastISel; 44 class FunctionLoweringInfo; 45 class ImmutableCallSite; 46 class IntrinsicInst; 47 class MachineBasicBlock; 48 class MachineFunction; 49 class MachineInstr; 50 class MachineJumpTableInfo; 51 class MCContext; 52 class MCExpr; 53 template<typename T> class SmallVectorImpl; 54 class DataLayout; 55 class TargetRegisterClass; 56 class TargetLibraryInfo; 57 class TargetLoweringObjectFile; 58 class Value; 59 60 namespace Sched { 61 enum Preference { 62 None, // No preference 63 Source, // Follow source order. 64 RegPressure, // Scheduling for lowest register pressure. 65 Hybrid, // Scheduling for both latency and register pressure. 66 ILP, // Scheduling for ILP in low register pressure mode. 67 VLIW // Scheduling for VLIW targets. 68 }; 69 } 70 71/// This base class for TargetLowering contains the SelectionDAG-independent 72/// parts that can be used from the rest of CodeGen. 73class TargetLoweringBase { 74 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 75 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 76 77public: 78 /// This enum indicates whether operations are valid for a target, and if not, 79 /// what action should be used to make them valid. 80 enum LegalizeAction { 81 Legal, // The target natively supports this operation. 82 Promote, // This operation should be executed in a larger type. 83 Expand, // Try to expand this to other ops, otherwise use a libcall. 84 Custom // Use the LowerOperation hook to implement custom lowering. 85 }; 86 87 /// This enum indicates whether a types are legal for a target, and if not, 88 /// what action should be used to make them valid. 89 enum LegalizeTypeAction { 90 TypeLegal, // The target natively supports this type. 91 TypePromoteInteger, // Replace this integer with a larger one. 92 TypeExpandInteger, // Split this integer into two of half the size. 93 TypeSoftenFloat, // Convert this float to a same size integer type. 94 TypeExpandFloat, // Split this float into two of half the size. 95 TypeScalarizeVector, // Replace this one-element vector with its element. 96 TypeSplitVector, // Split this vector into two of half the size. 97 TypeWidenVector // This vector should be widened into a larger vector. 98 }; 99 100 /// LegalizeKind holds the legalization kind that needs to happen to EVT 101 /// in order to type-legalize it. 102 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; 103 104 /// Enum that describes how the target represents true/false values. 105 enum BooleanContent { 106 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 107 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 108 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 109 }; 110 111 /// Enum that describes what type of support for selects the target has. 112 enum SelectSupportKind { 113 ScalarValSelect, // The target supports scalar selects (ex: cmov). 114 ScalarCondVectorVal, // The target supports selects with a scalar condition 115 // and vector values (ex: cmov). 116 VectorMaskSelect // The target supports vector selects with a vector 117 // mask (ex: x86 blends). 118 }; 119 120 static ISD::NodeType getExtendForContent(BooleanContent Content) { 121 switch (Content) { 122 case UndefinedBooleanContent: 123 // Extend by adding rubbish bits. 124 return ISD::ANY_EXTEND; 125 case ZeroOrOneBooleanContent: 126 // Extend by adding zero bits. 127 return ISD::ZERO_EXTEND; 128 case ZeroOrNegativeOneBooleanContent: 129 // Extend by copying the sign bit. 130 return ISD::SIGN_EXTEND; 131 } 132 llvm_unreachable("Invalid content kind"); 133 } 134 135 /// NOTE: The constructor takes ownership of TLOF. 136 explicit TargetLoweringBase(const TargetMachine &TM, 137 const TargetLoweringObjectFile *TLOF); 138 virtual ~TargetLoweringBase(); 139 140protected: 141 /// \brief Initialize all of the actions to default values. 142 void initActions(); 143 144public: 145 const TargetMachine &getTargetMachine() const { return TM; } 146 const DataLayout *getDataLayout() const { return TD; } 147 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 148 149 bool isBigEndian() const { return !IsLittleEndian; } 150 bool isLittleEndian() const { return IsLittleEndian; } 151 // Return the pointer type for the given address space, defaults to 152 // the pointer type from the data layout. 153 // FIXME: The default needs to be removed once all the code is updated. 154 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const; 155 unsigned getPointerSizeInBits(uint32_t AS = 0) const; 156 unsigned getPointerTypeSizeInBits(Type *Ty) const; 157 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const; 158 159 EVT getShiftAmountTy(EVT LHSTy) const; 160 161 /// Returns the type to be used for the index operand of: 162 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, 163 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR 164 virtual MVT getVectorIdxTy() const { 165 return getPointerTy(); 166 } 167 168 /// Return true if the select operation is expensive for this target. 169 bool isSelectExpensive() const { return SelectIsExpensive; } 170 171 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const { 172 return true; 173 } 174 175 /// Return true if a vector of the given type should be split 176 /// (TypeSplitVector) instead of promoted (TypePromoteInteger) during type 177 /// legalization. 178 virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; } 179 180 /// Return true if integer divide is usually cheaper than a sequence of 181 /// several shifts, adds, and multiplies for this target. 182 bool isIntDivCheap() const { return IntDivIsCheap; } 183 184 /// Returns true if target has indicated at least one type should be bypassed. 185 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); } 186 187 /// Returns map of slow types for division or remainder with corresponding 188 /// fast types 189 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const { 190 return BypassSlowDivWidths; 191 } 192 193 /// Return true if pow2 div is cheaper than a chain of srl/add/sra. 194 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 195 196 /// Return true if Flow Control is an expensive operation that should be 197 /// avoided. 198 bool isJumpExpensive() const { return JumpIsExpensive; } 199 200 /// Return true if selects are only cheaper than branches if the branch is 201 /// unlikely to be predicted right. 202 bool isPredictableSelectExpensive() const { 203 return PredictableSelectIsExpensive; 204 } 205 206 /// Return the ValueType of the result of SETCC operations. Also used to 207 /// obtain the target's preferred type for the condition operand of SELECT and 208 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other 209 /// since there are no other operands to get a type hint from. 210 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 211 212 /// Return the ValueType for comparison libcalls. Comparions libcalls include 213 /// floating point comparion calls, and Ordered/Unordered check calls on 214 /// floating point numbers. 215 virtual 216 MVT::SimpleValueType getCmpLibcallReturnType() const; 217 218 /// For targets without i1 registers, this gives the nature of the high-bits 219 /// of boolean values held in types wider than i1. 220 /// 221 /// "Boolean values" are special true/false values produced by nodes like 222 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 223 /// Not to be confused with general values promoted from i1. Some cpus 224 /// distinguish between vectors of boolean and scalars; the isVec parameter 225 /// selects between the two kinds. For example on X86 a scalar boolean should 226 /// be zero extended from i1, while the elements of a vector of booleans 227 /// should be sign extended from i1. 228 BooleanContent getBooleanContents(bool isVec) const { 229 return isVec ? BooleanVectorContents : BooleanContents; 230 } 231 232 /// Return target scheduling preference. 233 Sched::Preference getSchedulingPreference() const { 234 return SchedPreferenceInfo; 235 } 236 237 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics 238 /// for different nodes. This function returns the preference (or none) for 239 /// the given node. 240 virtual Sched::Preference getSchedulingPreference(SDNode *) const { 241 return Sched::None; 242 } 243 244 /// Return the register class that should be used for the specified value 245 /// type. 246 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { 247 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 248 assert(RC && "This value type is not natively supported!"); 249 return RC; 250 } 251 252 /// Return the 'representative' register class for the specified value 253 /// type. 254 /// 255 /// The 'representative' register class is the largest legal super-reg 256 /// register class for the register class of the value type. For example, on 257 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep 258 /// register class is GR64 on x86_64. 259 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { 260 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; 261 return RC; 262 } 263 264 /// Return the cost of the 'representative' register class for the specified 265 /// value type. 266 virtual uint8_t getRepRegClassCostFor(MVT VT) const { 267 return RepRegClassCostForVT[VT.SimpleTy]; 268 } 269 270 /// Return true if the target has native support for the specified value type. 271 /// This means that it has a register that directly holds it without 272 /// promotions or expansions. 273 bool isTypeLegal(EVT VT) const { 274 assert(!VT.isSimple() || 275 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 276 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 277 } 278 279 class ValueTypeActionImpl { 280 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum 281 /// that indicates how instruction selection should deal with the type. 282 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 283 284 public: 285 ValueTypeActionImpl() { 286 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 287 } 288 289 LegalizeTypeAction getTypeAction(MVT VT) const { 290 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; 291 } 292 293 void setTypeAction(MVT VT, LegalizeTypeAction Action) { 294 unsigned I = VT.SimpleTy; 295 ValueTypeActions[I] = Action; 296 } 297 }; 298 299 const ValueTypeActionImpl &getValueTypeActions() const { 300 return ValueTypeActions; 301 } 302 303 /// Return how we should legalize values of this type, either it is already 304 /// legal (return 'Legal') or we need to promote it to a larger type (return 305 /// 'Promote'), or we need to expand it into multiple registers of smaller 306 /// integer type (return 'Expand'). 'Custom' is not an option. 307 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { 308 return getTypeConversion(Context, VT).first; 309 } 310 LegalizeTypeAction getTypeAction(MVT VT) const { 311 return ValueTypeActions.getTypeAction(VT); 312 } 313 314 /// For types supported by the target, this is an identity function. For 315 /// types that must be promoted to larger types, this returns the larger type 316 /// to promote to. For integer types that are larger than the largest integer 317 /// register, this contains one step in the expansion to get to the smaller 318 /// register. For illegal floating point types, this returns the integer type 319 /// to transform to. 320 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 321 return getTypeConversion(Context, VT).second; 322 } 323 324 /// For types supported by the target, this is an identity function. For 325 /// types that must be expanded (i.e. integer types that are larger than the 326 /// largest integer register or illegal floating point types), this returns 327 /// the largest legal type it will be expanded to. 328 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 329 assert(!VT.isVector()); 330 while (true) { 331 switch (getTypeAction(Context, VT)) { 332 case TypeLegal: 333 return VT; 334 case TypeExpandInteger: 335 VT = getTypeToTransformTo(Context, VT); 336 break; 337 default: 338 llvm_unreachable("Type is not legal nor is it to be expanded!"); 339 } 340 } 341 } 342 343 /// Vector types are broken down into some number of legal first class types. 344 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 345 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 346 /// turns into 4 EVT::i32 values with both PPC and X86. 347 /// 348 /// This method returns the number of registers needed, and the VT for each 349 /// register. It also returns the VT and quantity of the intermediate values 350 /// before they are promoted/expanded. 351 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 352 EVT &IntermediateVT, 353 unsigned &NumIntermediates, 354 MVT &RegisterVT) const; 355 356 struct IntrinsicInfo { 357 unsigned opc; // target opcode 358 EVT memVT; // memory VT 359 const Value* ptrVal; // value representing memory location 360 int offset; // offset off of ptrVal 361 unsigned align; // alignment 362 bool vol; // is volatile? 363 bool readMem; // reads memory? 364 bool writeMem; // writes memory? 365 }; 366 367 /// Given an intrinsic, checks if on the target the intrinsic will need to map 368 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns 369 /// true and store the intrinsic information into the IntrinsicInfo that was 370 /// passed to the function. 371 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 372 unsigned /*Intrinsic*/) const { 373 return false; 374 } 375 376 /// Returns true if the target can instruction select the specified FP 377 /// immediate natively. If false, the legalizer will materialize the FP 378 /// immediate as a load from a constant pool. 379 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const { 380 return false; 381 } 382 383 /// Targets can use this to indicate that they only support *some* 384 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a 385 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be 386 /// legal. 387 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 388 EVT /*VT*/) const { 389 return true; 390 } 391 392 /// Returns true if the operation can trap for the value type. 393 /// 394 /// VT must be a legal type. By default, we optimistically assume most 395 /// operations don't trap except for divide and remainder. 396 virtual bool canOpTrap(unsigned Op, EVT VT) const; 397 398 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to 399 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace 400 /// a VAND with a constant pool entry. 401 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 402 EVT /*VT*/) const { 403 return false; 404 } 405 406 /// Return how this operation should be treated: either it is legal, needs to 407 /// be promoted to a larger size, needs to be expanded to some other code 408 /// sequence, or the target has a custom expander for it. 409 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 410 if (VT.isExtended()) return Expand; 411 // If a target-specific SDNode requires legalization, require the target 412 // to provide custom legalization for it. 413 if (Op > array_lengthof(OpActions[0])) return Custom; 414 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 415 return (LegalizeAction)OpActions[I][Op]; 416 } 417 418 /// Return true if the specified operation is legal on this target or can be 419 /// made legal with custom lowering. This is used to help guide high-level 420 /// lowering decisions. 421 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 422 return (VT == MVT::Other || isTypeLegal(VT)) && 423 (getOperationAction(Op, VT) == Legal || 424 getOperationAction(Op, VT) == Custom); 425 } 426 427 /// Return true if the specified operation is legal on this target or can be 428 /// made legal using promotion. This is used to help guide high-level lowering 429 /// decisions. 430 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const { 431 return (VT == MVT::Other || isTypeLegal(VT)) && 432 (getOperationAction(Op, VT) == Legal || 433 getOperationAction(Op, VT) == Promote); 434 } 435 436 /// Return true if the specified operation is illegal on this target or 437 /// unlikely to be made legal with custom lowering. This is used to help guide 438 /// high-level lowering decisions. 439 bool isOperationExpand(unsigned Op, EVT VT) const { 440 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); 441 } 442 443 /// Return true if the specified operation is legal on this target. 444 bool isOperationLegal(unsigned Op, EVT VT) const { 445 return (VT == MVT::Other || isTypeLegal(VT)) && 446 getOperationAction(Op, VT) == Legal; 447 } 448 449 /// Return how this load with extension should be treated: either it is legal, 450 /// needs to be promoted to a larger size, needs to be expanded to some other 451 /// code sequence, or the target has a custom expander for it. 452 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const { 453 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 454 "Table isn't big enough!"); 455 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType]; 456 } 457 458 /// Return true if the specified load with extension is legal on this target. 459 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 460 return VT.isSimple() && 461 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal; 462 } 463 464 /// Return how this store with truncation should be treated: either it is 465 /// legal, needs to be promoted to a larger size, needs to be expanded to some 466 /// other code sequence, or the target has a custom expander for it. 467 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const { 468 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 469 "Table isn't big enough!"); 470 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy] 471 [MemVT.SimpleTy]; 472 } 473 474 /// Return true if the specified store with truncation is legal on this 475 /// target. 476 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 477 return isTypeLegal(ValVT) && MemVT.isSimple() && 478 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal; 479 } 480 481 /// Return how the indexed load should be treated: either it is legal, needs 482 /// to be promoted to a larger size, needs to be expanded to some other code 483 /// sequence, or the target has a custom expander for it. 484 LegalizeAction 485 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 486 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 487 "Table isn't big enough!"); 488 unsigned Ty = (unsigned)VT.SimpleTy; 489 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 490 } 491 492 /// Return true if the specified indexed load is legal on this target. 493 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 494 return VT.isSimple() && 495 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || 496 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); 497 } 498 499 /// Return how the indexed store should be treated: either it is legal, needs 500 /// to be promoted to a larger size, needs to be expanded to some other code 501 /// sequence, or the target has a custom expander for it. 502 LegalizeAction 503 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 504 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 505 "Table isn't big enough!"); 506 unsigned Ty = (unsigned)VT.SimpleTy; 507 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 508 } 509 510 /// Return true if the specified indexed load is legal on this target. 511 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 512 return VT.isSimple() && 513 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || 514 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); 515 } 516 517 /// Return how the condition code should be treated: either it is legal, needs 518 /// to be expanded to some other code sequence, or the target has a custom 519 /// expander for it. 520 LegalizeAction 521 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 522 assert((unsigned)CC < array_lengthof(CondCodeActions) && 523 (unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 && 524 "Table isn't big enough!"); 525 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 526 /// value and the upper 27 bits index into the second dimension of the 527 /// array to select what 64bit value to use. 528 LegalizeAction Action = (LegalizeAction) 529 ((CondCodeActions[CC][VT.SimpleTy >> 5] >> (2*(VT.SimpleTy & 0x1F))) & 3); 530 assert(Action != Promote && "Can't promote condition code!"); 531 return Action; 532 } 533 534 /// Return true if the specified condition code is legal on this target. 535 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 536 return 537 getCondCodeAction(CC, VT) == Legal || 538 getCondCodeAction(CC, VT) == Custom; 539 } 540 541 542 /// If the action for this operation is to promote, this method returns the 543 /// ValueType to promote to. 544 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 545 assert(getOperationAction(Op, VT) == Promote && 546 "This operation isn't promoted!"); 547 548 // See if this has an explicit type specified. 549 std::map<std::pair<unsigned, MVT::SimpleValueType>, 550 MVT::SimpleValueType>::const_iterator PTTI = 551 PromoteToType.find(std::make_pair(Op, VT.SimpleTy)); 552 if (PTTI != PromoteToType.end()) return PTTI->second; 553 554 assert((VT.isInteger() || VT.isFloatingPoint()) && 555 "Cannot autopromote this type, add it with AddPromotedToType."); 556 557 MVT NVT = VT; 558 do { 559 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1); 560 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 561 "Didn't find type to promote to!"); 562 } while (!isTypeLegal(NVT) || 563 getOperationAction(Op, NVT) == Promote); 564 return NVT; 565 } 566 567 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM 568 /// operations except for the pointer size. If AllowUnknown is true, this 569 /// will return MVT::Other for types with no EVT counterpart (e.g. structs), 570 /// otherwise it will assert. 571 EVT getValueType(Type *Ty, bool AllowUnknown = false) const { 572 // Lower scalar pointers to native pointer types. 573 if (Ty->isPointerTy()) return getPointerTy(Ty->getPointerAddressSpace()); 574 575 if (Ty->isVectorTy()) { 576 VectorType *VTy = cast<VectorType>(Ty); 577 Type *Elm = VTy->getElementType(); 578 // Lower vectors of pointers to native pointer types. 579 if (Elm->isPointerTy()) 580 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext()); 581 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), 582 VTy->getNumElements()); 583 } 584 return EVT::getEVT(Ty, AllowUnknown); 585 } 586 587 /// Return the MVT corresponding to this LLVM type. See getValueType. 588 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const { 589 return getValueType(Ty, AllowUnknown).getSimpleVT(); 590 } 591 592 /// Return the desired alignment for ByVal aggregate function arguments in the 593 /// caller parameter area. This is the actual alignment, not its logarithm. 594 virtual unsigned getByValTypeAlignment(Type *Ty) const; 595 596 /// Return the type of registers that this ValueType will eventually require. 597 MVT getRegisterType(MVT VT) const { 598 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 599 return RegisterTypeForVT[VT.SimpleTy]; 600 } 601 602 /// Return the type of registers that this ValueType will eventually require. 603 MVT getRegisterType(LLVMContext &Context, EVT VT) const { 604 if (VT.isSimple()) { 605 assert((unsigned)VT.getSimpleVT().SimpleTy < 606 array_lengthof(RegisterTypeForVT)); 607 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 608 } 609 if (VT.isVector()) { 610 EVT VT1; 611 MVT RegisterVT; 612 unsigned NumIntermediates; 613 (void)getVectorTypeBreakdown(Context, VT, VT1, 614 NumIntermediates, RegisterVT); 615 return RegisterVT; 616 } 617 if (VT.isInteger()) { 618 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 619 } 620 llvm_unreachable("Unsupported extended type!"); 621 } 622 623 /// Return the number of registers that this ValueType will eventually 624 /// require. 625 /// 626 /// This is one for any types promoted to live in larger registers, but may be 627 /// more than one for types (like i64) that are split into pieces. For types 628 /// like i140, which are first promoted then expanded, it is the number of 629 /// registers needed to hold all the bits of the original type. For an i140 630 /// on a 32 bit machine this means 5 registers. 631 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 632 if (VT.isSimple()) { 633 assert((unsigned)VT.getSimpleVT().SimpleTy < 634 array_lengthof(NumRegistersForVT)); 635 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 636 } 637 if (VT.isVector()) { 638 EVT VT1; 639 MVT VT2; 640 unsigned NumIntermediates; 641 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 642 } 643 if (VT.isInteger()) { 644 unsigned BitWidth = VT.getSizeInBits(); 645 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 646 return (BitWidth + RegWidth - 1) / RegWidth; 647 } 648 llvm_unreachable("Unsupported extended type!"); 649 } 650 651 /// If true, then instruction selection should seek to shrink the FP constant 652 /// of the specified type to a smaller type in order to save space and / or 653 /// reduce runtime. 654 virtual bool ShouldShrinkFPConstant(EVT) const { return true; } 655 656 /// If true, the target has custom DAG combine transformations that it can 657 /// perform for the specified node. 658 bool hasTargetDAGCombine(ISD::NodeType NT) const { 659 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 660 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 661 } 662 663 /// \brief Get maximum # of store operations permitted for llvm.memset 664 /// 665 /// This function returns the maximum number of store operations permitted 666 /// to replace a call to llvm.memset. The value is set by the target at the 667 /// performance threshold for such a replacement. If OptSize is true, 668 /// return the limit for functions that have OptSize attribute. 669 unsigned getMaxStoresPerMemset(bool OptSize) const { 670 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset; 671 } 672 673 /// \brief Get maximum # of store operations permitted for llvm.memcpy 674 /// 675 /// This function returns the maximum number of store operations permitted 676 /// to replace a call to llvm.memcpy. The value is set by the target at the 677 /// performance threshold for such a replacement. If OptSize is true, 678 /// return the limit for functions that have OptSize attribute. 679 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 680 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy; 681 } 682 683 /// \brief Get maximum # of store operations permitted for llvm.memmove 684 /// 685 /// This function returns the maximum number of store operations permitted 686 /// to replace a call to llvm.memmove. The value is set by the target at the 687 /// performance threshold for such a replacement. If OptSize is true, 688 /// return the limit for functions that have OptSize attribute. 689 unsigned getMaxStoresPerMemmove(bool OptSize) const { 690 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove; 691 } 692 693 /// \brief Determine if the target supports unaligned memory accesses. 694 /// 695 /// This function returns true if the target allows unaligned memory accesses. 696 /// of the specified type. If true, it also returns whether the unaligned 697 /// memory access is "fast" in the second argument by reference. This is used, 698 /// for example, in situations where an array copy/move/set is converted to a 699 /// sequence of store operations. It's use helps to ensure that such 700 /// replacements don't generate code that causes an alignment error (trap) on 701 /// the target machine. 702 virtual bool allowsUnalignedMemoryAccesses(EVT, bool * /*Fast*/ = 0) const { 703 return false; 704 } 705 706 /// Returns the target specific optimal type for load and store operations as 707 /// a result of memset, memcpy, and memmove lowering. 708 /// 709 /// If DstAlign is zero that means it's safe to destination alignment can 710 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't 711 /// a need to check it against alignment requirement, probably because the 712 /// source does not need to be loaded. If 'IsMemset' is true, that means it's 713 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of 714 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it 715 /// does not need to be loaded. It returns EVT::Other if the type should be 716 /// determined using generic target-independent logic. 717 virtual EVT getOptimalMemOpType(uint64_t /*Size*/, 718 unsigned /*DstAlign*/, unsigned /*SrcAlign*/, 719 bool /*IsMemset*/, 720 bool /*ZeroMemset*/, 721 bool /*MemcpyStrSrc*/, 722 MachineFunction &/*MF*/) const { 723 return MVT::Other; 724 } 725 726 /// Returns true if it's safe to use load / store of the specified type to 727 /// expand memcpy / memset inline. 728 /// 729 /// This is mostly true for all types except for some special cases. For 730 /// example, on X86 targets without SSE2 f64 load / store are done with fldl / 731 /// fstpl which also does type conversion. Note the specified type doesn't 732 /// have to be legal as the hook is used before type legalization. 733 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; } 734 735 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp. 736 bool usesUnderscoreSetJmp() const { 737 return UseUnderscoreSetJmp; 738 } 739 740 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp. 741 bool usesUnderscoreLongJmp() const { 742 return UseUnderscoreLongJmp; 743 } 744 745 /// Return whether the target can generate code for jump tables. 746 bool supportJumpTables() const { 747 return SupportJumpTables; 748 } 749 750 /// Return integer threshold on number of blocks to use jump tables rather 751 /// than if sequence. 752 int getMinimumJumpTableEntries() const { 753 return MinimumJumpTableEntries; 754 } 755 756 /// If a physical register, this specifies the register that 757 /// llvm.savestack/llvm.restorestack should save and restore. 758 unsigned getStackPointerRegisterToSaveRestore() const { 759 return StackPointerRegisterToSaveRestore; 760 } 761 762 /// If a physical register, this returns the register that receives the 763 /// exception address on entry to a landing pad. 764 unsigned getExceptionPointerRegister() const { 765 return ExceptionPointerRegister; 766 } 767 768 /// If a physical register, this returns the register that receives the 769 /// exception typeid on entry to a landing pad. 770 unsigned getExceptionSelectorRegister() const { 771 return ExceptionSelectorRegister; 772 } 773 774 /// Returns the target's jmp_buf size in bytes (if never set, the default is 775 /// 200) 776 unsigned getJumpBufSize() const { 777 return JumpBufSize; 778 } 779 780 /// Returns the target's jmp_buf alignment in bytes (if never set, the default 781 /// is 0) 782 unsigned getJumpBufAlignment() const { 783 return JumpBufAlignment; 784 } 785 786 /// Return the minimum stack alignment of an argument. 787 unsigned getMinStackArgumentAlignment() const { 788 return MinStackArgumentAlignment; 789 } 790 791 /// Return the minimum function alignment. 792 unsigned getMinFunctionAlignment() const { 793 return MinFunctionAlignment; 794 } 795 796 /// Return the preferred function alignment. 797 unsigned getPrefFunctionAlignment() const { 798 return PrefFunctionAlignment; 799 } 800 801 /// Return the preferred loop alignment. 802 unsigned getPrefLoopAlignment() const { 803 return PrefLoopAlignment; 804 } 805 806 /// Return whether the DAG builder should automatically insert fences and 807 /// reduce ordering for atomics. 808 bool getInsertFencesForAtomic() const { 809 return InsertFencesForAtomic; 810 } 811 812 /// Return true if the target stores stack protector cookies at a fixed offset 813 /// in some non-standard address space, and populates the address space and 814 /// offset as appropriate. 815 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/, 816 unsigned &/*Offset*/) const { 817 return false; 818 } 819 820 /// Returns the maximal possible offset which can be used for loads / stores 821 /// from the global. 822 virtual unsigned getMaximalGlobalOffset() const { 823 return 0; 824 } 825 826 //===--------------------------------------------------------------------===// 827 /// \name Helpers for TargetTransformInfo implementations 828 /// @{ 829 830 /// Get the ISD node that corresponds to the Instruction class opcode. 831 int InstructionOpcodeToISD(unsigned Opcode) const; 832 833 /// Estimate the cost of type-legalization and the legalized type. 834 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const; 835 836 /// @} 837 838 //===--------------------------------------------------------------------===// 839 // TargetLowering Configuration Methods - These methods should be invoked by 840 // the derived class constructor to configure this object for the target. 841 // 842 843 /// \brief Reset the operation actions based on target options. 844 virtual void resetOperationActions() {} 845 846protected: 847 /// Specify how the target extends the result of a boolean value from i1 to a 848 /// wider type. See getBooleanContents. 849 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 850 851 /// Specify how the target extends the result of a vector boolean value from a 852 /// vector of i1 to a wider type. See getBooleanContents. 853 void setBooleanVectorContents(BooleanContent Ty) { 854 BooleanVectorContents = Ty; 855 } 856 857 /// Specify the target scheduling preference. 858 void setSchedulingPreference(Sched::Preference Pref) { 859 SchedPreferenceInfo = Pref; 860 } 861 862 /// Indicate whether this target prefers to use _setjmp to implement 863 /// llvm.setjmp or the non _ version. Defaults to false. 864 void setUseUnderscoreSetJmp(bool Val) { 865 UseUnderscoreSetJmp = Val; 866 } 867 868 /// Indicate whether this target prefers to use _longjmp to implement 869 /// llvm.longjmp or the non _ version. Defaults to false. 870 void setUseUnderscoreLongJmp(bool Val) { 871 UseUnderscoreLongJmp = Val; 872 } 873 874 /// Indicate whether the target can generate code for jump tables. 875 void setSupportJumpTables(bool Val) { 876 SupportJumpTables = Val; 877 } 878 879 /// Indicate the number of blocks to generate jump tables rather than if 880 /// sequence. 881 void setMinimumJumpTableEntries(int Val) { 882 MinimumJumpTableEntries = Val; 883 } 884 885 /// If set to a physical register, this specifies the register that 886 /// llvm.savestack/llvm.restorestack should save and restore. 887 void setStackPointerRegisterToSaveRestore(unsigned R) { 888 StackPointerRegisterToSaveRestore = R; 889 } 890 891 /// If set to a physical register, this sets the register that receives the 892 /// exception address on entry to a landing pad. 893 void setExceptionPointerRegister(unsigned R) { 894 ExceptionPointerRegister = R; 895 } 896 897 /// If set to a physical register, this sets the register that receives the 898 /// exception typeid on entry to a landing pad. 899 void setExceptionSelectorRegister(unsigned R) { 900 ExceptionSelectorRegister = R; 901 } 902 903 /// Tells the code generator not to expand operations into sequences that use 904 /// the select operations if possible. 905 void setSelectIsExpensive(bool isExpensive = true) { 906 SelectIsExpensive = isExpensive; 907 } 908 909 /// Tells the code generator not to expand sequence of operations into a 910 /// separate sequences that increases the amount of flow control. 911 void setJumpIsExpensive(bool isExpensive = true) { 912 JumpIsExpensive = isExpensive; 913 } 914 915 /// Tells the code generator that integer divide is expensive, and if 916 /// possible, should be replaced by an alternate sequence of instructions not 917 /// containing an integer divide. 918 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 919 920 /// Tells the code generator which bitwidths to bypass. 921 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { 922 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; 923 } 924 925 /// Tells the code generator that it shouldn't generate srl/add/sra for a 926 /// signed divide by power of two, and let the target handle it. 927 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 928 929 /// Add the specified register class as an available regclass for the 930 /// specified value type. This indicates the selector can handle values of 931 /// that class natively. 932 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { 933 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); 934 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 935 RegClassForVT[VT.SimpleTy] = RC; 936 } 937 938 /// Remove all register classes. 939 void clearRegisterClasses() { 940 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*)); 941 942 AvailableRegClasses.clear(); 943 } 944 945 /// \brief Remove all operation actions. 946 void clearOperationActions() { 947 } 948 949 /// Return the largest legal super-reg register class of the register class 950 /// for the specified type and its associated "cost". 951 virtual std::pair<const TargetRegisterClass*, uint8_t> 952 findRepresentativeClass(MVT VT) const; 953 954 /// Once all of the register classes are added, this allows us to compute 955 /// derived properties we expose. 956 void computeRegisterProperties(); 957 958 /// Indicate that the specified operation does not work with the specified 959 /// type and indicate what to do about it. 960 void setOperationAction(unsigned Op, MVT VT, 961 LegalizeAction Action) { 962 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 963 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 964 } 965 966 /// Indicate that the specified load with extension does not work with the 967 /// specified type and indicate what to do about it. 968 void setLoadExtAction(unsigned ExtType, MVT VT, 969 LegalizeAction Action) { 970 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 971 "Table isn't big enough!"); 972 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 973 } 974 975 /// Indicate that the specified truncating store does not work with the 976 /// specified type and indicate what to do about it. 977 void setTruncStoreAction(MVT ValVT, MVT MemVT, 978 LegalizeAction Action) { 979 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 980 "Table isn't big enough!"); 981 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 982 } 983 984 /// Indicate that the specified indexed load does or does not work with the 985 /// specified type and indicate what to do abort it. 986 /// 987 /// NOTE: All indexed mode loads are initialized to Expand in 988 /// TargetLowering.cpp 989 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 990 LegalizeAction Action) { 991 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 992 (unsigned)Action < 0xf && "Table isn't big enough!"); 993 // Load action are kept in the upper half. 994 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 995 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 996 } 997 998 /// Indicate that the specified indexed store does or does not work with the 999 /// specified type and indicate what to do about it. 1000 /// 1001 /// NOTE: All indexed mode stores are initialized to Expand in 1002 /// TargetLowering.cpp 1003 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1004 LegalizeAction Action) { 1005 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1006 (unsigned)Action < 0xf && "Table isn't big enough!"); 1007 // Store action are kept in the lower half. 1008 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1009 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1010 } 1011 1012 /// Indicate that the specified condition code is or isn't supported on the 1013 /// target and indicate what to do about it. 1014 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1015 LegalizeAction Action) { 1016 assert(VT < MVT::LAST_VALUETYPE && 1017 (unsigned)CC < array_lengthof(CondCodeActions) && 1018 "Table isn't big enough!"); 1019 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 1020 /// value and the upper 27 bits index into the second dimension of the 1021 /// array to select what 64bit value to use. 1022 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1023 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2); 1024 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1025 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2; 1026 } 1027 1028 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults 1029 /// to trying a larger integer/fp until it can find one that works. If that 1030 /// default is insufficient, this method can be used by the target to override 1031 /// the default. 1032 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1033 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1034 } 1035 1036 /// Targets should invoke this method for each target independent node that 1037 /// they want to provide a custom DAG combiner for by implementing the 1038 /// PerformDAGCombine virtual method. 1039 void setTargetDAGCombine(ISD::NodeType NT) { 1040 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1041 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1042 } 1043 1044 /// Set the target's required jmp_buf buffer size (in bytes); default is 200 1045 void setJumpBufSize(unsigned Size) { 1046 JumpBufSize = Size; 1047 } 1048 1049 /// Set the target's required jmp_buf buffer alignment (in bytes); default is 1050 /// 0 1051 void setJumpBufAlignment(unsigned Align) { 1052 JumpBufAlignment = Align; 1053 } 1054 1055 /// Set the target's minimum function alignment (in log2(bytes)) 1056 void setMinFunctionAlignment(unsigned Align) { 1057 MinFunctionAlignment = Align; 1058 } 1059 1060 /// Set the target's preferred function alignment. This should be set if 1061 /// there is a performance benefit to higher-than-minimum alignment (in 1062 /// log2(bytes)) 1063 void setPrefFunctionAlignment(unsigned Align) { 1064 PrefFunctionAlignment = Align; 1065 } 1066 1067 /// Set the target's preferred loop alignment. Default alignment is zero, it 1068 /// means the target does not care about loop alignment. The alignment is 1069 /// specified in log2(bytes). 1070 void setPrefLoopAlignment(unsigned Align) { 1071 PrefLoopAlignment = Align; 1072 } 1073 1074 /// Set the minimum stack alignment of an argument (in log2(bytes)). 1075 void setMinStackArgumentAlignment(unsigned Align) { 1076 MinStackArgumentAlignment = Align; 1077 } 1078 1079 /// Set if the DAG builder should automatically insert fences and reduce the 1080 /// order of atomic memory operations to Monotonic. 1081 void setInsertFencesForAtomic(bool fence) { 1082 InsertFencesForAtomic = fence; 1083 } 1084 1085public: 1086 //===--------------------------------------------------------------------===// 1087 // Addressing mode description hooks (used by LSR etc). 1088 // 1089 1090 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store 1091 /// instructions reading the address. This allows as much computation as 1092 /// possible to be done in the address mode for that operand. This hook lets 1093 /// targets also pass back when this should be done on intrinsics which 1094 /// load/store. 1095 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/, 1096 SmallVectorImpl<Value*> &/*Ops*/, 1097 Type *&/*AccessTy*/) const { 1098 return false; 1099 } 1100 1101 /// This represents an addressing mode of: 1102 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1103 /// If BaseGV is null, there is no BaseGV. 1104 /// If BaseOffs is zero, there is no base offset. 1105 /// If HasBaseReg is false, there is no base register. 1106 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1107 /// no scale. 1108 struct AddrMode { 1109 GlobalValue *BaseGV; 1110 int64_t BaseOffs; 1111 bool HasBaseReg; 1112 int64_t Scale; 1113 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1114 }; 1115 1116 /// Return true if the addressing mode represented by AM is legal for this 1117 /// target, for a load/store of the specified type. 1118 /// 1119 /// The type may be VoidTy, in which case only return true if the addressing 1120 /// mode is legal for a load/store of any legal type. TODO: Handle 1121 /// pre/postinc as well. 1122 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 1123 1124 /// \brief Return the cost of the scaling factor used in the addressing mode 1125 /// represented by AM for this target, for a load/store of the specified type. 1126 /// 1127 /// If the AM is supported, the return value must be >= 0. 1128 /// If the AM is not supported, it returns a negative value. 1129 /// TODO: Handle pre/postinc as well. 1130 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const { 1131 // Default: assume that any scaling factor used in a legal AM is free. 1132 if (isLegalAddressingMode(AM, Ty)) return 0; 1133 return -1; 1134 } 1135 1136 /// Return true if the specified immediate is legal icmp immediate, that is 1137 /// the target has icmp instructions which can compare a register against the 1138 /// immediate without having to materialize the immediate into a register. 1139 virtual bool isLegalICmpImmediate(int64_t) const { 1140 return true; 1141 } 1142 1143 /// Return true if the specified immediate is legal add immediate, that is the 1144 /// target has add instructions which can add a register with the immediate 1145 /// without having to materialize the immediate into a register. 1146 virtual bool isLegalAddImmediate(int64_t) const { 1147 return true; 1148 } 1149 1150 /// Return true if it's free to truncate a value of type Ty1 to type 1151 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 1152 /// by referencing its sub-register AX. 1153 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1154 return false; 1155 } 1156 1157 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding 1158 /// whether a call is in tail position. Typically this means that both results 1159 /// would be assigned to the same register or stack slot, but it could mean 1160 /// the target performs adequate checks of its own before proceeding with the 1161 /// tail call. 1162 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const { 1163 return false; 1164 } 1165 1166 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const { 1167 return false; 1168 } 1169 1170 /// Return true if any actual instruction that defines a value of type Ty1 1171 /// implicitly zero-extends the value to Ty2 in the result register. 1172 /// 1173 /// This does not necessarily include registers defined in unknown ways, such 1174 /// as incoming arguments, or copies from unknown virtual registers. Also, if 1175 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to 1176 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit 1177 /// values implicit zero-extend the result out to 64 bits. 1178 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1179 return false; 1180 } 1181 1182 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const { 1183 return false; 1184 } 1185 1186 /// Return true if the target supplies and combines to a paired load 1187 /// two loaded values of type LoadedType next to each other in memory. 1188 /// RequiredAlignment gives the minimal alignment constraints that must be met to 1189 /// be able to select this paired load. 1190 /// 1191 /// This information is *not* used to generate actual paired loads, but it is used 1192 /// to generate a sequence of loads that is easier to combine into a paired load. 1193 /// For instance, something like this: 1194 /// a = load i64* addr 1195 /// b = trunc i64 a to i32 1196 /// c = lshr i64 a, 32 1197 /// d = trunc i64 c to i32 1198 /// will be optimized into: 1199 /// b = load i32* addr1 1200 /// d = load i32* addr2 1201 /// Where addr1 = addr2 +/- sizeof(i32). 1202 /// 1203 /// In other words, unless the target performs a post-isel load combining, this 1204 /// information should not be provided because it will generate more loads. 1205 virtual bool hasPairedLoad(Type * /*LoadedType*/, 1206 unsigned & /*RequiredAligment*/) const { 1207 return false; 1208 } 1209 1210 virtual bool hasPairedLoad(EVT /*LoadedType*/, 1211 unsigned & /*RequiredAligment*/) const { 1212 return false; 1213 } 1214 1215 /// Return true if zero-extending the specific node Val to type VT2 is free 1216 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or 1217 /// because it's folded such as X86 zero-extending loads). 1218 virtual bool isZExtFree(SDValue Val, EVT VT2) const { 1219 return isZExtFree(Val.getValueType(), VT2); 1220 } 1221 1222 /// Return true if an fneg operation is free to the point where it is never 1223 /// worthwhile to replace it with a bitwise operation. 1224 virtual bool isFNegFree(EVT VT) const { 1225 assert(VT.isFloatingPoint()); 1226 return false; 1227 } 1228 1229 /// Return true if an fabs operation is free to the point where it is never 1230 /// worthwhile to replace it with a bitwise operation. 1231 virtual bool isFAbsFree(EVT VT) const { 1232 assert(VT.isFloatingPoint()); 1233 return false; 1234 } 1235 1236 /// Return true if an FMA operation is faster than a pair of fmul and fadd 1237 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method 1238 /// returns true, otherwise fmuladd is expanded to fmul + fadd. 1239 /// 1240 /// NOTE: This may be called before legalization on types for which FMAs are 1241 /// not legal, but should return true if those types will eventually legalize 1242 /// to types that support FMAs. After legalization, it will only be called on 1243 /// types that support FMAs (via Legal or Custom actions) 1244 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const { 1245 return false; 1246 } 1247 1248 /// Return true if it's profitable to narrow operations of type VT1 to 1249 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from 1250 /// i32 to i16. 1251 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { 1252 return false; 1253 } 1254 1255 //===--------------------------------------------------------------------===// 1256 // Runtime Library hooks 1257 // 1258 1259 /// Rename the default libcall routine name for the specified libcall. 1260 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1261 LibcallRoutineNames[Call] = Name; 1262 } 1263 1264 /// Get the libcall routine name for the specified libcall. 1265 const char *getLibcallName(RTLIB::Libcall Call) const { 1266 return LibcallRoutineNames[Call]; 1267 } 1268 1269 /// Override the default CondCode to be used to test the result of the 1270 /// comparison libcall against zero. 1271 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1272 CmpLibcallCCs[Call] = CC; 1273 } 1274 1275 /// Get the CondCode that's to be used to test the result of the comparison 1276 /// libcall against zero. 1277 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1278 return CmpLibcallCCs[Call]; 1279 } 1280 1281 /// Set the CallingConv that should be used for the specified libcall. 1282 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1283 LibcallCallingConvs[Call] = CC; 1284 } 1285 1286 /// Get the CallingConv that should be used for the specified libcall. 1287 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1288 return LibcallCallingConvs[Call]; 1289 } 1290 1291private: 1292 const TargetMachine &TM; 1293 const DataLayout *TD; 1294 const TargetLoweringObjectFile &TLOF; 1295 1296 /// The type to use for pointers for the default address space, usually i32 or 1297 /// i64. 1298 MVT PointerTy; 1299 1300 /// True if this is a little endian target. 1301 bool IsLittleEndian; 1302 1303 /// Tells the code generator not to expand operations into sequences that use 1304 /// the select operations if possible. 1305 bool SelectIsExpensive; 1306 1307 /// Tells the code generator not to expand integer divides by constants into a 1308 /// sequence of muls, adds, and shifts. This is a hack until a real cost 1309 /// model is in place. If we ever optimize for size, this will be set to true 1310 /// unconditionally. 1311 bool IntDivIsCheap; 1312 1313 /// Tells the code generator to bypass slow divide or remainder 1314 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code 1315 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer 1316 /// div/rem when the operands are positive and less than 256. 1317 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths; 1318 1319 /// Tells the code generator that it shouldn't generate srl/add/sra for a 1320 /// signed divide by power of two, and let the target handle it. 1321 bool Pow2DivIsCheap; 1322 1323 /// Tells the code generator that it shouldn't generate extra flow control 1324 /// instructions and should attempt to combine flow control instructions via 1325 /// predication. 1326 bool JumpIsExpensive; 1327 1328 /// This target prefers to use _setjmp to implement llvm.setjmp. 1329 /// 1330 /// Defaults to false. 1331 bool UseUnderscoreSetJmp; 1332 1333 /// This target prefers to use _longjmp to implement llvm.longjmp. 1334 /// 1335 /// Defaults to false. 1336 bool UseUnderscoreLongJmp; 1337 1338 /// Whether the target can generate code for jumptables. If it's not true, 1339 /// then each jumptable must be lowered into if-then-else's. 1340 bool SupportJumpTables; 1341 1342 /// Number of blocks threshold to use jump tables. 1343 int MinimumJumpTableEntries; 1344 1345 /// Information about the contents of the high-bits in boolean values held in 1346 /// a type wider than i1. See getBooleanContents. 1347 BooleanContent BooleanContents; 1348 1349 /// Information about the contents of the high-bits in boolean vector values 1350 /// when the element type is wider than i1. See getBooleanContents. 1351 BooleanContent BooleanVectorContents; 1352 1353 /// The target scheduling preference: shortest possible total cycles or lowest 1354 /// register usage. 1355 Sched::Preference SchedPreferenceInfo; 1356 1357 /// The size, in bytes, of the target's jmp_buf buffers 1358 unsigned JumpBufSize; 1359 1360 /// The alignment, in bytes, of the target's jmp_buf buffers 1361 unsigned JumpBufAlignment; 1362 1363 /// The minimum alignment that any argument on the stack needs to have. 1364 unsigned MinStackArgumentAlignment; 1365 1366 /// The minimum function alignment (used when optimizing for size, and to 1367 /// prevent explicitly provided alignment from leading to incorrect code). 1368 unsigned MinFunctionAlignment; 1369 1370 /// The preferred function alignment (used when alignment unspecified and 1371 /// optimizing for speed). 1372 unsigned PrefFunctionAlignment; 1373 1374 /// The preferred loop alignment. 1375 unsigned PrefLoopAlignment; 1376 1377 /// Whether the DAG builder should automatically insert fences and reduce 1378 /// ordering for atomics. (This will be set for for most architectures with 1379 /// weak memory ordering.) 1380 bool InsertFencesForAtomic; 1381 1382 /// If set to a physical register, this specifies the register that 1383 /// llvm.savestack/llvm.restorestack should save and restore. 1384 unsigned StackPointerRegisterToSaveRestore; 1385 1386 /// If set to a physical register, this specifies the register that receives 1387 /// the exception address on entry to a landing pad. 1388 unsigned ExceptionPointerRegister; 1389 1390 /// If set to a physical register, this specifies the register that receives 1391 /// the exception typeid on entry to a landing pad. 1392 unsigned ExceptionSelectorRegister; 1393 1394 /// This indicates the default register class to use for each ValueType the 1395 /// target supports natively. 1396 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1397 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1398 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1399 1400 /// This indicates the "representative" register class to use for each 1401 /// ValueType the target supports natively. This information is used by the 1402 /// scheduler to track register pressure. By default, the representative 1403 /// register class is the largest legal super-reg register class of the 1404 /// register class of the specified type. e.g. On x86, i8, i16, and i32's 1405 /// representative class would be GR32. 1406 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1407 1408 /// This indicates the "cost" of the "representative" register class for each 1409 /// ValueType. The cost is used by the scheduler to approximate register 1410 /// pressure. 1411 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1412 1413 /// For any value types we are promoting or expanding, this contains the value 1414 /// type that we are changing to. For Expanded types, this contains one step 1415 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required 1416 /// (e.g. i64 -> i16). For types natively supported by the system, this holds 1417 /// the same type (e.g. i32 -> i32). 1418 MVT TransformToType[MVT::LAST_VALUETYPE]; 1419 1420 /// For each operation and each value type, keep a LegalizeAction that 1421 /// indicates how instruction selection should deal with the operation. Most 1422 /// operations are Legal (aka, supported natively by the target), but 1423 /// operations that are not should be described. Note that operations on 1424 /// non-legal value types are not described here. 1425 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1426 1427 /// For each load extension type and each value type, keep a LegalizeAction 1428 /// that indicates how instruction selection should deal with a load of a 1429 /// specific value type and extension type. 1430 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1431 1432 /// For each value type pair keep a LegalizeAction that indicates whether a 1433 /// truncating store of a specific value type and truncating type is legal. 1434 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1435 1436 /// For each indexed mode and each value type, keep a pair of LegalizeAction 1437 /// that indicates how instruction selection should deal with the load / 1438 /// store. 1439 /// 1440 /// The first dimension is the value_type for the reference. The second 1441 /// dimension represents the various modes for load store. 1442 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1443 1444 /// For each condition code (ISD::CondCode) keep a LegalizeAction that 1445 /// indicates how instruction selection should deal with the condition code. 1446 /// 1447 /// Because each CC action takes up 2 bits, we need to have the array size be 1448 /// large enough to fit all of the value types. This can be done by dividing 1449 /// the MVT::LAST_VALUETYPE by 32 and adding one. 1450 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1]; 1451 1452 ValueTypeActionImpl ValueTypeActions; 1453 1454public: 1455 LegalizeKind 1456 getTypeConversion(LLVMContext &Context, EVT VT) const { 1457 // If this is a simple type, use the ComputeRegisterProp mechanism. 1458 if (VT.isSimple()) { 1459 MVT SVT = VT.getSimpleVT(); 1460 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 1461 MVT NVT = TransformToType[SVT.SimpleTy]; 1462 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 1463 1464 assert( 1465 (LA == TypeLegal || 1466 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) 1467 && "Promote may not follow Expand or Promote"); 1468 1469 if (LA == TypeSplitVector) 1470 return LegalizeKind(LA, EVT::getVectorVT(Context, 1471 SVT.getVectorElementType(), 1472 SVT.getVectorNumElements()/2)); 1473 if (LA == TypeScalarizeVector) 1474 return LegalizeKind(LA, SVT.getVectorElementType()); 1475 return LegalizeKind(LA, NVT); 1476 } 1477 1478 // Handle Extended Scalar Types. 1479 if (!VT.isVector()) { 1480 assert(VT.isInteger() && "Float types must be simple"); 1481 unsigned BitSize = VT.getSizeInBits(); 1482 // First promote to a power-of-two size, then expand if necessary. 1483 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1484 EVT NVT = VT.getRoundIntegerType(Context); 1485 assert(NVT != VT && "Unable to round integer VT"); 1486 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1487 // Avoid multi-step promotion. 1488 if (NextStep.first == TypePromoteInteger) return NextStep; 1489 // Return rounded integer type. 1490 return LegalizeKind(TypePromoteInteger, NVT); 1491 } 1492 1493 return LegalizeKind(TypeExpandInteger, 1494 EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); 1495 } 1496 1497 // Handle vector types. 1498 unsigned NumElts = VT.getVectorNumElements(); 1499 EVT EltVT = VT.getVectorElementType(); 1500 1501 // Vectors with only one element are always scalarized. 1502 if (NumElts == 1) 1503 return LegalizeKind(TypeScalarizeVector, EltVT); 1504 1505 // Try to widen vector elements until the element type is a power of two and 1506 // promote it to a legal type later on, for example: 1507 // <3 x i8> -> <4 x i8> -> <4 x i32> 1508 if (EltVT.isInteger()) { 1509 // Vectors with a number of elements that is not a power of two are always 1510 // widened, for example <3 x i8> -> <4 x i8>. 1511 if (!VT.isPow2VectorType()) { 1512 NumElts = (unsigned)NextPowerOf2(NumElts); 1513 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1514 return LegalizeKind(TypeWidenVector, NVT); 1515 } 1516 1517 // Examine the element type. 1518 LegalizeKind LK = getTypeConversion(Context, EltVT); 1519 1520 // If type is to be expanded, split the vector. 1521 // <4 x i140> -> <2 x i140> 1522 if (LK.first == TypeExpandInteger) 1523 return LegalizeKind(TypeSplitVector, 1524 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1525 1526 // Promote the integer element types until a legal vector type is found 1527 // or until the element integer type is too big. If a legal type was not 1528 // found, fallback to the usual mechanism of widening/splitting the 1529 // vector. 1530 EVT OldEltVT = EltVT; 1531 while (1) { 1532 // Increase the bitwidth of the element to the next pow-of-two 1533 // (which is greater than 8 bits). 1534 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() 1535 ).getRoundIntegerType(Context); 1536 1537 // Stop trying when getting a non-simple element type. 1538 // Note that vector elements may be greater than legal vector element 1539 // types. Example: X86 XMM registers hold 64bit element on 32bit systems. 1540 if (!EltVT.isSimple()) break; 1541 1542 // Build a new vector type and check if it is legal. 1543 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1544 // Found a legal promoted vector type. 1545 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1546 return LegalizeKind(TypePromoteInteger, 1547 EVT::getVectorVT(Context, EltVT, NumElts)); 1548 } 1549 1550 // Reset the type to the unexpanded type if we did not find a legal vector 1551 // type with a promoted vector element type. 1552 EltVT = OldEltVT; 1553 } 1554 1555 // Try to widen the vector until a legal type is found. 1556 // If there is no wider legal type, split the vector. 1557 while (1) { 1558 // Round up to the next power of 2. 1559 NumElts = (unsigned)NextPowerOf2(NumElts); 1560 1561 // If there is no simple vector type with this many elements then there 1562 // cannot be a larger legal vector type. Note that this assumes that 1563 // there are no skipped intermediate vector types in the simple types. 1564 if (!EltVT.isSimple()) break; 1565 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1566 if (LargerVector == MVT()) break; 1567 1568 // If this type is legal then widen the vector. 1569 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1570 return LegalizeKind(TypeWidenVector, LargerVector); 1571 } 1572 1573 // Widen odd vectors to next power of two. 1574 if (!VT.isPow2VectorType()) { 1575 EVT NVT = VT.getPow2VectorType(Context); 1576 return LegalizeKind(TypeWidenVector, NVT); 1577 } 1578 1579 // Vectors with illegal element types are expanded. 1580 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1581 return LegalizeKind(TypeSplitVector, NVT); 1582 } 1583 1584private: 1585 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses; 1586 1587 /// Targets can specify ISD nodes that they would like PerformDAGCombine 1588 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this 1589 /// array. 1590 unsigned char 1591 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1592 1593 /// For operations that must be promoted to a specific type, this holds the 1594 /// destination type. This map should be sparse, so don't hold it as an 1595 /// array. 1596 /// 1597 /// Targets add entries to this map with AddPromotedToType(..), clients access 1598 /// this with getTypeToPromoteTo(..). 1599 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1600 PromoteToType; 1601 1602 /// Stores the name each libcall. 1603 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1604 1605 /// The ISD::CondCode that should be used to test the result of each of the 1606 /// comparison libcall against zero. 1607 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1608 1609 /// Stores the CallingConv that should be used for each libcall. 1610 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1611 1612protected: 1613 /// \brief Specify maximum number of store instructions per memset call. 1614 /// 1615 /// When lowering \@llvm.memset this field specifies the maximum number of 1616 /// store operations that may be substituted for the call to memset. Targets 1617 /// must set this value based on the cost threshold for that target. Targets 1618 /// should assume that the memset will be done using as many of the largest 1619 /// store operations first, followed by smaller ones, if necessary, per 1620 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1621 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1622 /// store. This only applies to setting a constant array of a constant size. 1623 unsigned MaxStoresPerMemset; 1624 1625 /// Maximum number of stores operations that may be substituted for the call 1626 /// to memset, used for functions with OptSize attribute. 1627 unsigned MaxStoresPerMemsetOptSize; 1628 1629 /// \brief Specify maximum bytes of store instructions per memcpy call. 1630 /// 1631 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1632 /// store operations that may be substituted for a call to memcpy. Targets 1633 /// must set this value based on the cost threshold for that target. Targets 1634 /// should assume that the memcpy will be done using as many of the largest 1635 /// store operations first, followed by smaller ones, if necessary, per 1636 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1637 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1638 /// and one 1-byte store. This only applies to copying a constant array of 1639 /// constant size. 1640 unsigned MaxStoresPerMemcpy; 1641 1642 /// Maximum number of store operations that may be substituted for a call to 1643 /// memcpy, used for functions with OptSize attribute. 1644 unsigned MaxStoresPerMemcpyOptSize; 1645 1646 /// \brief Specify maximum bytes of store instructions per memmove call. 1647 /// 1648 /// When lowering \@llvm.memmove this field specifies the maximum number of 1649 /// store instructions that may be substituted for a call to memmove. Targets 1650 /// must set this value based on the cost threshold for that target. Targets 1651 /// should assume that the memmove will be done using as many of the largest 1652 /// store operations first, followed by smaller ones, if necessary, per 1653 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1654 /// with 8-bit alignment would result in nine 1-byte stores. This only 1655 /// applies to copying a constant array of constant size. 1656 unsigned MaxStoresPerMemmove; 1657 1658 /// Maximum number of store instructions that may be substituted for a call to 1659 /// memmove, used for functions with OpSize attribute. 1660 unsigned MaxStoresPerMemmoveOptSize; 1661 1662 /// Tells the code generator that select is more expensive than a branch if 1663 /// the branch is usually predicted right. 1664 bool PredictableSelectIsExpensive; 1665 1666protected: 1667 /// Return true if the value types that can be represented by the specified 1668 /// register class are all legal. 1669 bool isLegalRC(const TargetRegisterClass *RC) const; 1670}; 1671 1672/// This class defines information used to lower LLVM code to legal SelectionDAG 1673/// operators that the target instruction selector can accept natively. 1674/// 1675/// This class also defines callbacks that targets must implement to lower 1676/// target-specific constructs to SelectionDAG operators. 1677class TargetLowering : public TargetLoweringBase { 1678 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION; 1679 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION; 1680 1681public: 1682 /// NOTE: The constructor takes ownership of TLOF. 1683 explicit TargetLowering(const TargetMachine &TM, 1684 const TargetLoweringObjectFile *TLOF); 1685 1686 /// Returns true by value, base pointer and offset pointer and addressing mode 1687 /// by reference if the node's address can be legally represented as 1688 /// pre-indexed load / store address. 1689 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, 1690 SDValue &/*Offset*/, 1691 ISD::MemIndexedMode &/*AM*/, 1692 SelectionDAG &/*DAG*/) const { 1693 return false; 1694 } 1695 1696 /// Returns true by value, base pointer and offset pointer and addressing mode 1697 /// by reference if this node can be combined with a load / store to form a 1698 /// post-indexed load / store. 1699 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, 1700 SDValue &/*Base*/, SDValue &/*Offset*/, 1701 ISD::MemIndexedMode &/*AM*/, 1702 SelectionDAG &/*DAG*/) const { 1703 return false; 1704 } 1705 1706 /// Return the entry encoding for a jump table in the current function. The 1707 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum. 1708 virtual unsigned getJumpTableEncoding() const; 1709 1710 virtual const MCExpr * 1711 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/, 1712 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/, 1713 MCContext &/*Ctx*/) const { 1714 llvm_unreachable("Need to implement this hook if target has custom JTIs"); 1715 } 1716 1717 /// Returns relocation base for the given PIC jumptable. 1718 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 1719 SelectionDAG &DAG) const; 1720 1721 /// This returns the relocation base for the given PIC jumptable, the same as 1722 /// getPICJumpTableRelocBase, but as an MCExpr. 1723 virtual const MCExpr * 1724 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1725 unsigned JTI, MCContext &Ctx) const; 1726 1727 /// Return true if folding a constant offset with the given GlobalAddress is 1728 /// legal. It is frequently not legal in PIC relocation models. 1729 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 1730 1731 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 1732 SDValue &Chain) const; 1733 1734 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, 1735 SDValue &NewLHS, SDValue &NewRHS, 1736 ISD::CondCode &CCCode, SDLoc DL) const; 1737 1738 /// Returns a pair of (return value, chain). 1739 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, 1740 EVT RetVT, const SDValue *Ops, 1741 unsigned NumOps, bool isSigned, 1742 SDLoc dl, bool doesNotReturn = false, 1743 bool isReturnValueUsed = true) const; 1744 1745 //===--------------------------------------------------------------------===// 1746 // TargetLowering Optimization Methods 1747 // 1748 1749 /// A convenience struct that encapsulates a DAG, and two SDValues for 1750 /// returning information from TargetLowering to its clients that want to 1751 /// combine. 1752 struct TargetLoweringOpt { 1753 SelectionDAG &DAG; 1754 bool LegalTys; 1755 bool LegalOps; 1756 SDValue Old; 1757 SDValue New; 1758 1759 explicit TargetLoweringOpt(SelectionDAG &InDAG, 1760 bool LT, bool LO) : 1761 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 1762 1763 bool LegalTypes() const { return LegalTys; } 1764 bool LegalOperations() const { return LegalOps; } 1765 1766 bool CombineTo(SDValue O, SDValue N) { 1767 Old = O; 1768 New = N; 1769 return true; 1770 } 1771 1772 /// Check to see if the specified operand of the specified instruction is a 1773 /// constant integer. If so, check to see if there are any bits set in the 1774 /// constant that are not demanded. If so, shrink the constant and return 1775 /// true. 1776 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 1777 1778 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This 1779 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be 1780 /// generalized for targets with other types of implicit widening casts. 1781 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 1782 SDLoc dl); 1783 }; 1784 1785 /// Look at Op. At this point, we know that only the DemandedMask bits of the 1786 /// result of Op are ever used downstream. If we can use this information to 1787 /// simplify Op, create a new simplified DAG node and return true, returning 1788 /// the original and new nodes in Old and New. Otherwise, analyze the 1789 /// expression and return a mask of KnownOne and KnownZero bits for the 1790 /// expression (used to simplify the caller). The KnownZero/One bits may only 1791 /// be accurate for those bits in the DemandedMask. 1792 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 1793 APInt &KnownZero, APInt &KnownOne, 1794 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 1795 1796 /// Determine which of the bits specified in Mask are known to be either zero 1797 /// or one and return them in the KnownZero/KnownOne bitsets. 1798 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 1799 APInt &KnownZero, 1800 APInt &KnownOne, 1801 const SelectionDAG &DAG, 1802 unsigned Depth = 0) const; 1803 1804 /// This method can be implemented by targets that want to expose additional 1805 /// information about sign bits to the DAG Combiner. 1806 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 1807 unsigned Depth = 0) const; 1808 1809 struct DAGCombinerInfo { 1810 void *DC; // The DAG Combiner object. 1811 CombineLevel Level; 1812 bool CalledByLegalizer; 1813 public: 1814 SelectionDAG &DAG; 1815 1816 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc) 1817 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {} 1818 1819 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } 1820 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } 1821 bool isAfterLegalizeVectorOps() const { 1822 return Level == AfterLegalizeDAG; 1823 } 1824 CombineLevel getDAGCombineLevel() { return Level; } 1825 bool isCalledByLegalizer() const { return CalledByLegalizer; } 1826 1827 void AddToWorklist(SDNode *N); 1828 void RemoveFromWorklist(SDNode *N); 1829 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 1830 bool AddTo = true); 1831 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 1832 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 1833 1834 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 1835 }; 1836 1837 /// Try to simplify a setcc built with the specified operands and cc. If it is 1838 /// unable to simplify it, return a null SDValue. 1839 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1840 ISD::CondCode Cond, bool foldBooleans, 1841 DAGCombinerInfo &DCI, SDLoc dl) const; 1842 1843 /// Returns true (and the GlobalValue and the offset) if the node is a 1844 /// GlobalAddress + offset. 1845 virtual bool 1846 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 1847 1848 /// This method will be invoked for all target nodes and for any 1849 /// target-independent nodes that the target has registered with invoke it 1850 /// for. 1851 /// 1852 /// The semantics are as follows: 1853 /// Return Value: 1854 /// SDValue.Val == 0 - No change was made 1855 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 1856 /// otherwise - N should be replaced by the returned Operand. 1857 /// 1858 /// In addition, methods provided by DAGCombinerInfo may be used to perform 1859 /// more complex transformations. 1860 /// 1861 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 1862 1863 /// Return true if the target has native support for the specified value type 1864 /// and it is 'desirable' to use the type for the given node type. e.g. On x86 1865 /// i16 is legal, but undesirable since i16 instruction encodings are longer 1866 /// and some i16 instructions are slow. 1867 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { 1868 // By default, assume all legal types are desirable. 1869 return isTypeLegal(VT); 1870 } 1871 1872 /// Return true if it is profitable for dag combiner to transform a floating 1873 /// point op of specified opcode to a equivalent op of an integer 1874 /// type. e.g. f32 load -> i32 load can be profitable on ARM. 1875 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, 1876 EVT /*VT*/) const { 1877 return false; 1878 } 1879 1880 /// This method query the target whether it is beneficial for dag combiner to 1881 /// promote the specified node. If true, it should return the desired 1882 /// promotion type by reference. 1883 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { 1884 return false; 1885 } 1886 1887 //===--------------------------------------------------------------------===// 1888 // Lowering methods - These methods must be implemented by targets so that 1889 // the SelectionDAGBuilder code knows how to lower these. 1890 // 1891 1892 /// This hook must be implemented to lower the incoming (formal) arguments, 1893 /// described by the Ins array, into the specified DAG. The implementation 1894 /// should fill in the InVals array with legal-type argument values, and 1895 /// return the resulting token chain value. 1896 /// 1897 virtual SDValue 1898 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1899 bool /*isVarArg*/, 1900 const SmallVectorImpl<ISD::InputArg> &/*Ins*/, 1901 SDLoc /*dl*/, SelectionDAG &/*DAG*/, 1902 SmallVectorImpl<SDValue> &/*InVals*/) const { 1903 llvm_unreachable("Not Implemented"); 1904 } 1905 1906 struct ArgListEntry { 1907 SDValue Node; 1908 Type* Ty; 1909 bool isSExt : 1; 1910 bool isZExt : 1; 1911 bool isInReg : 1; 1912 bool isSRet : 1; 1913 bool isNest : 1; 1914 bool isByVal : 1; 1915 bool isReturned : 1; 1916 uint16_t Alignment; 1917 1918 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1919 isSRet(false), isNest(false), isByVal(false), isReturned(false), 1920 Alignment(0) { } 1921 }; 1922 typedef std::vector<ArgListEntry> ArgListTy; 1923 1924 /// This structure contains all information that is necessary for lowering 1925 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder 1926 /// needs to lower a call, and targets will see this struct in their LowerCall 1927 /// implementation. 1928 struct CallLoweringInfo { 1929 SDValue Chain; 1930 Type *RetTy; 1931 bool RetSExt : 1; 1932 bool RetZExt : 1; 1933 bool IsVarArg : 1; 1934 bool IsInReg : 1; 1935 bool DoesNotReturn : 1; 1936 bool IsReturnValueUsed : 1; 1937 1938 // IsTailCall should be modified by implementations of 1939 // TargetLowering::LowerCall that perform tail call conversions. 1940 bool IsTailCall; 1941 1942 unsigned NumFixedArgs; 1943 CallingConv::ID CallConv; 1944 SDValue Callee; 1945 ArgListTy &Args; 1946 SelectionDAG &DAG; 1947 SDLoc DL; 1948 ImmutableCallSite *CS; 1949 SmallVector<ISD::OutputArg, 32> Outs; 1950 SmallVector<SDValue, 32> OutVals; 1951 SmallVector<ISD::InputArg, 32> Ins; 1952 1953 1954 /// Constructs a call lowering context based on the ImmutableCallSite \p cs. 1955 CallLoweringInfo(SDValue chain, Type *retTy, 1956 FunctionType *FTy, bool isTailCall, SDValue callee, 1957 ArgListTy &args, SelectionDAG &dag, SDLoc dl, 1958 ImmutableCallSite &cs) 1959 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)), 1960 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()), 1961 IsInReg(cs.paramHasAttr(0, Attribute::InReg)), 1962 DoesNotReturn(cs.doesNotReturn()), 1963 IsReturnValueUsed(!cs.getInstruction()->use_empty()), 1964 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()), 1965 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag), 1966 DL(dl), CS(&cs) {} 1967 1968 /// Constructs a call lowering context based on the provided call 1969 /// information. 1970 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt, 1971 bool isVarArg, bool isInReg, unsigned numFixedArgs, 1972 CallingConv::ID callConv, bool isTailCall, 1973 bool doesNotReturn, bool isReturnValueUsed, SDValue callee, 1974 ArgListTy &args, SelectionDAG &dag, SDLoc dl) 1975 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt), 1976 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn), 1977 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall), 1978 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee), 1979 Args(args), DAG(dag), DL(dl), CS(NULL) {} 1980 }; 1981 1982 /// This function lowers an abstract call to a function into an actual call. 1983 /// This returns a pair of operands. The first element is the return value 1984 /// for the function (if RetTy is not VoidTy). The second element is the 1985 /// outgoing token chain. It calls LowerCall to do the actual lowering. 1986 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const; 1987 1988 /// This hook must be implemented to lower calls into the the specified 1989 /// DAG. The outgoing arguments to the call are described by the Outs array, 1990 /// and the values to be returned by the call are described by the Ins 1991 /// array. The implementation should fill in the InVals array with legal-type 1992 /// return values from the call, and return the resulting token chain value. 1993 virtual SDValue 1994 LowerCall(CallLoweringInfo &/*CLI*/, 1995 SmallVectorImpl<SDValue> &/*InVals*/) const { 1996 llvm_unreachable("Not Implemented"); 1997 } 1998 1999 /// Target-specific cleanup for formal ByVal parameters. 2000 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {} 2001 2002 /// This hook should be implemented to check whether the return values 2003 /// described by the Outs array can fit into the return registers. If false 2004 /// is returned, an sret-demotion is performed. 2005 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, 2006 MachineFunction &/*MF*/, bool /*isVarArg*/, 2007 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 2008 LLVMContext &/*Context*/) const 2009 { 2010 // Return true by default to get preexisting behavior. 2011 return true; 2012 } 2013 2014 /// This hook must be implemented to lower outgoing return values, described 2015 /// by the Outs array, into the specified DAG. The implementation should 2016 /// return the resulting token chain value. 2017 virtual SDValue 2018 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 2019 bool /*isVarArg*/, 2020 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 2021 const SmallVectorImpl<SDValue> &/*OutVals*/, 2022 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const { 2023 llvm_unreachable("Not Implemented"); 2024 } 2025 2026 /// Return true if result of the specified node is used by a return node 2027 /// only. It also compute and return the input chain for the tail call. 2028 /// 2029 /// This is used to determine whether it is possible to codegen a libcall as 2030 /// tail call at legalization time. 2031 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const { 2032 return false; 2033 } 2034 2035 /// Return true if the target may be able emit the call instruction as a tail 2036 /// call. This is used by optimization passes to determine if it's profitable 2037 /// to duplicate return instructions to enable tailcall optimization. 2038 virtual bool mayBeEmittedAsTailCall(CallInst *) const { 2039 return false; 2040 } 2041 2042 /// Return the type that should be used to zero or sign extend a 2043 /// zeroext/signext integer argument or return value. FIXME: Most C calling 2044 /// convention requires the return type to be promoted, but this is not true 2045 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C 2046 /// calling conventions. The frontend should handle this and include all of 2047 /// the necessary information. 2048 virtual MVT getTypeForExtArgOrReturn(MVT VT, 2049 ISD::NodeType /*ExtendKind*/) const { 2050 MVT MinVT = getRegisterType(MVT::i32); 2051 return VT.bitsLT(MinVT) ? MinVT : VT; 2052 } 2053 2054 /// This callback is invoked by the type legalizer to legalize nodes with an 2055 /// illegal operand type but legal result types. It replaces the 2056 /// LowerOperation callback in the type Legalizer. The reason we can not do 2057 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to 2058 /// use this callback. 2059 /// 2060 /// TODO: Consider merging with ReplaceNodeResults. 2061 /// 2062 /// The target places new result values for the node in Results (their number 2063 /// and types must exactly match those of the original return values of 2064 /// the node), or leaves Results empty, which indicates that the node is not 2065 /// to be custom lowered after all. 2066 /// The default implementation calls LowerOperation. 2067 virtual void LowerOperationWrapper(SDNode *N, 2068 SmallVectorImpl<SDValue> &Results, 2069 SelectionDAG &DAG) const; 2070 2071 /// This callback is invoked for operations that are unsupported by the 2072 /// target, which are registered to use 'custom' lowering, and whose defined 2073 /// values are all legal. If the target has no operations that require custom 2074 /// lowering, it need not implement this. The default implementation of this 2075 /// aborts. 2076 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 2077 2078 /// This callback is invoked when a node result type is illegal for the 2079 /// target, and the operation was registered to use 'custom' lowering for that 2080 /// result type. The target places new result values for the node in Results 2081 /// (their number and types must exactly match those of the original return 2082 /// values of the node), or leaves Results empty, which indicates that the 2083 /// node is not to be custom lowered after all. 2084 /// 2085 /// If the target has no operations that require custom lowering, it need not 2086 /// implement this. The default implementation aborts. 2087 virtual void ReplaceNodeResults(SDNode * /*N*/, 2088 SmallVectorImpl<SDValue> &/*Results*/, 2089 SelectionDAG &/*DAG*/) const { 2090 llvm_unreachable("ReplaceNodeResults not implemented for this target!"); 2091 } 2092 2093 /// This method returns the name of a target specific DAG node. 2094 virtual const char *getTargetNodeName(unsigned Opcode) const; 2095 2096 /// This method returns a target specific FastISel object, or null if the 2097 /// target does not support "fast" ISel. 2098 virtual FastISel *createFastISel(FunctionLoweringInfo &, 2099 const TargetLibraryInfo *) const { 2100 return 0; 2101 } 2102 2103 //===--------------------------------------------------------------------===// 2104 // Inline Asm Support hooks 2105 // 2106 2107 /// This hook allows the target to expand an inline asm call to be explicit 2108 /// llvm code if it wants to. This is useful for turning simple inline asms 2109 /// into LLVM intrinsics, which gives the compiler more information about the 2110 /// behavior of the code. 2111 virtual bool ExpandInlineAsm(CallInst *) const { 2112 return false; 2113 } 2114 2115 enum ConstraintType { 2116 C_Register, // Constraint represents specific register(s). 2117 C_RegisterClass, // Constraint represents any of register(s) in class. 2118 C_Memory, // Memory constraint. 2119 C_Other, // Something else. 2120 C_Unknown // Unsupported constraint. 2121 }; 2122 2123 enum ConstraintWeight { 2124 // Generic weights. 2125 CW_Invalid = -1, // No match. 2126 CW_Okay = 0, // Acceptable. 2127 CW_Good = 1, // Good weight. 2128 CW_Better = 2, // Better weight. 2129 CW_Best = 3, // Best weight. 2130 2131 // Well-known weights. 2132 CW_SpecificReg = CW_Okay, // Specific register operands. 2133 CW_Register = CW_Good, // Register operands. 2134 CW_Memory = CW_Better, // Memory operands. 2135 CW_Constant = CW_Best, // Constant operand. 2136 CW_Default = CW_Okay // Default or don't know type. 2137 }; 2138 2139 /// This contains information for each constraint that we are lowering. 2140 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 2141 /// This contains the actual string for the code, like "m". TargetLowering 2142 /// picks the 'best' code from ConstraintInfo::Codes that most closely 2143 /// matches the operand. 2144 std::string ConstraintCode; 2145 2146 /// Information about the constraint code, e.g. Register, RegisterClass, 2147 /// Memory, Other, Unknown. 2148 TargetLowering::ConstraintType ConstraintType; 2149 2150 /// If this is the result output operand or a clobber, this is null, 2151 /// otherwise it is the incoming operand to the CallInst. This gets 2152 /// modified as the asm is processed. 2153 Value *CallOperandVal; 2154 2155 /// The ValueType for the operand value. 2156 MVT ConstraintVT; 2157 2158 /// Return true of this is an input operand that is a matching constraint 2159 /// like "4". 2160 bool isMatchingInputConstraint() const; 2161 2162 /// If this is an input matching constraint, this method returns the output 2163 /// operand it matches. 2164 unsigned getMatchedOperand() const; 2165 2166 /// Copy constructor for copying from an AsmOperandInfo. 2167 AsmOperandInfo(const AsmOperandInfo &info) 2168 : InlineAsm::ConstraintInfo(info), 2169 ConstraintCode(info.ConstraintCode), 2170 ConstraintType(info.ConstraintType), 2171 CallOperandVal(info.CallOperandVal), 2172 ConstraintVT(info.ConstraintVT) { 2173 } 2174 2175 /// Copy constructor for copying from a ConstraintInfo. 2176 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 2177 : InlineAsm::ConstraintInfo(info), 2178 ConstraintType(TargetLowering::C_Unknown), 2179 CallOperandVal(0), ConstraintVT(MVT::Other) { 2180 } 2181 }; 2182 2183 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; 2184 2185 /// Split up the constraint string from the inline assembly value into the 2186 /// specific constraints and their prefixes, and also tie in the associated 2187 /// operand values. If this returns an empty vector, and if the constraint 2188 /// string itself isn't empty, there was an error parsing. 2189 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; 2190 2191 /// Examine constraint type and operand type and determine a weight value. 2192 /// The operand object must already have been set up with the operand type. 2193 virtual ConstraintWeight getMultipleConstraintMatchWeight( 2194 AsmOperandInfo &info, int maIndex) const; 2195 2196 /// Examine constraint string and operand type and determine a weight value. 2197 /// The operand object must already have been set up with the operand type. 2198 virtual ConstraintWeight getSingleConstraintMatchWeight( 2199 AsmOperandInfo &info, const char *constraint) const; 2200 2201 /// Determines the constraint code and constraint type to use for the specific 2202 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. 2203 /// If the actual operand being passed in is available, it can be passed in as 2204 /// Op, otherwise an empty SDValue can be passed. 2205 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2206 SDValue Op, 2207 SelectionDAG *DAG = 0) const; 2208 2209 /// Given a constraint, return the type of constraint it is for this target. 2210 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 2211 2212 /// Given a physical register constraint (e.g. {edx}), return the register 2213 /// number and the register class for the register. 2214 /// 2215 /// Given a register class constraint, like 'r', if this corresponds directly 2216 /// to an LLVM register class, return a register of 0 and the register class 2217 /// pointer. 2218 /// 2219 /// This should only be used for C_Register constraints. On error, this 2220 /// returns a register number of 0 and a null register class pointer.. 2221 virtual std::pair<unsigned, const TargetRegisterClass*> 2222 getRegForInlineAsmConstraint(const std::string &Constraint, 2223 MVT VT) const; 2224 2225 /// Try to replace an X constraint, which matches anything, with another that 2226 /// has more specific requirements based on the type of the corresponding 2227 /// operand. This returns null if there is no replacement to make. 2228 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 2229 2230 /// Lower the specified operand into the Ops vector. If it is invalid, don't 2231 /// add anything to Ops. 2232 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 2233 std::vector<SDValue> &Ops, 2234 SelectionDAG &DAG) const; 2235 2236 //===--------------------------------------------------------------------===// 2237 // Div utility functions 2238 // 2239 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, 2240 SelectionDAG &DAG) const; 2241 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2242 std::vector<SDNode*> *Created) const; 2243 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2244 std::vector<SDNode*> *Created) const; 2245 2246 //===--------------------------------------------------------------------===// 2247 // Instruction Emitting Hooks 2248 // 2249 2250 // This method should be implemented by targets that mark instructions with 2251 // the 'usesCustomInserter' flag. These instructions are special in various 2252 // ways, which require special support to insert. The specified MachineInstr 2253 // is created but not inserted into any basic blocks, and this method is 2254 // called to expand it into a sequence of instructions, potentially also 2255 // creating new basic blocks and control flow. 2256 virtual MachineBasicBlock * 2257 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 2258 2259 /// This method should be implemented by targets that mark instructions with 2260 /// the 'hasPostISelHook' flag. These instructions must be adjusted after 2261 /// instruction selection by target hooks. e.g. To fill in optional defs for 2262 /// ARM 's' setting instructions. 2263 virtual void 2264 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 2265}; 2266 2267/// Given an LLVM IR type and return type attributes, compute the return value 2268/// EVTs and flags, and optionally also the offsets, if the return value is 2269/// being lowered to memory. 2270void GetReturnInfo(Type* ReturnType, AttributeSet attr, 2271 SmallVectorImpl<ISD::OutputArg> &Outs, 2272 const TargetLowering &TLI); 2273 2274} // end llvm namespace 2275 2276#endif 2277