TargetLowering.h revision d4f5a615674aaabeee4e444e708d1fa00a41495e
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// 10/// \file 11/// This file describes how to lower LLVM code to machine code. This has two 12/// main components: 13/// 14/// 1. Which ValueTypes are natively supported by the target. 15/// 2. Which operations are supported for supported ValueTypes. 16/// 3. Cost thresholds for alternative implementations of certain operations. 17/// 18/// In addition it has a few other components, like information about FP 19/// immediates. 20/// 21//===----------------------------------------------------------------------===// 22 23#ifndef LLVM_TARGET_TARGETLOWERING_H 24#define LLVM_TARGET_TARGETLOWERING_H 25 26#include "llvm/ADT/DenseMap.h" 27#include "llvm/CodeGen/DAGCombine.h" 28#include "llvm/CodeGen/RuntimeLibcalls.h" 29#include "llvm/CodeGen/SelectionDAGNodes.h" 30#include "llvm/IR/Attributes.h" 31#include "llvm/IR/CallingConv.h" 32#include "llvm/IR/InlineAsm.h" 33#include "llvm/Support/CallSite.h" 34#include "llvm/Target/TargetCallingConv.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class CallInst; 42 class CCState; 43 class FastISel; 44 class FunctionLoweringInfo; 45 class ImmutableCallSite; 46 class IntrinsicInst; 47 class MachineBasicBlock; 48 class MachineFunction; 49 class MachineInstr; 50 class MachineJumpTableInfo; 51 class MCContext; 52 class MCExpr; 53 template<typename T> class SmallVectorImpl; 54 class DataLayout; 55 class TargetRegisterClass; 56 class TargetLibraryInfo; 57 class TargetLoweringObjectFile; 58 class Value; 59 60 namespace Sched { 61 enum Preference { 62 None, // No preference 63 Source, // Follow source order. 64 RegPressure, // Scheduling for lowest register pressure. 65 Hybrid, // Scheduling for both latency and register pressure. 66 ILP, // Scheduling for ILP in low register pressure mode. 67 VLIW // Scheduling for VLIW targets. 68 }; 69 } 70 71/// This base class for TargetLowering contains the SelectionDAG-independent 72/// parts that can be used from the rest of CodeGen. 73class TargetLoweringBase { 74 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 75 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION; 76 77public: 78 /// This enum indicates whether operations are valid for a target, and if not, 79 /// what action should be used to make them valid. 80 enum LegalizeAction { 81 Legal, // The target natively supports this operation. 82 Promote, // This operation should be executed in a larger type. 83 Expand, // Try to expand this to other ops, otherwise use a libcall. 84 Custom // Use the LowerOperation hook to implement custom lowering. 85 }; 86 87 /// This enum indicates whether a types are legal for a target, and if not, 88 /// what action should be used to make them valid. 89 enum LegalizeTypeAction { 90 TypeLegal, // The target natively supports this type. 91 TypePromoteInteger, // Replace this integer with a larger one. 92 TypeExpandInteger, // Split this integer into two of half the size. 93 TypeSoftenFloat, // Convert this float to a same size integer type. 94 TypeExpandFloat, // Split this float into two of half the size. 95 TypeScalarizeVector, // Replace this one-element vector with its element. 96 TypeSplitVector, // Split this vector into two of half the size. 97 TypeWidenVector // This vector should be widened into a larger vector. 98 }; 99 100 /// LegalizeKind holds the legalization kind that needs to happen to EVT 101 /// in order to type-legalize it. 102 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; 103 104 /// Enum that describes how the target represents true/false values. 105 enum BooleanContent { 106 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 107 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 108 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 109 }; 110 111 /// Enum that describes what type of support for selects the target has. 112 enum SelectSupportKind { 113 ScalarValSelect, // The target supports scalar selects (ex: cmov). 114 ScalarCondVectorVal, // The target supports selects with a scalar condition 115 // and vector values (ex: cmov). 116 VectorMaskSelect // The target supports vector selects with a vector 117 // mask (ex: x86 blends). 118 }; 119 120 static ISD::NodeType getExtendForContent(BooleanContent Content) { 121 switch (Content) { 122 case UndefinedBooleanContent: 123 // Extend by adding rubbish bits. 124 return ISD::ANY_EXTEND; 125 case ZeroOrOneBooleanContent: 126 // Extend by adding zero bits. 127 return ISD::ZERO_EXTEND; 128 case ZeroOrNegativeOneBooleanContent: 129 // Extend by copying the sign bit. 130 return ISD::SIGN_EXTEND; 131 } 132 llvm_unreachable("Invalid content kind"); 133 } 134 135 /// NOTE: The constructor takes ownership of TLOF. 136 explicit TargetLoweringBase(const TargetMachine &TM, 137 const TargetLoweringObjectFile *TLOF); 138 virtual ~TargetLoweringBase(); 139 140protected: 141 /// \brief Initialize all of the actions to default values. 142 void initActions(); 143 144public: 145 const TargetMachine &getTargetMachine() const { return TM; } 146 const DataLayout *getDataLayout() const { return TD; } 147 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 148 149 bool isBigEndian() const { return !IsLittleEndian; } 150 bool isLittleEndian() const { return IsLittleEndian; } 151 152 /// Return the pointer type for the given address space, defaults to 153 /// the pointer type from the data layout. 154 /// FIXME: The default needs to be removed once all the code is updated. 155 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const; 156 unsigned getPointerSizeInBits(uint32_t AS = 0) const; 157 unsigned getPointerTypeSizeInBits(Type *Ty) const; 158 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const; 159 160 EVT getShiftAmountTy(EVT LHSTy) const; 161 162 /// Returns the type to be used for the index operand of: 163 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, 164 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR 165 virtual MVT getVectorIdxTy() const { 166 return getPointerTy(); 167 } 168 169 /// Return true if the select operation is expensive for this target. 170 bool isSelectExpensive() const { return SelectIsExpensive; } 171 172 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const { 173 return true; 174 } 175 176 /// Return true if a vector of the given type should be split 177 /// (TypeSplitVector) instead of promoted (TypePromoteInteger) during type 178 /// legalization. 179 virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; } 180 181 /// Return true if integer divide is usually cheaper than a sequence of 182 /// several shifts, adds, and multiplies for this target. 183 bool isIntDivCheap() const { return IntDivIsCheap; } 184 185 /// Returns true if target has indicated at least one type should be bypassed. 186 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); } 187 188 /// Returns map of slow types for division or remainder with corresponding 189 /// fast types 190 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const { 191 return BypassSlowDivWidths; 192 } 193 194 /// Return true if pow2 div is cheaper than a chain of srl/add/sra. 195 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 196 197 /// Return true if Flow Control is an expensive operation that should be 198 /// avoided. 199 bool isJumpExpensive() const { return JumpIsExpensive; } 200 201 /// Return true if selects are only cheaper than branches if the branch is 202 /// unlikely to be predicted right. 203 bool isPredictableSelectExpensive() const { 204 return PredictableSelectIsExpensive; 205 } 206 207 /// Return the ValueType of the result of SETCC operations. Also used to 208 /// obtain the target's preferred type for the condition operand of SELECT and 209 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other 210 /// since there are no other operands to get a type hint from. 211 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 212 213 /// Return the ValueType for comparison libcalls. Comparions libcalls include 214 /// floating point comparion calls, and Ordered/Unordered check calls on 215 /// floating point numbers. 216 virtual 217 MVT::SimpleValueType getCmpLibcallReturnType() const; 218 219 /// For targets without i1 registers, this gives the nature of the high-bits 220 /// of boolean values held in types wider than i1. 221 /// 222 /// "Boolean values" are special true/false values produced by nodes like 223 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 224 /// Not to be confused with general values promoted from i1. Some cpus 225 /// distinguish between vectors of boolean and scalars; the isVec parameter 226 /// selects between the two kinds. For example on X86 a scalar boolean should 227 /// be zero extended from i1, while the elements of a vector of booleans 228 /// should be sign extended from i1. 229 BooleanContent getBooleanContents(bool isVec) const { 230 return isVec ? BooleanVectorContents : BooleanContents; 231 } 232 233 /// Return target scheduling preference. 234 Sched::Preference getSchedulingPreference() const { 235 return SchedPreferenceInfo; 236 } 237 238 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics 239 /// for different nodes. This function returns the preference (or none) for 240 /// the given node. 241 virtual Sched::Preference getSchedulingPreference(SDNode *) const { 242 return Sched::None; 243 } 244 245 /// Return the register class that should be used for the specified value 246 /// type. 247 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { 248 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 249 assert(RC && "This value type is not natively supported!"); 250 return RC; 251 } 252 253 /// Return the 'representative' register class for the specified value 254 /// type. 255 /// 256 /// The 'representative' register class is the largest legal super-reg 257 /// register class for the register class of the value type. For example, on 258 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep 259 /// register class is GR64 on x86_64. 260 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { 261 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; 262 return RC; 263 } 264 265 /// Return the cost of the 'representative' register class for the specified 266 /// value type. 267 virtual uint8_t getRepRegClassCostFor(MVT VT) const { 268 return RepRegClassCostForVT[VT.SimpleTy]; 269 } 270 271 /// Return true if the target has native support for the specified value type. 272 /// This means that it has a register that directly holds it without 273 /// promotions or expansions. 274 bool isTypeLegal(EVT VT) const { 275 assert(!VT.isSimple() || 276 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 277 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 278 } 279 280 class ValueTypeActionImpl { 281 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum 282 /// that indicates how instruction selection should deal with the type. 283 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 284 285 public: 286 ValueTypeActionImpl() { 287 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 288 } 289 290 LegalizeTypeAction getTypeAction(MVT VT) const { 291 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; 292 } 293 294 void setTypeAction(MVT VT, LegalizeTypeAction Action) { 295 unsigned I = VT.SimpleTy; 296 ValueTypeActions[I] = Action; 297 } 298 }; 299 300 const ValueTypeActionImpl &getValueTypeActions() const { 301 return ValueTypeActions; 302 } 303 304 /// Return how we should legalize values of this type, either it is already 305 /// legal (return 'Legal') or we need to promote it to a larger type (return 306 /// 'Promote'), or we need to expand it into multiple registers of smaller 307 /// integer type (return 'Expand'). 'Custom' is not an option. 308 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { 309 return getTypeConversion(Context, VT).first; 310 } 311 LegalizeTypeAction getTypeAction(MVT VT) const { 312 return ValueTypeActions.getTypeAction(VT); 313 } 314 315 /// For types supported by the target, this is an identity function. For 316 /// types that must be promoted to larger types, this returns the larger type 317 /// to promote to. For integer types that are larger than the largest integer 318 /// register, this contains one step in the expansion to get to the smaller 319 /// register. For illegal floating point types, this returns the integer type 320 /// to transform to. 321 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 322 return getTypeConversion(Context, VT).second; 323 } 324 325 /// For types supported by the target, this is an identity function. For 326 /// types that must be expanded (i.e. integer types that are larger than the 327 /// largest integer register or illegal floating point types), this returns 328 /// the largest legal type it will be expanded to. 329 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 330 assert(!VT.isVector()); 331 while (true) { 332 switch (getTypeAction(Context, VT)) { 333 case TypeLegal: 334 return VT; 335 case TypeExpandInteger: 336 VT = getTypeToTransformTo(Context, VT); 337 break; 338 default: 339 llvm_unreachable("Type is not legal nor is it to be expanded!"); 340 } 341 } 342 } 343 344 /// Vector types are broken down into some number of legal first class types. 345 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 346 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 347 /// turns into 4 EVT::i32 values with both PPC and X86. 348 /// 349 /// This method returns the number of registers needed, and the VT for each 350 /// register. It also returns the VT and quantity of the intermediate values 351 /// before they are promoted/expanded. 352 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 353 EVT &IntermediateVT, 354 unsigned &NumIntermediates, 355 MVT &RegisterVT) const; 356 357 struct IntrinsicInfo { 358 unsigned opc; // target opcode 359 EVT memVT; // memory VT 360 const Value* ptrVal; // value representing memory location 361 int offset; // offset off of ptrVal 362 unsigned align; // alignment 363 bool vol; // is volatile? 364 bool readMem; // reads memory? 365 bool writeMem; // writes memory? 366 }; 367 368 /// Given an intrinsic, checks if on the target the intrinsic will need to map 369 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns 370 /// true and store the intrinsic information into the IntrinsicInfo that was 371 /// passed to the function. 372 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 373 unsigned /*Intrinsic*/) const { 374 return false; 375 } 376 377 /// Returns true if the target can instruction select the specified FP 378 /// immediate natively. If false, the legalizer will materialize the FP 379 /// immediate as a load from a constant pool. 380 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const { 381 return false; 382 } 383 384 /// Targets can use this to indicate that they only support *some* 385 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a 386 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be 387 /// legal. 388 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 389 EVT /*VT*/) const { 390 return true; 391 } 392 393 /// Returns true if the operation can trap for the value type. 394 /// 395 /// VT must be a legal type. By default, we optimistically assume most 396 /// operations don't trap except for divide and remainder. 397 virtual bool canOpTrap(unsigned Op, EVT VT) const; 398 399 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to 400 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace 401 /// a VAND with a constant pool entry. 402 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 403 EVT /*VT*/) const { 404 return false; 405 } 406 407 /// Return how this operation should be treated: either it is legal, needs to 408 /// be promoted to a larger size, needs to be expanded to some other code 409 /// sequence, or the target has a custom expander for it. 410 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 411 if (VT.isExtended()) return Expand; 412 // If a target-specific SDNode requires legalization, require the target 413 // to provide custom legalization for it. 414 if (Op > array_lengthof(OpActions[0])) return Custom; 415 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 416 return (LegalizeAction)OpActions[I][Op]; 417 } 418 419 /// Return true if the specified operation is legal on this target or can be 420 /// made legal with custom lowering. This is used to help guide high-level 421 /// lowering decisions. 422 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 423 return (VT == MVT::Other || isTypeLegal(VT)) && 424 (getOperationAction(Op, VT) == Legal || 425 getOperationAction(Op, VT) == Custom); 426 } 427 428 /// Return true if the specified operation is legal on this target or can be 429 /// made legal using promotion. This is used to help guide high-level lowering 430 /// decisions. 431 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const { 432 return (VT == MVT::Other || isTypeLegal(VT)) && 433 (getOperationAction(Op, VT) == Legal || 434 getOperationAction(Op, VT) == Promote); 435 } 436 437 /// Return true if the specified operation is illegal on this target or 438 /// unlikely to be made legal with custom lowering. This is used to help guide 439 /// high-level lowering decisions. 440 bool isOperationExpand(unsigned Op, EVT VT) const { 441 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); 442 } 443 444 /// Return true if the specified operation is legal on this target. 445 bool isOperationLegal(unsigned Op, EVT VT) const { 446 return (VT == MVT::Other || isTypeLegal(VT)) && 447 getOperationAction(Op, VT) == Legal; 448 } 449 450 /// Return how this load with extension should be treated: either it is legal, 451 /// needs to be promoted to a larger size, needs to be expanded to some other 452 /// code sequence, or the target has a custom expander for it. 453 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const { 454 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 455 "Table isn't big enough!"); 456 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType]; 457 } 458 459 /// Return true if the specified load with extension is legal on this target. 460 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 461 return VT.isSimple() && 462 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal; 463 } 464 465 /// Return how this store with truncation should be treated: either it is 466 /// legal, needs to be promoted to a larger size, needs to be expanded to some 467 /// other code sequence, or the target has a custom expander for it. 468 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const { 469 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 470 "Table isn't big enough!"); 471 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy] 472 [MemVT.SimpleTy]; 473 } 474 475 /// Return true if the specified store with truncation is legal on this 476 /// target. 477 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 478 return isTypeLegal(ValVT) && MemVT.isSimple() && 479 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal; 480 } 481 482 /// Return how the indexed load should be treated: either it is legal, needs 483 /// to be promoted to a larger size, needs to be expanded to some other code 484 /// sequence, or the target has a custom expander for it. 485 LegalizeAction 486 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 487 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 488 "Table isn't big enough!"); 489 unsigned Ty = (unsigned)VT.SimpleTy; 490 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 491 } 492 493 /// Return true if the specified indexed load is legal on this target. 494 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 495 return VT.isSimple() && 496 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || 497 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); 498 } 499 500 /// Return how the indexed store should be treated: either it is legal, needs 501 /// to be promoted to a larger size, needs to be expanded to some other code 502 /// sequence, or the target has a custom expander for it. 503 LegalizeAction 504 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 505 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE && 506 "Table isn't big enough!"); 507 unsigned Ty = (unsigned)VT.SimpleTy; 508 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 509 } 510 511 /// Return true if the specified indexed load is legal on this target. 512 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 513 return VT.isSimple() && 514 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || 515 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); 516 } 517 518 /// Return how the condition code should be treated: either it is legal, needs 519 /// to be expanded to some other code sequence, or the target has a custom 520 /// expander for it. 521 LegalizeAction 522 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 523 assert((unsigned)CC < array_lengthof(CondCodeActions) && 524 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) && 525 "Table isn't big enough!"); 526 // See setCondCodeAction for how this is encoded. 527 uint32_t Shift = 2 * (VT.SimpleTy & 0xF); 528 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4]; 529 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3); 530 assert(Action != Promote && "Can't promote condition code!"); 531 return Action; 532 } 533 534 /// Return true if the specified condition code is legal on this target. 535 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 536 return 537 getCondCodeAction(CC, VT) == Legal || 538 getCondCodeAction(CC, VT) == Custom; 539 } 540 541 542 /// If the action for this operation is to promote, this method returns the 543 /// ValueType to promote to. 544 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 545 assert(getOperationAction(Op, VT) == Promote && 546 "This operation isn't promoted!"); 547 548 // See if this has an explicit type specified. 549 std::map<std::pair<unsigned, MVT::SimpleValueType>, 550 MVT::SimpleValueType>::const_iterator PTTI = 551 PromoteToType.find(std::make_pair(Op, VT.SimpleTy)); 552 if (PTTI != PromoteToType.end()) return PTTI->second; 553 554 assert((VT.isInteger() || VT.isFloatingPoint()) && 555 "Cannot autopromote this type, add it with AddPromotedToType."); 556 557 MVT NVT = VT; 558 do { 559 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1); 560 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 561 "Didn't find type to promote to!"); 562 } while (!isTypeLegal(NVT) || 563 getOperationAction(Op, NVT) == Promote); 564 return NVT; 565 } 566 567 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM 568 /// operations except for the pointer size. If AllowUnknown is true, this 569 /// will return MVT::Other for types with no EVT counterpart (e.g. structs), 570 /// otherwise it will assert. 571 EVT getValueType(Type *Ty, bool AllowUnknown = false) const { 572 // Lower scalar pointers to native pointer types. 573 if (PointerType *PTy = dyn_cast<PointerType>(Ty)) 574 return getPointerTy(PTy->getAddressSpace()); 575 576 if (Ty->isVectorTy()) { 577 VectorType *VTy = cast<VectorType>(Ty); 578 Type *Elm = VTy->getElementType(); 579 // Lower vectors of pointers to native pointer types. 580 if (PointerType *PT = dyn_cast<PointerType>(Elm)) { 581 EVT PointerTy(getPointerTy(PT->getAddressSpace())); 582 Elm = PointerTy.getTypeForEVT(Ty->getContext()); 583 } 584 585 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), 586 VTy->getNumElements()); 587 } 588 return EVT::getEVT(Ty, AllowUnknown); 589 } 590 591 /// Return the MVT corresponding to this LLVM type. See getValueType. 592 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const { 593 return getValueType(Ty, AllowUnknown).getSimpleVT(); 594 } 595 596 /// Return the desired alignment for ByVal aggregate function arguments in the 597 /// caller parameter area. This is the actual alignment, not its logarithm. 598 virtual unsigned getByValTypeAlignment(Type *Ty) const; 599 600 /// Return the type of registers that this ValueType will eventually require. 601 MVT getRegisterType(MVT VT) const { 602 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 603 return RegisterTypeForVT[VT.SimpleTy]; 604 } 605 606 /// Return the type of registers that this ValueType will eventually require. 607 MVT getRegisterType(LLVMContext &Context, EVT VT) const { 608 if (VT.isSimple()) { 609 assert((unsigned)VT.getSimpleVT().SimpleTy < 610 array_lengthof(RegisterTypeForVT)); 611 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 612 } 613 if (VT.isVector()) { 614 EVT VT1; 615 MVT RegisterVT; 616 unsigned NumIntermediates; 617 (void)getVectorTypeBreakdown(Context, VT, VT1, 618 NumIntermediates, RegisterVT); 619 return RegisterVT; 620 } 621 if (VT.isInteger()) { 622 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 623 } 624 llvm_unreachable("Unsupported extended type!"); 625 } 626 627 /// Return the number of registers that this ValueType will eventually 628 /// require. 629 /// 630 /// This is one for any types promoted to live in larger registers, but may be 631 /// more than one for types (like i64) that are split into pieces. For types 632 /// like i140, which are first promoted then expanded, it is the number of 633 /// registers needed to hold all the bits of the original type. For an i140 634 /// on a 32 bit machine this means 5 registers. 635 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 636 if (VT.isSimple()) { 637 assert((unsigned)VT.getSimpleVT().SimpleTy < 638 array_lengthof(NumRegistersForVT)); 639 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 640 } 641 if (VT.isVector()) { 642 EVT VT1; 643 MVT VT2; 644 unsigned NumIntermediates; 645 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 646 } 647 if (VT.isInteger()) { 648 unsigned BitWidth = VT.getSizeInBits(); 649 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 650 return (BitWidth + RegWidth - 1) / RegWidth; 651 } 652 llvm_unreachable("Unsupported extended type!"); 653 } 654 655 /// If true, then instruction selection should seek to shrink the FP constant 656 /// of the specified type to a smaller type in order to save space and / or 657 /// reduce runtime. 658 virtual bool ShouldShrinkFPConstant(EVT) const { return true; } 659 660 /// If true, the target has custom DAG combine transformations that it can 661 /// perform for the specified node. 662 bool hasTargetDAGCombine(ISD::NodeType NT) const { 663 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 664 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 665 } 666 667 /// \brief Get maximum # of store operations permitted for llvm.memset 668 /// 669 /// This function returns the maximum number of store operations permitted 670 /// to replace a call to llvm.memset. The value is set by the target at the 671 /// performance threshold for such a replacement. If OptSize is true, 672 /// return the limit for functions that have OptSize attribute. 673 unsigned getMaxStoresPerMemset(bool OptSize) const { 674 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset; 675 } 676 677 /// \brief Get maximum # of store operations permitted for llvm.memcpy 678 /// 679 /// This function returns the maximum number of store operations permitted 680 /// to replace a call to llvm.memcpy. The value is set by the target at the 681 /// performance threshold for such a replacement. If OptSize is true, 682 /// return the limit for functions that have OptSize attribute. 683 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 684 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy; 685 } 686 687 /// \brief Get maximum # of store operations permitted for llvm.memmove 688 /// 689 /// This function returns the maximum number of store operations permitted 690 /// to replace a call to llvm.memmove. The value is set by the target at the 691 /// performance threshold for such a replacement. If OptSize is true, 692 /// return the limit for functions that have OptSize attribute. 693 unsigned getMaxStoresPerMemmove(bool OptSize) const { 694 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove; 695 } 696 697 /// \brief Determine if the target supports unaligned memory accesses. 698 /// 699 /// This function returns true if the target allows unaligned memory accesses. 700 /// of the specified type. If true, it also returns whether the unaligned 701 /// memory access is "fast" in the second argument by reference. This is used, 702 /// for example, in situations where an array copy/move/set is converted to a 703 /// sequence of store operations. It's use helps to ensure that such 704 /// replacements don't generate code that causes an alignment error (trap) on 705 /// the target machine. 706 virtual bool allowsUnalignedMemoryAccesses(EVT, bool * /*Fast*/ = 0) const { 707 return false; 708 } 709 710 /// Returns the target specific optimal type for load and store operations as 711 /// a result of memset, memcpy, and memmove lowering. 712 /// 713 /// If DstAlign is zero that means it's safe to destination alignment can 714 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't 715 /// a need to check it against alignment requirement, probably because the 716 /// source does not need to be loaded. If 'IsMemset' is true, that means it's 717 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of 718 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it 719 /// does not need to be loaded. It returns EVT::Other if the type should be 720 /// determined using generic target-independent logic. 721 virtual EVT getOptimalMemOpType(uint64_t /*Size*/, 722 unsigned /*DstAlign*/, unsigned /*SrcAlign*/, 723 bool /*IsMemset*/, 724 bool /*ZeroMemset*/, 725 bool /*MemcpyStrSrc*/, 726 MachineFunction &/*MF*/) const { 727 return MVT::Other; 728 } 729 730 /// Returns true if it's safe to use load / store of the specified type to 731 /// expand memcpy / memset inline. 732 /// 733 /// This is mostly true for all types except for some special cases. For 734 /// example, on X86 targets without SSE2 f64 load / store are done with fldl / 735 /// fstpl which also does type conversion. Note the specified type doesn't 736 /// have to be legal as the hook is used before type legalization. 737 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; } 738 739 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp. 740 bool usesUnderscoreSetJmp() const { 741 return UseUnderscoreSetJmp; 742 } 743 744 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp. 745 bool usesUnderscoreLongJmp() const { 746 return UseUnderscoreLongJmp; 747 } 748 749 /// Return whether the target can generate code for jump tables. 750 bool supportJumpTables() const { 751 return SupportJumpTables; 752 } 753 754 /// Return integer threshold on number of blocks to use jump tables rather 755 /// than if sequence. 756 int getMinimumJumpTableEntries() const { 757 return MinimumJumpTableEntries; 758 } 759 760 /// If a physical register, this specifies the register that 761 /// llvm.savestack/llvm.restorestack should save and restore. 762 unsigned getStackPointerRegisterToSaveRestore() const { 763 return StackPointerRegisterToSaveRestore; 764 } 765 766 /// If a physical register, this returns the register that receives the 767 /// exception address on entry to a landing pad. 768 unsigned getExceptionPointerRegister() const { 769 return ExceptionPointerRegister; 770 } 771 772 /// If a physical register, this returns the register that receives the 773 /// exception typeid on entry to a landing pad. 774 unsigned getExceptionSelectorRegister() const { 775 return ExceptionSelectorRegister; 776 } 777 778 /// Returns the target's jmp_buf size in bytes (if never set, the default is 779 /// 200) 780 unsigned getJumpBufSize() const { 781 return JumpBufSize; 782 } 783 784 /// Returns the target's jmp_buf alignment in bytes (if never set, the default 785 /// is 0) 786 unsigned getJumpBufAlignment() const { 787 return JumpBufAlignment; 788 } 789 790 /// Return the minimum stack alignment of an argument. 791 unsigned getMinStackArgumentAlignment() const { 792 return MinStackArgumentAlignment; 793 } 794 795 /// Return the minimum function alignment. 796 unsigned getMinFunctionAlignment() const { 797 return MinFunctionAlignment; 798 } 799 800 /// Return the preferred function alignment. 801 unsigned getPrefFunctionAlignment() const { 802 return PrefFunctionAlignment; 803 } 804 805 /// Return the preferred loop alignment. 806 unsigned getPrefLoopAlignment() const { 807 return PrefLoopAlignment; 808 } 809 810 /// Return whether the DAG builder should automatically insert fences and 811 /// reduce ordering for atomics. 812 bool getInsertFencesForAtomic() const { 813 return InsertFencesForAtomic; 814 } 815 816 /// Return true if the target stores stack protector cookies at a fixed offset 817 /// in some non-standard address space, and populates the address space and 818 /// offset as appropriate. 819 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/, 820 unsigned &/*Offset*/) const { 821 return false; 822 } 823 824 /// Returns the maximal possible offset which can be used for loads / stores 825 /// from the global. 826 virtual unsigned getMaximalGlobalOffset() const { 827 return 0; 828 } 829 830 //===--------------------------------------------------------------------===// 831 /// \name Helpers for TargetTransformInfo implementations 832 /// @{ 833 834 /// Get the ISD node that corresponds to the Instruction class opcode. 835 int InstructionOpcodeToISD(unsigned Opcode) const; 836 837 /// Estimate the cost of type-legalization and the legalized type. 838 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const; 839 840 /// @} 841 842 //===--------------------------------------------------------------------===// 843 // TargetLowering Configuration Methods - These methods should be invoked by 844 // the derived class constructor to configure this object for the target. 845 // 846 847 /// \brief Reset the operation actions based on target options. 848 virtual void resetOperationActions() {} 849 850protected: 851 /// Specify how the target extends the result of a boolean value from i1 to a 852 /// wider type. See getBooleanContents. 853 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 854 855 /// Specify how the target extends the result of a vector boolean value from a 856 /// vector of i1 to a wider type. See getBooleanContents. 857 void setBooleanVectorContents(BooleanContent Ty) { 858 BooleanVectorContents = Ty; 859 } 860 861 /// Specify the target scheduling preference. 862 void setSchedulingPreference(Sched::Preference Pref) { 863 SchedPreferenceInfo = Pref; 864 } 865 866 /// Indicate whether this target prefers to use _setjmp to implement 867 /// llvm.setjmp or the non _ version. Defaults to false. 868 void setUseUnderscoreSetJmp(bool Val) { 869 UseUnderscoreSetJmp = Val; 870 } 871 872 /// Indicate whether this target prefers to use _longjmp to implement 873 /// llvm.longjmp or the non _ version. Defaults to false. 874 void setUseUnderscoreLongJmp(bool Val) { 875 UseUnderscoreLongJmp = Val; 876 } 877 878 /// Indicate whether the target can generate code for jump tables. 879 void setSupportJumpTables(bool Val) { 880 SupportJumpTables = Val; 881 } 882 883 /// Indicate the number of blocks to generate jump tables rather than if 884 /// sequence. 885 void setMinimumJumpTableEntries(int Val) { 886 MinimumJumpTableEntries = Val; 887 } 888 889 /// If set to a physical register, this specifies the register that 890 /// llvm.savestack/llvm.restorestack should save and restore. 891 void setStackPointerRegisterToSaveRestore(unsigned R) { 892 StackPointerRegisterToSaveRestore = R; 893 } 894 895 /// If set to a physical register, this sets the register that receives the 896 /// exception address on entry to a landing pad. 897 void setExceptionPointerRegister(unsigned R) { 898 ExceptionPointerRegister = R; 899 } 900 901 /// If set to a physical register, this sets the register that receives the 902 /// exception typeid on entry to a landing pad. 903 void setExceptionSelectorRegister(unsigned R) { 904 ExceptionSelectorRegister = R; 905 } 906 907 /// Tells the code generator not to expand operations into sequences that use 908 /// the select operations if possible. 909 void setSelectIsExpensive(bool isExpensive = true) { 910 SelectIsExpensive = isExpensive; 911 } 912 913 /// Tells the code generator not to expand sequence of operations into a 914 /// separate sequences that increases the amount of flow control. 915 void setJumpIsExpensive(bool isExpensive = true) { 916 JumpIsExpensive = isExpensive; 917 } 918 919 /// Tells the code generator that integer divide is expensive, and if 920 /// possible, should be replaced by an alternate sequence of instructions not 921 /// containing an integer divide. 922 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 923 924 /// Tells the code generator which bitwidths to bypass. 925 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { 926 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; 927 } 928 929 /// Tells the code generator that it shouldn't generate srl/add/sra for a 930 /// signed divide by power of two, and let the target handle it. 931 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 932 933 /// Add the specified register class as an available regclass for the 934 /// specified value type. This indicates the selector can handle values of 935 /// that class natively. 936 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { 937 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); 938 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 939 RegClassForVT[VT.SimpleTy] = RC; 940 } 941 942 /// Remove all register classes. 943 void clearRegisterClasses() { 944 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*)); 945 946 AvailableRegClasses.clear(); 947 } 948 949 /// \brief Remove all operation actions. 950 void clearOperationActions() { 951 } 952 953 /// Return the largest legal super-reg register class of the register class 954 /// for the specified type and its associated "cost". 955 virtual std::pair<const TargetRegisterClass*, uint8_t> 956 findRepresentativeClass(MVT VT) const; 957 958 /// Once all of the register classes are added, this allows us to compute 959 /// derived properties we expose. 960 void computeRegisterProperties(); 961 962 /// Indicate that the specified operation does not work with the specified 963 /// type and indicate what to do about it. 964 void setOperationAction(unsigned Op, MVT VT, 965 LegalizeAction Action) { 966 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 967 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 968 } 969 970 /// Indicate that the specified load with extension does not work with the 971 /// specified type and indicate what to do about it. 972 void setLoadExtAction(unsigned ExtType, MVT VT, 973 LegalizeAction Action) { 974 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 975 "Table isn't big enough!"); 976 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 977 } 978 979 /// Indicate that the specified truncating store does not work with the 980 /// specified type and indicate what to do about it. 981 void setTruncStoreAction(MVT ValVT, MVT MemVT, 982 LegalizeAction Action) { 983 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 984 "Table isn't big enough!"); 985 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 986 } 987 988 /// Indicate that the specified indexed load does or does not work with the 989 /// specified type and indicate what to do abort it. 990 /// 991 /// NOTE: All indexed mode loads are initialized to Expand in 992 /// TargetLowering.cpp 993 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 994 LegalizeAction Action) { 995 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 996 (unsigned)Action < 0xf && "Table isn't big enough!"); 997 // Load action are kept in the upper half. 998 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 999 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1000 } 1001 1002 /// Indicate that the specified indexed store does or does not work with the 1003 /// specified type and indicate what to do about it. 1004 /// 1005 /// NOTE: All indexed mode stores are initialized to Expand in 1006 /// TargetLowering.cpp 1007 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1008 LegalizeAction Action) { 1009 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1010 (unsigned)Action < 0xf && "Table isn't big enough!"); 1011 // Store action are kept in the lower half. 1012 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1013 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1014 } 1015 1016 /// Indicate that the specified condition code is or isn't supported on the 1017 /// target and indicate what to do about it. 1018 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1019 LegalizeAction Action) { 1020 assert(VT < MVT::LAST_VALUETYPE && 1021 (unsigned)CC < array_lengthof(CondCodeActions) && 1022 "Table isn't big enough!"); 1023 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit 1024 /// value and the upper 27 bits index into the second dimension of the array 1025 /// to select what 32-bit value to use. 1026 uint32_t Shift = 2 * (VT.SimpleTy & 0xF); 1027 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift); 1028 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift; 1029 } 1030 1031 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults 1032 /// to trying a larger integer/fp until it can find one that works. If that 1033 /// default is insufficient, this method can be used by the target to override 1034 /// the default. 1035 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1036 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1037 } 1038 1039 /// Targets should invoke this method for each target independent node that 1040 /// they want to provide a custom DAG combiner for by implementing the 1041 /// PerformDAGCombine virtual method. 1042 void setTargetDAGCombine(ISD::NodeType NT) { 1043 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1044 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1045 } 1046 1047 /// Set the target's required jmp_buf buffer size (in bytes); default is 200 1048 void setJumpBufSize(unsigned Size) { 1049 JumpBufSize = Size; 1050 } 1051 1052 /// Set the target's required jmp_buf buffer alignment (in bytes); default is 1053 /// 0 1054 void setJumpBufAlignment(unsigned Align) { 1055 JumpBufAlignment = Align; 1056 } 1057 1058 /// Set the target's minimum function alignment (in log2(bytes)) 1059 void setMinFunctionAlignment(unsigned Align) { 1060 MinFunctionAlignment = Align; 1061 } 1062 1063 /// Set the target's preferred function alignment. This should be set if 1064 /// there is a performance benefit to higher-than-minimum alignment (in 1065 /// log2(bytes)) 1066 void setPrefFunctionAlignment(unsigned Align) { 1067 PrefFunctionAlignment = Align; 1068 } 1069 1070 /// Set the target's preferred loop alignment. Default alignment is zero, it 1071 /// means the target does not care about loop alignment. The alignment is 1072 /// specified in log2(bytes). 1073 void setPrefLoopAlignment(unsigned Align) { 1074 PrefLoopAlignment = Align; 1075 } 1076 1077 /// Set the minimum stack alignment of an argument (in log2(bytes)). 1078 void setMinStackArgumentAlignment(unsigned Align) { 1079 MinStackArgumentAlignment = Align; 1080 } 1081 1082 /// Set if the DAG builder should automatically insert fences and reduce the 1083 /// order of atomic memory operations to Monotonic. 1084 void setInsertFencesForAtomic(bool fence) { 1085 InsertFencesForAtomic = fence; 1086 } 1087 1088public: 1089 //===--------------------------------------------------------------------===// 1090 // Addressing mode description hooks (used by LSR etc). 1091 // 1092 1093 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store 1094 /// instructions reading the address. This allows as much computation as 1095 /// possible to be done in the address mode for that operand. This hook lets 1096 /// targets also pass back when this should be done on intrinsics which 1097 /// load/store. 1098 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/, 1099 SmallVectorImpl<Value*> &/*Ops*/, 1100 Type *&/*AccessTy*/) const { 1101 return false; 1102 } 1103 1104 /// This represents an addressing mode of: 1105 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1106 /// If BaseGV is null, there is no BaseGV. 1107 /// If BaseOffs is zero, there is no base offset. 1108 /// If HasBaseReg is false, there is no base register. 1109 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1110 /// no scale. 1111 struct AddrMode { 1112 GlobalValue *BaseGV; 1113 int64_t BaseOffs; 1114 bool HasBaseReg; 1115 int64_t Scale; 1116 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1117 }; 1118 1119 /// Return true if the addressing mode represented by AM is legal for this 1120 /// target, for a load/store of the specified type. 1121 /// 1122 /// The type may be VoidTy, in which case only return true if the addressing 1123 /// mode is legal for a load/store of any legal type. TODO: Handle 1124 /// pre/postinc as well. 1125 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 1126 1127 /// \brief Return the cost of the scaling factor used in the addressing mode 1128 /// represented by AM for this target, for a load/store of the specified type. 1129 /// 1130 /// If the AM is supported, the return value must be >= 0. 1131 /// If the AM is not supported, it returns a negative value. 1132 /// TODO: Handle pre/postinc as well. 1133 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const { 1134 // Default: assume that any scaling factor used in a legal AM is free. 1135 if (isLegalAddressingMode(AM, Ty)) return 0; 1136 return -1; 1137 } 1138 1139 /// Return true if the specified immediate is legal icmp immediate, that is 1140 /// the target has icmp instructions which can compare a register against the 1141 /// immediate without having to materialize the immediate into a register. 1142 virtual bool isLegalICmpImmediate(int64_t) const { 1143 return true; 1144 } 1145 1146 /// Return true if the specified immediate is legal add immediate, that is the 1147 /// target has add instructions which can add a register with the immediate 1148 /// without having to materialize the immediate into a register. 1149 virtual bool isLegalAddImmediate(int64_t) const { 1150 return true; 1151 } 1152 1153 /// Return true if it's free to truncate a value of type Ty1 to type 1154 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 1155 /// by referencing its sub-register AX. 1156 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1157 return false; 1158 } 1159 1160 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding 1161 /// whether a call is in tail position. Typically this means that both results 1162 /// would be assigned to the same register or stack slot, but it could mean 1163 /// the target performs adequate checks of its own before proceeding with the 1164 /// tail call. 1165 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const { 1166 return false; 1167 } 1168 1169 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const { 1170 return false; 1171 } 1172 1173 /// Return true if any actual instruction that defines a value of type Ty1 1174 /// implicitly zero-extends the value to Ty2 in the result register. 1175 /// 1176 /// This does not necessarily include registers defined in unknown ways, such 1177 /// as incoming arguments, or copies from unknown virtual registers. Also, if 1178 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to 1179 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit 1180 /// values implicit zero-extend the result out to 64 bits. 1181 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1182 return false; 1183 } 1184 1185 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const { 1186 return false; 1187 } 1188 1189 /// Return true if the target supplies and combines to a paired load 1190 /// two loaded values of type LoadedType next to each other in memory. 1191 /// RequiredAlignment gives the minimal alignment constraints that must be met 1192 /// to be able to select this paired load. 1193 /// 1194 /// This information is *not* used to generate actual paired loads, but it is 1195 /// used to generate a sequence of loads that is easier to combine into a 1196 /// paired load. 1197 /// For instance, something like this: 1198 /// a = load i64* addr 1199 /// b = trunc i64 a to i32 1200 /// c = lshr i64 a, 32 1201 /// d = trunc i64 c to i32 1202 /// will be optimized into: 1203 /// b = load i32* addr1 1204 /// d = load i32* addr2 1205 /// Where addr1 = addr2 +/- sizeof(i32). 1206 /// 1207 /// In other words, unless the target performs a post-isel load combining, 1208 /// this information should not be provided because it will generate more 1209 /// loads. 1210 virtual bool hasPairedLoad(Type * /*LoadedType*/, 1211 unsigned & /*RequiredAligment*/) const { 1212 return false; 1213 } 1214 1215 virtual bool hasPairedLoad(EVT /*LoadedType*/, 1216 unsigned & /*RequiredAligment*/) const { 1217 return false; 1218 } 1219 1220 /// Return true if zero-extending the specific node Val to type VT2 is free 1221 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or 1222 /// because it's folded such as X86 zero-extending loads). 1223 virtual bool isZExtFree(SDValue Val, EVT VT2) const { 1224 return isZExtFree(Val.getValueType(), VT2); 1225 } 1226 1227 /// Return true if an fneg operation is free to the point where it is never 1228 /// worthwhile to replace it with a bitwise operation. 1229 virtual bool isFNegFree(EVT VT) const { 1230 assert(VT.isFloatingPoint()); 1231 return false; 1232 } 1233 1234 /// Return true if an fabs operation is free to the point where it is never 1235 /// worthwhile to replace it with a bitwise operation. 1236 virtual bool isFAbsFree(EVT VT) const { 1237 assert(VT.isFloatingPoint()); 1238 return false; 1239 } 1240 1241 /// Return true if an FMA operation is faster than a pair of fmul and fadd 1242 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method 1243 /// returns true, otherwise fmuladd is expanded to fmul + fadd. 1244 /// 1245 /// NOTE: This may be called before legalization on types for which FMAs are 1246 /// not legal, but should return true if those types will eventually legalize 1247 /// to types that support FMAs. After legalization, it will only be called on 1248 /// types that support FMAs (via Legal or Custom actions) 1249 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const { 1250 return false; 1251 } 1252 1253 /// Return true if it's profitable to narrow operations of type VT1 to 1254 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from 1255 /// i32 to i16. 1256 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { 1257 return false; 1258 } 1259 1260 //===--------------------------------------------------------------------===// 1261 // Runtime Library hooks 1262 // 1263 1264 /// Rename the default libcall routine name for the specified libcall. 1265 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1266 LibcallRoutineNames[Call] = Name; 1267 } 1268 1269 /// Get the libcall routine name for the specified libcall. 1270 const char *getLibcallName(RTLIB::Libcall Call) const { 1271 return LibcallRoutineNames[Call]; 1272 } 1273 1274 /// Override the default CondCode to be used to test the result of the 1275 /// comparison libcall against zero. 1276 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1277 CmpLibcallCCs[Call] = CC; 1278 } 1279 1280 /// Get the CondCode that's to be used to test the result of the comparison 1281 /// libcall against zero. 1282 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1283 return CmpLibcallCCs[Call]; 1284 } 1285 1286 /// Set the CallingConv that should be used for the specified libcall. 1287 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1288 LibcallCallingConvs[Call] = CC; 1289 } 1290 1291 /// Get the CallingConv that should be used for the specified libcall. 1292 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1293 return LibcallCallingConvs[Call]; 1294 } 1295 1296private: 1297 const TargetMachine &TM; 1298 const DataLayout *TD; 1299 const TargetLoweringObjectFile &TLOF; 1300 1301 /// True if this is a little endian target. 1302 bool IsLittleEndian; 1303 1304 /// Tells the code generator not to expand operations into sequences that use 1305 /// the select operations if possible. 1306 bool SelectIsExpensive; 1307 1308 /// Tells the code generator not to expand integer divides by constants into a 1309 /// sequence of muls, adds, and shifts. This is a hack until a real cost 1310 /// model is in place. If we ever optimize for size, this will be set to true 1311 /// unconditionally. 1312 bool IntDivIsCheap; 1313 1314 /// Tells the code generator to bypass slow divide or remainder 1315 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code 1316 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer 1317 /// div/rem when the operands are positive and less than 256. 1318 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths; 1319 1320 /// Tells the code generator that it shouldn't generate srl/add/sra for a 1321 /// signed divide by power of two, and let the target handle it. 1322 bool Pow2DivIsCheap; 1323 1324 /// Tells the code generator that it shouldn't generate extra flow control 1325 /// instructions and should attempt to combine flow control instructions via 1326 /// predication. 1327 bool JumpIsExpensive; 1328 1329 /// This target prefers to use _setjmp to implement llvm.setjmp. 1330 /// 1331 /// Defaults to false. 1332 bool UseUnderscoreSetJmp; 1333 1334 /// This target prefers to use _longjmp to implement llvm.longjmp. 1335 /// 1336 /// Defaults to false. 1337 bool UseUnderscoreLongJmp; 1338 1339 /// Whether the target can generate code for jumptables. If it's not true, 1340 /// then each jumptable must be lowered into if-then-else's. 1341 bool SupportJumpTables; 1342 1343 /// Number of blocks threshold to use jump tables. 1344 int MinimumJumpTableEntries; 1345 1346 /// Information about the contents of the high-bits in boolean values held in 1347 /// a type wider than i1. See getBooleanContents. 1348 BooleanContent BooleanContents; 1349 1350 /// Information about the contents of the high-bits in boolean vector values 1351 /// when the element type is wider than i1. See getBooleanContents. 1352 BooleanContent BooleanVectorContents; 1353 1354 /// The target scheduling preference: shortest possible total cycles or lowest 1355 /// register usage. 1356 Sched::Preference SchedPreferenceInfo; 1357 1358 /// The size, in bytes, of the target's jmp_buf buffers 1359 unsigned JumpBufSize; 1360 1361 /// The alignment, in bytes, of the target's jmp_buf buffers 1362 unsigned JumpBufAlignment; 1363 1364 /// The minimum alignment that any argument on the stack needs to have. 1365 unsigned MinStackArgumentAlignment; 1366 1367 /// The minimum function alignment (used when optimizing for size, and to 1368 /// prevent explicitly provided alignment from leading to incorrect code). 1369 unsigned MinFunctionAlignment; 1370 1371 /// The preferred function alignment (used when alignment unspecified and 1372 /// optimizing for speed). 1373 unsigned PrefFunctionAlignment; 1374 1375 /// The preferred loop alignment. 1376 unsigned PrefLoopAlignment; 1377 1378 /// Whether the DAG builder should automatically insert fences and reduce 1379 /// ordering for atomics. (This will be set for for most architectures with 1380 /// weak memory ordering.) 1381 bool InsertFencesForAtomic; 1382 1383 /// If set to a physical register, this specifies the register that 1384 /// llvm.savestack/llvm.restorestack should save and restore. 1385 unsigned StackPointerRegisterToSaveRestore; 1386 1387 /// If set to a physical register, this specifies the register that receives 1388 /// the exception address on entry to a landing pad. 1389 unsigned ExceptionPointerRegister; 1390 1391 /// If set to a physical register, this specifies the register that receives 1392 /// the exception typeid on entry to a landing pad. 1393 unsigned ExceptionSelectorRegister; 1394 1395 /// This indicates the default register class to use for each ValueType the 1396 /// target supports natively. 1397 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1398 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1399 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1400 1401 /// This indicates the "representative" register class to use for each 1402 /// ValueType the target supports natively. This information is used by the 1403 /// scheduler to track register pressure. By default, the representative 1404 /// register class is the largest legal super-reg register class of the 1405 /// register class of the specified type. e.g. On x86, i8, i16, and i32's 1406 /// representative class would be GR32. 1407 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1408 1409 /// This indicates the "cost" of the "representative" register class for each 1410 /// ValueType. The cost is used by the scheduler to approximate register 1411 /// pressure. 1412 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1413 1414 /// For any value types we are promoting or expanding, this contains the value 1415 /// type that we are changing to. For Expanded types, this contains one step 1416 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required 1417 /// (e.g. i64 -> i16). For types natively supported by the system, this holds 1418 /// the same type (e.g. i32 -> i32). 1419 MVT TransformToType[MVT::LAST_VALUETYPE]; 1420 1421 /// For each operation and each value type, keep a LegalizeAction that 1422 /// indicates how instruction selection should deal with the operation. Most 1423 /// operations are Legal (aka, supported natively by the target), but 1424 /// operations that are not should be described. Note that operations on 1425 /// non-legal value types are not described here. 1426 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1427 1428 /// For each load extension type and each value type, keep a LegalizeAction 1429 /// that indicates how instruction selection should deal with a load of a 1430 /// specific value type and extension type. 1431 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1432 1433 /// For each value type pair keep a LegalizeAction that indicates whether a 1434 /// truncating store of a specific value type and truncating type is legal. 1435 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1436 1437 /// For each indexed mode and each value type, keep a pair of LegalizeAction 1438 /// that indicates how instruction selection should deal with the load / 1439 /// store. 1440 /// 1441 /// The first dimension is the value_type for the reference. The second 1442 /// dimension represents the various modes for load store. 1443 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1444 1445 /// For each condition code (ISD::CondCode) keep a LegalizeAction that 1446 /// indicates how instruction selection should deal with the condition code. 1447 /// 1448 /// Because each CC action takes up 2 bits, we need to have the array size be 1449 /// large enough to fit all of the value types. This can be done by rounding 1450 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16. 1451 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16]; 1452 1453 ValueTypeActionImpl ValueTypeActions; 1454 1455public: 1456 LegalizeKind 1457 getTypeConversion(LLVMContext &Context, EVT VT) const { 1458 // If this is a simple type, use the ComputeRegisterProp mechanism. 1459 if (VT.isSimple()) { 1460 MVT SVT = VT.getSimpleVT(); 1461 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 1462 MVT NVT = TransformToType[SVT.SimpleTy]; 1463 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 1464 1465 assert( 1466 (LA == TypeLegal || 1467 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) 1468 && "Promote may not follow Expand or Promote"); 1469 1470 if (LA == TypeSplitVector) 1471 return LegalizeKind(LA, EVT::getVectorVT(Context, 1472 SVT.getVectorElementType(), 1473 SVT.getVectorNumElements()/2)); 1474 if (LA == TypeScalarizeVector) 1475 return LegalizeKind(LA, SVT.getVectorElementType()); 1476 return LegalizeKind(LA, NVT); 1477 } 1478 1479 // Handle Extended Scalar Types. 1480 if (!VT.isVector()) { 1481 assert(VT.isInteger() && "Float types must be simple"); 1482 unsigned BitSize = VT.getSizeInBits(); 1483 // First promote to a power-of-two size, then expand if necessary. 1484 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1485 EVT NVT = VT.getRoundIntegerType(Context); 1486 assert(NVT != VT && "Unable to round integer VT"); 1487 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1488 // Avoid multi-step promotion. 1489 if (NextStep.first == TypePromoteInteger) return NextStep; 1490 // Return rounded integer type. 1491 return LegalizeKind(TypePromoteInteger, NVT); 1492 } 1493 1494 return LegalizeKind(TypeExpandInteger, 1495 EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); 1496 } 1497 1498 // Handle vector types. 1499 unsigned NumElts = VT.getVectorNumElements(); 1500 EVT EltVT = VT.getVectorElementType(); 1501 1502 // Vectors with only one element are always scalarized. 1503 if (NumElts == 1) 1504 return LegalizeKind(TypeScalarizeVector, EltVT); 1505 1506 // Try to widen vector elements until the element type is a power of two and 1507 // promote it to a legal type later on, for example: 1508 // <3 x i8> -> <4 x i8> -> <4 x i32> 1509 if (EltVT.isInteger()) { 1510 // Vectors with a number of elements that is not a power of two are always 1511 // widened, for example <3 x i8> -> <4 x i8>. 1512 if (!VT.isPow2VectorType()) { 1513 NumElts = (unsigned)NextPowerOf2(NumElts); 1514 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1515 return LegalizeKind(TypeWidenVector, NVT); 1516 } 1517 1518 // Examine the element type. 1519 LegalizeKind LK = getTypeConversion(Context, EltVT); 1520 1521 // If type is to be expanded, split the vector. 1522 // <4 x i140> -> <2 x i140> 1523 if (LK.first == TypeExpandInteger) 1524 return LegalizeKind(TypeSplitVector, 1525 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1526 1527 // Promote the integer element types until a legal vector type is found 1528 // or until the element integer type is too big. If a legal type was not 1529 // found, fallback to the usual mechanism of widening/splitting the 1530 // vector. 1531 EVT OldEltVT = EltVT; 1532 while (1) { 1533 // Increase the bitwidth of the element to the next pow-of-two 1534 // (which is greater than 8 bits). 1535 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() 1536 ).getRoundIntegerType(Context); 1537 1538 // Stop trying when getting a non-simple element type. 1539 // Note that vector elements may be greater than legal vector element 1540 // types. Example: X86 XMM registers hold 64bit element on 32bit 1541 // systems. 1542 if (!EltVT.isSimple()) break; 1543 1544 // Build a new vector type and check if it is legal. 1545 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1546 // Found a legal promoted vector type. 1547 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1548 return LegalizeKind(TypePromoteInteger, 1549 EVT::getVectorVT(Context, EltVT, NumElts)); 1550 } 1551 1552 // Reset the type to the unexpanded type if we did not find a legal vector 1553 // type with a promoted vector element type. 1554 EltVT = OldEltVT; 1555 } 1556 1557 // Try to widen the vector until a legal type is found. 1558 // If there is no wider legal type, split the vector. 1559 while (1) { 1560 // Round up to the next power of 2. 1561 NumElts = (unsigned)NextPowerOf2(NumElts); 1562 1563 // If there is no simple vector type with this many elements then there 1564 // cannot be a larger legal vector type. Note that this assumes that 1565 // there are no skipped intermediate vector types in the simple types. 1566 if (!EltVT.isSimple()) break; 1567 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1568 if (LargerVector == MVT()) break; 1569 1570 // If this type is legal then widen the vector. 1571 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1572 return LegalizeKind(TypeWidenVector, LargerVector); 1573 } 1574 1575 // Widen odd vectors to next power of two. 1576 if (!VT.isPow2VectorType()) { 1577 EVT NVT = VT.getPow2VectorType(Context); 1578 return LegalizeKind(TypeWidenVector, NVT); 1579 } 1580 1581 // Vectors with illegal element types are expanded. 1582 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1583 return LegalizeKind(TypeSplitVector, NVT); 1584 } 1585 1586private: 1587 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses; 1588 1589 /// Targets can specify ISD nodes that they would like PerformDAGCombine 1590 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this 1591 /// array. 1592 unsigned char 1593 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1594 1595 /// For operations that must be promoted to a specific type, this holds the 1596 /// destination type. This map should be sparse, so don't hold it as an 1597 /// array. 1598 /// 1599 /// Targets add entries to this map with AddPromotedToType(..), clients access 1600 /// this with getTypeToPromoteTo(..). 1601 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1602 PromoteToType; 1603 1604 /// Stores the name each libcall. 1605 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1606 1607 /// The ISD::CondCode that should be used to test the result of each of the 1608 /// comparison libcall against zero. 1609 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1610 1611 /// Stores the CallingConv that should be used for each libcall. 1612 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1613 1614protected: 1615 /// \brief Specify maximum number of store instructions per memset call. 1616 /// 1617 /// When lowering \@llvm.memset this field specifies the maximum number of 1618 /// store operations that may be substituted for the call to memset. Targets 1619 /// must set this value based on the cost threshold for that target. Targets 1620 /// should assume that the memset will be done using as many of the largest 1621 /// store operations first, followed by smaller ones, if necessary, per 1622 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1623 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1624 /// store. This only applies to setting a constant array of a constant size. 1625 unsigned MaxStoresPerMemset; 1626 1627 /// Maximum number of stores operations that may be substituted for the call 1628 /// to memset, used for functions with OptSize attribute. 1629 unsigned MaxStoresPerMemsetOptSize; 1630 1631 /// \brief Specify maximum bytes of store instructions per memcpy call. 1632 /// 1633 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1634 /// store operations that may be substituted for a call to memcpy. Targets 1635 /// must set this value based on the cost threshold for that target. Targets 1636 /// should assume that the memcpy will be done using as many of the largest 1637 /// store operations first, followed by smaller ones, if necessary, per 1638 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1639 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1640 /// and one 1-byte store. This only applies to copying a constant array of 1641 /// constant size. 1642 unsigned MaxStoresPerMemcpy; 1643 1644 /// Maximum number of store operations that may be substituted for a call to 1645 /// memcpy, used for functions with OptSize attribute. 1646 unsigned MaxStoresPerMemcpyOptSize; 1647 1648 /// \brief Specify maximum bytes of store instructions per memmove call. 1649 /// 1650 /// When lowering \@llvm.memmove this field specifies the maximum number of 1651 /// store instructions that may be substituted for a call to memmove. Targets 1652 /// must set this value based on the cost threshold for that target. Targets 1653 /// should assume that the memmove will be done using as many of the largest 1654 /// store operations first, followed by smaller ones, if necessary, per 1655 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1656 /// with 8-bit alignment would result in nine 1-byte stores. This only 1657 /// applies to copying a constant array of constant size. 1658 unsigned MaxStoresPerMemmove; 1659 1660 /// Maximum number of store instructions that may be substituted for a call to 1661 /// memmove, used for functions with OpSize attribute. 1662 unsigned MaxStoresPerMemmoveOptSize; 1663 1664 /// Tells the code generator that select is more expensive than a branch if 1665 /// the branch is usually predicted right. 1666 bool PredictableSelectIsExpensive; 1667 1668protected: 1669 /// Return true if the value types that can be represented by the specified 1670 /// register class are all legal. 1671 bool isLegalRC(const TargetRegisterClass *RC) const; 1672}; 1673 1674/// This class defines information used to lower LLVM code to legal SelectionDAG 1675/// operators that the target instruction selector can accept natively. 1676/// 1677/// This class also defines callbacks that targets must implement to lower 1678/// target-specific constructs to SelectionDAG operators. 1679class TargetLowering : public TargetLoweringBase { 1680 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION; 1681 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION; 1682 1683public: 1684 /// NOTE: The constructor takes ownership of TLOF. 1685 explicit TargetLowering(const TargetMachine &TM, 1686 const TargetLoweringObjectFile *TLOF); 1687 1688 /// Returns true by value, base pointer and offset pointer and addressing mode 1689 /// by reference if the node's address can be legally represented as 1690 /// pre-indexed load / store address. 1691 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, 1692 SDValue &/*Offset*/, 1693 ISD::MemIndexedMode &/*AM*/, 1694 SelectionDAG &/*DAG*/) const { 1695 return false; 1696 } 1697 1698 /// Returns true by value, base pointer and offset pointer and addressing mode 1699 /// by reference if this node can be combined with a load / store to form a 1700 /// post-indexed load / store. 1701 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, 1702 SDValue &/*Base*/, 1703 SDValue &/*Offset*/, 1704 ISD::MemIndexedMode &/*AM*/, 1705 SelectionDAG &/*DAG*/) const { 1706 return false; 1707 } 1708 1709 /// Return the entry encoding for a jump table in the current function. The 1710 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum. 1711 virtual unsigned getJumpTableEncoding() const; 1712 1713 virtual const MCExpr * 1714 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/, 1715 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/, 1716 MCContext &/*Ctx*/) const { 1717 llvm_unreachable("Need to implement this hook if target has custom JTIs"); 1718 } 1719 1720 /// Returns relocation base for the given PIC jumptable. 1721 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 1722 SelectionDAG &DAG) const; 1723 1724 /// This returns the relocation base for the given PIC jumptable, the same as 1725 /// getPICJumpTableRelocBase, but as an MCExpr. 1726 virtual const MCExpr * 1727 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1728 unsigned JTI, MCContext &Ctx) const; 1729 1730 /// Return true if folding a constant offset with the given GlobalAddress is 1731 /// legal. It is frequently not legal in PIC relocation models. 1732 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 1733 1734 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 1735 SDValue &Chain) const; 1736 1737 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, 1738 SDValue &NewLHS, SDValue &NewRHS, 1739 ISD::CondCode &CCCode, SDLoc DL) const; 1740 1741 /// Returns a pair of (return value, chain). 1742 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, 1743 EVT RetVT, const SDValue *Ops, 1744 unsigned NumOps, bool isSigned, 1745 SDLoc dl, bool doesNotReturn = false, 1746 bool isReturnValueUsed = true) const; 1747 1748 //===--------------------------------------------------------------------===// 1749 // TargetLowering Optimization Methods 1750 // 1751 1752 /// A convenience struct that encapsulates a DAG, and two SDValues for 1753 /// returning information from TargetLowering to its clients that want to 1754 /// combine. 1755 struct TargetLoweringOpt { 1756 SelectionDAG &DAG; 1757 bool LegalTys; 1758 bool LegalOps; 1759 SDValue Old; 1760 SDValue New; 1761 1762 explicit TargetLoweringOpt(SelectionDAG &InDAG, 1763 bool LT, bool LO) : 1764 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 1765 1766 bool LegalTypes() const { return LegalTys; } 1767 bool LegalOperations() const { return LegalOps; } 1768 1769 bool CombineTo(SDValue O, SDValue N) { 1770 Old = O; 1771 New = N; 1772 return true; 1773 } 1774 1775 /// Check to see if the specified operand of the specified instruction is a 1776 /// constant integer. If so, check to see if there are any bits set in the 1777 /// constant that are not demanded. If so, shrink the constant and return 1778 /// true. 1779 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 1780 1781 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This 1782 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be 1783 /// generalized for targets with other types of implicit widening casts. 1784 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 1785 SDLoc dl); 1786 }; 1787 1788 /// Look at Op. At this point, we know that only the DemandedMask bits of the 1789 /// result of Op are ever used downstream. If we can use this information to 1790 /// simplify Op, create a new simplified DAG node and return true, returning 1791 /// the original and new nodes in Old and New. Otherwise, analyze the 1792 /// expression and return a mask of KnownOne and KnownZero bits for the 1793 /// expression (used to simplify the caller). The KnownZero/One bits may only 1794 /// be accurate for those bits in the DemandedMask. 1795 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 1796 APInt &KnownZero, APInt &KnownOne, 1797 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 1798 1799 /// Determine which of the bits specified in Mask are known to be either zero 1800 /// or one and return them in the KnownZero/KnownOne bitsets. 1801 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 1802 APInt &KnownZero, 1803 APInt &KnownOne, 1804 const SelectionDAG &DAG, 1805 unsigned Depth = 0) const; 1806 1807 /// This method can be implemented by targets that want to expose additional 1808 /// information about sign bits to the DAG Combiner. 1809 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 1810 unsigned Depth = 0) const; 1811 1812 struct DAGCombinerInfo { 1813 void *DC; // The DAG Combiner object. 1814 CombineLevel Level; 1815 bool CalledByLegalizer; 1816 public: 1817 SelectionDAG &DAG; 1818 1819 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc) 1820 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {} 1821 1822 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } 1823 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } 1824 bool isAfterLegalizeVectorOps() const { 1825 return Level == AfterLegalizeDAG; 1826 } 1827 CombineLevel getDAGCombineLevel() { return Level; } 1828 bool isCalledByLegalizer() const { return CalledByLegalizer; } 1829 1830 void AddToWorklist(SDNode *N); 1831 void RemoveFromWorklist(SDNode *N); 1832 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 1833 bool AddTo = true); 1834 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 1835 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 1836 1837 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 1838 }; 1839 1840 /// Try to simplify a setcc built with the specified operands and cc. If it is 1841 /// unable to simplify it, return a null SDValue. 1842 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1843 ISD::CondCode Cond, bool foldBooleans, 1844 DAGCombinerInfo &DCI, SDLoc dl) const; 1845 1846 /// Returns true (and the GlobalValue and the offset) if the node is a 1847 /// GlobalAddress + offset. 1848 virtual bool 1849 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 1850 1851 /// This method will be invoked for all target nodes and for any 1852 /// target-independent nodes that the target has registered with invoke it 1853 /// for. 1854 /// 1855 /// The semantics are as follows: 1856 /// Return Value: 1857 /// SDValue.Val == 0 - No change was made 1858 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 1859 /// otherwise - N should be replaced by the returned Operand. 1860 /// 1861 /// In addition, methods provided by DAGCombinerInfo may be used to perform 1862 /// more complex transformations. 1863 /// 1864 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 1865 1866 /// Return true if the target has native support for the specified value type 1867 /// and it is 'desirable' to use the type for the given node type. e.g. On x86 1868 /// i16 is legal, but undesirable since i16 instruction encodings are longer 1869 /// and some i16 instructions are slow. 1870 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { 1871 // By default, assume all legal types are desirable. 1872 return isTypeLegal(VT); 1873 } 1874 1875 /// Return true if it is profitable for dag combiner to transform a floating 1876 /// point op of specified opcode to a equivalent op of an integer 1877 /// type. e.g. f32 load -> i32 load can be profitable on ARM. 1878 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, 1879 EVT /*VT*/) const { 1880 return false; 1881 } 1882 1883 /// This method query the target whether it is beneficial for dag combiner to 1884 /// promote the specified node. If true, it should return the desired 1885 /// promotion type by reference. 1886 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { 1887 return false; 1888 } 1889 1890 //===--------------------------------------------------------------------===// 1891 // Lowering methods - These methods must be implemented by targets so that 1892 // the SelectionDAGBuilder code knows how to lower these. 1893 // 1894 1895 /// This hook must be implemented to lower the incoming (formal) arguments, 1896 /// described by the Ins array, into the specified DAG. The implementation 1897 /// should fill in the InVals array with legal-type argument values, and 1898 /// return the resulting token chain value. 1899 /// 1900 virtual SDValue 1901 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1902 bool /*isVarArg*/, 1903 const SmallVectorImpl<ISD::InputArg> &/*Ins*/, 1904 SDLoc /*dl*/, SelectionDAG &/*DAG*/, 1905 SmallVectorImpl<SDValue> &/*InVals*/) const { 1906 llvm_unreachable("Not Implemented"); 1907 } 1908 1909 struct ArgListEntry { 1910 SDValue Node; 1911 Type* Ty; 1912 bool isSExt : 1; 1913 bool isZExt : 1; 1914 bool isInReg : 1; 1915 bool isSRet : 1; 1916 bool isNest : 1; 1917 bool isByVal : 1; 1918 bool isReturned : 1; 1919 uint16_t Alignment; 1920 1921 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1922 isSRet(false), isNest(false), isByVal(false), isReturned(false), 1923 Alignment(0) { } 1924 1925 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx); 1926 }; 1927 typedef std::vector<ArgListEntry> ArgListTy; 1928 1929 /// This structure contains all information that is necessary for lowering 1930 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder 1931 /// needs to lower a call, and targets will see this struct in their LowerCall 1932 /// implementation. 1933 struct CallLoweringInfo { 1934 SDValue Chain; 1935 Type *RetTy; 1936 bool RetSExt : 1; 1937 bool RetZExt : 1; 1938 bool IsVarArg : 1; 1939 bool IsInReg : 1; 1940 bool DoesNotReturn : 1; 1941 bool IsReturnValueUsed : 1; 1942 1943 // IsTailCall should be modified by implementations of 1944 // TargetLowering::LowerCall that perform tail call conversions. 1945 bool IsTailCall; 1946 1947 unsigned NumFixedArgs; 1948 CallingConv::ID CallConv; 1949 SDValue Callee; 1950 ArgListTy &Args; 1951 SelectionDAG &DAG; 1952 SDLoc DL; 1953 ImmutableCallSite *CS; 1954 SmallVector<ISD::OutputArg, 32> Outs; 1955 SmallVector<SDValue, 32> OutVals; 1956 SmallVector<ISD::InputArg, 32> Ins; 1957 1958 1959 /// Constructs a call lowering context based on the ImmutableCallSite \p cs. 1960 CallLoweringInfo(SDValue chain, Type *retTy, 1961 FunctionType *FTy, bool isTailCall, SDValue callee, 1962 ArgListTy &args, SelectionDAG &dag, SDLoc dl, 1963 ImmutableCallSite &cs) 1964 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)), 1965 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()), 1966 IsInReg(cs.paramHasAttr(0, Attribute::InReg)), 1967 DoesNotReturn(cs.doesNotReturn()), 1968 IsReturnValueUsed(!cs.getInstruction()->use_empty()), 1969 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()), 1970 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag), 1971 DL(dl), CS(&cs) {} 1972 1973 /// Constructs a call lowering context based on the provided call 1974 /// information. 1975 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt, 1976 bool isVarArg, bool isInReg, unsigned numFixedArgs, 1977 CallingConv::ID callConv, bool isTailCall, 1978 bool doesNotReturn, bool isReturnValueUsed, SDValue callee, 1979 ArgListTy &args, SelectionDAG &dag, SDLoc dl) 1980 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt), 1981 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn), 1982 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall), 1983 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee), 1984 Args(args), DAG(dag), DL(dl), CS(NULL) {} 1985 }; 1986 1987 /// This function lowers an abstract call to a function into an actual call. 1988 /// This returns a pair of operands. The first element is the return value 1989 /// for the function (if RetTy is not VoidTy). The second element is the 1990 /// outgoing token chain. It calls LowerCall to do the actual lowering. 1991 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const; 1992 1993 /// This hook must be implemented to lower calls into the the specified 1994 /// DAG. The outgoing arguments to the call are described by the Outs array, 1995 /// and the values to be returned by the call are described by the Ins 1996 /// array. The implementation should fill in the InVals array with legal-type 1997 /// return values from the call, and return the resulting token chain value. 1998 virtual SDValue 1999 LowerCall(CallLoweringInfo &/*CLI*/, 2000 SmallVectorImpl<SDValue> &/*InVals*/) const { 2001 llvm_unreachable("Not Implemented"); 2002 } 2003 2004 /// Target-specific cleanup for formal ByVal parameters. 2005 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {} 2006 2007 /// This hook should be implemented to check whether the return values 2008 /// described by the Outs array can fit into the return registers. If false 2009 /// is returned, an sret-demotion is performed. 2010 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, 2011 MachineFunction &/*MF*/, bool /*isVarArg*/, 2012 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 2013 LLVMContext &/*Context*/) const 2014 { 2015 // Return true by default to get preexisting behavior. 2016 return true; 2017 } 2018 2019 /// This hook must be implemented to lower outgoing return values, described 2020 /// by the Outs array, into the specified DAG. The implementation should 2021 /// return the resulting token chain value. 2022 virtual SDValue 2023 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 2024 bool /*isVarArg*/, 2025 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 2026 const SmallVectorImpl<SDValue> &/*OutVals*/, 2027 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const { 2028 llvm_unreachable("Not Implemented"); 2029 } 2030 2031 /// Return true if result of the specified node is used by a return node 2032 /// only. It also compute and return the input chain for the tail call. 2033 /// 2034 /// This is used to determine whether it is possible to codegen a libcall as 2035 /// tail call at legalization time. 2036 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const { 2037 return false; 2038 } 2039 2040 /// Return true if the target may be able emit the call instruction as a tail 2041 /// call. This is used by optimization passes to determine if it's profitable 2042 /// to duplicate return instructions to enable tailcall optimization. 2043 virtual bool mayBeEmittedAsTailCall(CallInst *) const { 2044 return false; 2045 } 2046 2047 /// Return the type that should be used to zero or sign extend a 2048 /// zeroext/signext integer argument or return value. FIXME: Most C calling 2049 /// convention requires the return type to be promoted, but this is not true 2050 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C 2051 /// calling conventions. The frontend should handle this and include all of 2052 /// the necessary information. 2053 virtual MVT getTypeForExtArgOrReturn(MVT VT, 2054 ISD::NodeType /*ExtendKind*/) const { 2055 MVT MinVT = getRegisterType(MVT::i32); 2056 return VT.bitsLT(MinVT) ? MinVT : VT; 2057 } 2058 2059 /// Returns a 0 terminated array of registers that can be safely used as 2060 /// scratch registers. 2061 virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const { 2062 return NULL; 2063 } 2064 2065 /// This callback is invoked by the type legalizer to legalize nodes with an 2066 /// illegal operand type but legal result types. It replaces the 2067 /// LowerOperation callback in the type Legalizer. The reason we can not do 2068 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to 2069 /// use this callback. 2070 /// 2071 /// TODO: Consider merging with ReplaceNodeResults. 2072 /// 2073 /// The target places new result values for the node in Results (their number 2074 /// and types must exactly match those of the original return values of 2075 /// the node), or leaves Results empty, which indicates that the node is not 2076 /// to be custom lowered after all. 2077 /// The default implementation calls LowerOperation. 2078 virtual void LowerOperationWrapper(SDNode *N, 2079 SmallVectorImpl<SDValue> &Results, 2080 SelectionDAG &DAG) const; 2081 2082 /// This callback is invoked for operations that are unsupported by the 2083 /// target, which are registered to use 'custom' lowering, and whose defined 2084 /// values are all legal. If the target has no operations that require custom 2085 /// lowering, it need not implement this. The default implementation of this 2086 /// aborts. 2087 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 2088 2089 /// This callback is invoked when a node result type is illegal for the 2090 /// target, and the operation was registered to use 'custom' lowering for that 2091 /// result type. The target places new result values for the node in Results 2092 /// (their number and types must exactly match those of the original return 2093 /// values of the node), or leaves Results empty, which indicates that the 2094 /// node is not to be custom lowered after all. 2095 /// 2096 /// If the target has no operations that require custom lowering, it need not 2097 /// implement this. The default implementation aborts. 2098 virtual void ReplaceNodeResults(SDNode * /*N*/, 2099 SmallVectorImpl<SDValue> &/*Results*/, 2100 SelectionDAG &/*DAG*/) const { 2101 llvm_unreachable("ReplaceNodeResults not implemented for this target!"); 2102 } 2103 2104 /// This method returns the name of a target specific DAG node. 2105 virtual const char *getTargetNodeName(unsigned Opcode) const; 2106 2107 /// This method returns a target specific FastISel object, or null if the 2108 /// target does not support "fast" ISel. 2109 virtual FastISel *createFastISel(FunctionLoweringInfo &, 2110 const TargetLibraryInfo *) const { 2111 return 0; 2112 } 2113 2114 //===--------------------------------------------------------------------===// 2115 // Inline Asm Support hooks 2116 // 2117 2118 /// This hook allows the target to expand an inline asm call to be explicit 2119 /// llvm code if it wants to. This is useful for turning simple inline asms 2120 /// into LLVM intrinsics, which gives the compiler more information about the 2121 /// behavior of the code. 2122 virtual bool ExpandInlineAsm(CallInst *) const { 2123 return false; 2124 } 2125 2126 enum ConstraintType { 2127 C_Register, // Constraint represents specific register(s). 2128 C_RegisterClass, // Constraint represents any of register(s) in class. 2129 C_Memory, // Memory constraint. 2130 C_Other, // Something else. 2131 C_Unknown // Unsupported constraint. 2132 }; 2133 2134 enum ConstraintWeight { 2135 // Generic weights. 2136 CW_Invalid = -1, // No match. 2137 CW_Okay = 0, // Acceptable. 2138 CW_Good = 1, // Good weight. 2139 CW_Better = 2, // Better weight. 2140 CW_Best = 3, // Best weight. 2141 2142 // Well-known weights. 2143 CW_SpecificReg = CW_Okay, // Specific register operands. 2144 CW_Register = CW_Good, // Register operands. 2145 CW_Memory = CW_Better, // Memory operands. 2146 CW_Constant = CW_Best, // Constant operand. 2147 CW_Default = CW_Okay // Default or don't know type. 2148 }; 2149 2150 /// This contains information for each constraint that we are lowering. 2151 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 2152 /// This contains the actual string for the code, like "m". TargetLowering 2153 /// picks the 'best' code from ConstraintInfo::Codes that most closely 2154 /// matches the operand. 2155 std::string ConstraintCode; 2156 2157 /// Information about the constraint code, e.g. Register, RegisterClass, 2158 /// Memory, Other, Unknown. 2159 TargetLowering::ConstraintType ConstraintType; 2160 2161 /// If this is the result output operand or a clobber, this is null, 2162 /// otherwise it is the incoming operand to the CallInst. This gets 2163 /// modified as the asm is processed. 2164 Value *CallOperandVal; 2165 2166 /// The ValueType for the operand value. 2167 MVT ConstraintVT; 2168 2169 /// Return true of this is an input operand that is a matching constraint 2170 /// like "4". 2171 bool isMatchingInputConstraint() const; 2172 2173 /// If this is an input matching constraint, this method returns the output 2174 /// operand it matches. 2175 unsigned getMatchedOperand() const; 2176 2177 /// Copy constructor for copying from an AsmOperandInfo. 2178 AsmOperandInfo(const AsmOperandInfo &info) 2179 : InlineAsm::ConstraintInfo(info), 2180 ConstraintCode(info.ConstraintCode), 2181 ConstraintType(info.ConstraintType), 2182 CallOperandVal(info.CallOperandVal), 2183 ConstraintVT(info.ConstraintVT) { 2184 } 2185 2186 /// Copy constructor for copying from a ConstraintInfo. 2187 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 2188 : InlineAsm::ConstraintInfo(info), 2189 ConstraintType(TargetLowering::C_Unknown), 2190 CallOperandVal(0), ConstraintVT(MVT::Other) { 2191 } 2192 }; 2193 2194 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; 2195 2196 /// Split up the constraint string from the inline assembly value into the 2197 /// specific constraints and their prefixes, and also tie in the associated 2198 /// operand values. If this returns an empty vector, and if the constraint 2199 /// string itself isn't empty, there was an error parsing. 2200 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; 2201 2202 /// Examine constraint type and operand type and determine a weight value. 2203 /// The operand object must already have been set up with the operand type. 2204 virtual ConstraintWeight getMultipleConstraintMatchWeight( 2205 AsmOperandInfo &info, int maIndex) const; 2206 2207 /// Examine constraint string and operand type and determine a weight value. 2208 /// The operand object must already have been set up with the operand type. 2209 virtual ConstraintWeight getSingleConstraintMatchWeight( 2210 AsmOperandInfo &info, const char *constraint) const; 2211 2212 /// Determines the constraint code and constraint type to use for the specific 2213 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. 2214 /// If the actual operand being passed in is available, it can be passed in as 2215 /// Op, otherwise an empty SDValue can be passed. 2216 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2217 SDValue Op, 2218 SelectionDAG *DAG = 0) const; 2219 2220 /// Given a constraint, return the type of constraint it is for this target. 2221 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 2222 2223 /// Given a physical register constraint (e.g. {edx}), return the register 2224 /// number and the register class for the register. 2225 /// 2226 /// Given a register class constraint, like 'r', if this corresponds directly 2227 /// to an LLVM register class, return a register of 0 and the register class 2228 /// pointer. 2229 /// 2230 /// This should only be used for C_Register constraints. On error, this 2231 /// returns a register number of 0 and a null register class pointer.. 2232 virtual std::pair<unsigned, const TargetRegisterClass*> 2233 getRegForInlineAsmConstraint(const std::string &Constraint, 2234 MVT VT) const; 2235 2236 /// Try to replace an X constraint, which matches anything, with another that 2237 /// has more specific requirements based on the type of the corresponding 2238 /// operand. This returns null if there is no replacement to make. 2239 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 2240 2241 /// Lower the specified operand into the Ops vector. If it is invalid, don't 2242 /// add anything to Ops. 2243 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 2244 std::vector<SDValue> &Ops, 2245 SelectionDAG &DAG) const; 2246 2247 //===--------------------------------------------------------------------===// 2248 // Div utility functions 2249 // 2250 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, 2251 SelectionDAG &DAG) const; 2252 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2253 std::vector<SDNode*> *Created) const; 2254 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2255 std::vector<SDNode*> *Created) const; 2256 2257 //===--------------------------------------------------------------------===// 2258 // Instruction Emitting Hooks 2259 // 2260 2261 /// This method should be implemented by targets that mark instructions with 2262 /// the 'usesCustomInserter' flag. These instructions are special in various 2263 /// ways, which require special support to insert. The specified MachineInstr 2264 /// is created but not inserted into any basic blocks, and this method is 2265 /// called to expand it into a sequence of instructions, potentially also 2266 /// creating new basic blocks and control flow. 2267 virtual MachineBasicBlock * 2268 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 2269 2270 /// This method should be implemented by targets that mark instructions with 2271 /// the 'hasPostISelHook' flag. These instructions must be adjusted after 2272 /// instruction selection by target hooks. e.g. To fill in optional defs for 2273 /// ARM 's' setting instructions. 2274 virtual void 2275 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 2276}; 2277 2278/// Given an LLVM IR type and return type attributes, compute the return value 2279/// EVTs and flags, and optionally also the offsets, if the return value is 2280/// being lowered to memory. 2281void GetReturnInfo(Type* ReturnType, AttributeSet attr, 2282 SmallVectorImpl<ISD::OutputArg> &Outs, 2283 const TargetLowering &TLI); 2284 2285} // end llvm namespace 2286 2287#endif 2288