TargetLowering.h revision d6662add687f20cffa0755e410efbb40de4dcf23
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/InlineAsm.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/CodeGen/RuntimeLibcalls.h" 28#include "llvm/ADT/APFloat.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallSet.h" 31#include "llvm/ADT/SmallVector.h" 32#include "llvm/ADT/STLExtras.h" 33#include "llvm/Support/DebugLoc.h" 34#include "llvm/Target/TargetMachine.h" 35#include <climits> 36#include <map> 37#include <vector> 38 39namespace llvm { 40 class AllocaInst; 41 class CallInst; 42 class Function; 43 class FastISel; 44 class MachineBasicBlock; 45 class MachineFunction; 46 class MachineFrameInfo; 47 class MachineInstr; 48 class MachineModuleInfo; 49 class DwarfWriter; 50 class SDNode; 51 class SDValue; 52 class SelectionDAG; 53 class TargetData; 54 class TargetMachine; 55 class TargetRegisterClass; 56 class TargetSubtarget; 57 class TargetLoweringObjectFile; 58 class Value; 59 60 // FIXME: should this be here? 61 namespace TLSModel { 62 enum Model { 63 GeneralDynamic, 64 LocalDynamic, 65 InitialExec, 66 LocalExec 67 }; 68 } 69 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 70 71 72//===----------------------------------------------------------------------===// 73/// TargetLowering - This class defines information used to lower LLVM code to 74/// legal SelectionDAG operators that the target instruction selector can accept 75/// natively. 76/// 77/// This class also defines callbacks that targets must implement to lower 78/// target-specific constructs to SelectionDAG operators. 79/// 80class TargetLowering { 81 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 82 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 83public: 84 /// LegalizeAction - This enum indicates whether operations are valid for a 85 /// target, and if not, what action should be used to make them valid. 86 enum LegalizeAction { 87 Legal, // The target natively supports this operation. 88 Promote, // This operation should be executed in a larger type. 89 Expand, // Try to expand this to other ops, otherwise use a libcall. 90 Custom // Use the LowerOperation hook to implement custom lowering. 91 }; 92 93 enum BooleanContent { // How the target represents true/false values. 94 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 95 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 96 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 97 }; 98 99 enum SchedPreference { 100 SchedulingForLatency, // Scheduling for shortest total latency. 101 SchedulingForRegPressure // Scheduling for lowest register pressure. 102 }; 103 104 /// NOTE: The constructor takes ownership of TLOF. 105 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF); 106 virtual ~TargetLowering(); 107 108 TargetMachine &getTargetMachine() const { return TM; } 109 const TargetData *getTargetData() const { return TD; } 110 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 111 112 bool isBigEndian() const { return !IsLittleEndian; } 113 bool isLittleEndian() const { return IsLittleEndian; } 114 MVT::SimpleValueType getPointerTy() const { return PointerTy; } 115 MVT::SimpleValueType getShiftAmountTy() const { return ShiftAmountTy; } 116 117 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 118 /// codegen. 119 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 120 121 /// isSelectExpensive - Return true if the select operation is expensive for 122 /// this target. 123 bool isSelectExpensive() const { return SelectIsExpensive; } 124 125 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 126 /// a sequence of several shifts, adds, and multiplies for this target. 127 bool isIntDivCheap() const { return IntDivIsCheap; } 128 129 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 130 /// srl/add/sra. 131 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 132 133 /// getSetCCResultType - Return the ValueType of the result of SETCC 134 /// operations. Also used to obtain the target's preferred type for 135 /// the condition operand of SELECT and BRCOND nodes. In the case of 136 /// BRCOND the argument passed is MVT::Other since there are no other 137 /// operands to get a type hint from. 138 virtual 139 MVT::SimpleValueType getSetCCResultType(MVT VT) const; 140 141 /// getBooleanContents - For targets without i1 registers, this gives the 142 /// nature of the high-bits of boolean values held in types wider than i1. 143 /// "Boolean values" are special true/false values produced by nodes like 144 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 145 /// Not to be confused with general values promoted from i1. 146 BooleanContent getBooleanContents() const { return BooleanContents;} 147 148 /// getSchedulingPreference - Return target scheduling preference. 149 SchedPreference getSchedulingPreference() const { 150 return SchedPreferenceInfo; 151 } 152 153 /// getRegClassFor - Return the register class that should be used for the 154 /// specified value type. This may only be called on legal types. 155 TargetRegisterClass *getRegClassFor(MVT VT) const { 156 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 157 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()]; 158 assert(RC && "This value type is not natively supported!"); 159 return RC; 160 } 161 162 /// isTypeLegal - Return true if the target has native support for the 163 /// specified value type. This means that it has a register that directly 164 /// holds it without promotions or expansions. 165 bool isTypeLegal(MVT VT) const { 166 assert(!VT.isSimple() || 167 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 168 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0; 169 } 170 171 class ValueTypeActionImpl { 172 /// ValueTypeActions - This is a bitvector that contains two bits for each 173 /// value type, where the two bits correspond to the LegalizeAction enum. 174 /// This can be queried with "getTypeAction(VT)". 175 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2 176 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2]; 177 public: 178 ValueTypeActionImpl() { 179 ValueTypeActions[0] = ValueTypeActions[1] = 0; 180 ValueTypeActions[2] = ValueTypeActions[3] = 0; 181 } 182 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 183 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 184 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 185 ValueTypeActions[2] = RHS.ValueTypeActions[2]; 186 ValueTypeActions[3] = RHS.ValueTypeActions[3]; 187 } 188 189 LegalizeAction getTypeAction(MVT VT) const { 190 if (VT.isExtended()) { 191 if (VT.isVector()) { 192 return VT.isPow2VectorType() ? Expand : Promote; 193 } 194 if (VT.isInteger()) 195 // First promote to a power-of-two size, then expand if necessary. 196 return VT == VT.getRoundIntegerType() ? Expand : Promote; 197 assert(0 && "Unsupported extended type!"); 198 return Legal; 199 } 200 unsigned I = VT.getSimpleVT(); 201 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 202 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 203 } 204 void setTypeAction(MVT VT, LegalizeAction Action) { 205 unsigned I = VT.getSimpleVT(); 206 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 207 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 208 } 209 }; 210 211 const ValueTypeActionImpl &getValueTypeActions() const { 212 return ValueTypeActions; 213 } 214 215 /// getTypeAction - Return how we should legalize values of this type, either 216 /// it is already legal (return 'Legal') or we need to promote it to a larger 217 /// type (return 'Promote'), or we need to expand it into multiple registers 218 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 219 LegalizeAction getTypeAction(MVT VT) const { 220 return ValueTypeActions.getTypeAction(VT); 221 } 222 223 /// getTypeToTransformTo - For types supported by the target, this is an 224 /// identity function. For types that must be promoted to larger types, this 225 /// returns the larger type to promote to. For integer types that are larger 226 /// than the largest integer register, this contains one step in the expansion 227 /// to get to the smaller register. For illegal floating point types, this 228 /// returns the integer type to transform to. 229 MVT getTypeToTransformTo(MVT VT) const { 230 if (VT.isSimple()) { 231 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType)); 232 MVT NVT = TransformToType[VT.getSimpleVT()]; 233 assert(getTypeAction(NVT) != Promote && 234 "Promote may not follow Expand or Promote"); 235 return NVT; 236 } 237 238 if (VT.isVector()) { 239 MVT NVT = VT.getPow2VectorType(); 240 if (NVT == VT) { 241 // Vector length is a power of 2 - split to half the size. 242 unsigned NumElts = VT.getVectorNumElements(); 243 MVT EltVT = VT.getVectorElementType(); 244 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2); 245 } 246 // Promote to a power of two size, avoiding multi-step promotion. 247 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 248 } else if (VT.isInteger()) { 249 MVT NVT = VT.getRoundIntegerType(); 250 if (NVT == VT) 251 // Size is a power of two - expand to half the size. 252 return MVT::getIntegerVT(VT.getSizeInBits() / 2); 253 else 254 // Promote to a power of two size, avoiding multi-step promotion. 255 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 256 } 257 assert(0 && "Unsupported extended type!"); 258 return MVT(MVT::Other); // Not reached 259 } 260 261 /// getTypeToExpandTo - For types supported by the target, this is an 262 /// identity function. For types that must be expanded (i.e. integer types 263 /// that are larger than the largest integer register or illegal floating 264 /// point types), this returns the largest legal type it will be expanded to. 265 MVT getTypeToExpandTo(MVT VT) const { 266 assert(!VT.isVector()); 267 while (true) { 268 switch (getTypeAction(VT)) { 269 case Legal: 270 return VT; 271 case Expand: 272 VT = getTypeToTransformTo(VT); 273 break; 274 default: 275 assert(false && "Type is not legal nor is it to be expanded!"); 276 return VT; 277 } 278 } 279 return VT; 280 } 281 282 /// getVectorTypeBreakdown - Vector types are broken down into some number of 283 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 284 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 285 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 286 /// 287 /// This method returns the number of registers needed, and the VT for each 288 /// register. It also returns the VT and quantity of the intermediate values 289 /// before they are promoted/expanded. 290 /// 291 unsigned getVectorTypeBreakdown(MVT VT, 292 MVT &IntermediateVT, 293 unsigned &NumIntermediates, 294 MVT &RegisterVT) const; 295 296 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 297 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 298 /// this is the case, it returns true and store the intrinsic 299 /// information into the IntrinsicInfo that was passed to the function. 300 typedef struct IntrinsicInfo { 301 unsigned opc; // target opcode 302 MVT memVT; // memory VT 303 const Value* ptrVal; // value representing memory location 304 int offset; // offset off of ptrVal 305 unsigned align; // alignment 306 bool vol; // is volatile? 307 bool readMem; // reads memory? 308 bool writeMem; // writes memory? 309 } IntrinisicInfo; 310 311 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 312 CallInst &I, unsigned Intrinsic) { 313 return false; 314 } 315 316 /// getWidenVectorType: given a vector type, returns the type to widen to 317 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 318 /// If there is no vector type that we want to widen to, returns MVT::Other 319 /// When and were to widen is target dependent based on the cost of 320 /// scalarizing vs using the wider vector type. 321 virtual MVT getWidenVectorType(MVT VT) const; 322 323 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 324 legal_fpimm_iterator legal_fpimm_begin() const { 325 return LegalFPImmediates.begin(); 326 } 327 legal_fpimm_iterator legal_fpimm_end() const { 328 return LegalFPImmediates.end(); 329 } 330 331 /// isShuffleMaskLegal - Targets can use this to indicate that they only 332 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 333 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 334 /// are assumed to be legal. 335 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 336 MVT VT) const { 337 return true; 338 } 339 340 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 341 /// used by Targets can use this to indicate if there is a suitable 342 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 343 /// pool entry. 344 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 345 MVT VT) const { 346 return false; 347 } 348 349 /// getOperationAction - Return how this operation should be treated: either 350 /// it is legal, needs to be promoted to a larger size, needs to be 351 /// expanded to some other code sequence, or the target has a custom expander 352 /// for it. 353 LegalizeAction getOperationAction(unsigned Op, MVT VT) const { 354 if (VT.isExtended()) return Expand; 355 assert(Op < array_lengthof(OpActions[0]) && 356 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 && 357 "Table isn't big enough!"); 358 unsigned I = (unsigned) VT.getSimpleVT(); 359 unsigned J = I & 31; 360 I = I >> 5; 361 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3); 362 } 363 364 /// isOperationLegalOrCustom - Return true if the specified operation is 365 /// legal on this target or can be made legal with custom lowering. This 366 /// is used to help guide high-level lowering decisions. 367 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const { 368 return (VT == MVT::Other || isTypeLegal(VT)) && 369 (getOperationAction(Op, VT) == Legal || 370 getOperationAction(Op, VT) == Custom); 371 } 372 373 /// isOperationLegal - Return true if the specified operation is legal on this 374 /// target. 375 bool isOperationLegal(unsigned Op, MVT VT) const { 376 return (VT == MVT::Other || isTypeLegal(VT)) && 377 getOperationAction(Op, VT) == Legal; 378 } 379 380 /// getLoadExtAction - Return how this load with extension should be treated: 381 /// either it is legal, needs to be promoted to a larger size, needs to be 382 /// expanded to some other code sequence, or the target has a custom expander 383 /// for it. 384 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const { 385 assert(LType < array_lengthof(LoadExtActions) && 386 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 387 "Table isn't big enough!"); 388 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3); 389 } 390 391 /// isLoadExtLegal - Return true if the specified load with extension is legal 392 /// on this target. 393 bool isLoadExtLegal(unsigned LType, MVT VT) const { 394 return VT.isSimple() && 395 (getLoadExtAction(LType, VT) == Legal || 396 getLoadExtAction(LType, VT) == Custom); 397 } 398 399 /// getTruncStoreAction - Return how this store with truncation should be 400 /// treated: either it is legal, needs to be promoted to a larger size, needs 401 /// to be expanded to some other code sequence, or the target has a custom 402 /// expander for it. 403 LegalizeAction getTruncStoreAction(MVT ValVT, 404 MVT MemVT) const { 405 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 406 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 407 "Table isn't big enough!"); 408 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >> 409 (2*MemVT.getSimpleVT())) & 3); 410 } 411 412 /// isTruncStoreLegal - Return true if the specified store with truncation is 413 /// legal on this target. 414 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const { 415 return isTypeLegal(ValVT) && MemVT.isSimple() && 416 (getTruncStoreAction(ValVT, MemVT) == Legal || 417 getTruncStoreAction(ValVT, MemVT) == Custom); 418 } 419 420 /// getIndexedLoadAction - Return how the indexed load should be treated: 421 /// either it is legal, needs to be promoted to a larger size, needs to be 422 /// expanded to some other code sequence, or the target has a custom expander 423 /// for it. 424 LegalizeAction 425 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 426 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) && 427 ((unsigned)VT.getSimpleVT()) < MVT::LAST_VALUETYPE && 428 "Table isn't big enough!"); 429 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode])); 430 } 431 432 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 433 /// on this target. 434 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const { 435 return VT.isSimple() && 436 (getIndexedLoadAction(IdxMode, VT) == Legal || 437 getIndexedLoadAction(IdxMode, VT) == Custom); 438 } 439 440 /// getIndexedStoreAction - Return how the indexed store should be treated: 441 /// either it is legal, needs to be promoted to a larger size, needs to be 442 /// expanded to some other code sequence, or the target has a custom expander 443 /// for it. 444 LegalizeAction 445 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 446 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) && 447 (unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE && 448 "Table isn't big enough!"); 449 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode])); 450 } 451 452 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 453 /// on this target. 454 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const { 455 return VT.isSimple() && 456 (getIndexedStoreAction(IdxMode, VT) == Legal || 457 getIndexedStoreAction(IdxMode, VT) == Custom); 458 } 459 460 /// getConvertAction - Return how the conversion should be treated: 461 /// either it is legal, needs to be promoted to a larger size, needs to be 462 /// expanded to some other code sequence, or the target has a custom expander 463 /// for it. 464 LegalizeAction 465 getConvertAction(MVT FromVT, MVT ToVT) const { 466 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 467 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 468 "Table isn't big enough!"); 469 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >> 470 (2*ToVT.getSimpleVT())) & 3); 471 } 472 473 /// isConvertLegal - Return true if the specified conversion is legal 474 /// on this target. 475 bool isConvertLegal(MVT FromVT, MVT ToVT) const { 476 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 477 (getConvertAction(FromVT, ToVT) == Legal || 478 getConvertAction(FromVT, ToVT) == Custom); 479 } 480 481 /// getCondCodeAction - Return how the condition code should be treated: 482 /// either it is legal, needs to be expanded to some other code sequence, 483 /// or the target has a custom expander for it. 484 LegalizeAction 485 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 486 assert((unsigned)CC < array_lengthof(CondCodeActions) && 487 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 488 "Table isn't big enough!"); 489 LegalizeAction Action = (LegalizeAction) 490 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3); 491 assert(Action != Promote && "Can't promote condition code!"); 492 return Action; 493 } 494 495 /// isCondCodeLegal - Return true if the specified condition code is legal 496 /// on this target. 497 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 498 return getCondCodeAction(CC, VT) == Legal || 499 getCondCodeAction(CC, VT) == Custom; 500 } 501 502 503 /// getTypeToPromoteTo - If the action for this operation is to promote, this 504 /// method returns the ValueType to promote to. 505 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 506 assert(getOperationAction(Op, VT) == Promote && 507 "This operation isn't promoted!"); 508 509 // See if this has an explicit type specified. 510 std::map<std::pair<unsigned, MVT::SimpleValueType>, 511 MVT::SimpleValueType>::const_iterator PTTI = 512 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT())); 513 if (PTTI != PromoteToType.end()) return PTTI->second; 514 515 assert((VT.isInteger() || VT.isFloatingPoint()) && 516 "Cannot autopromote this type, add it with AddPromotedToType."); 517 518 MVT NVT = VT; 519 do { 520 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1); 521 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 522 "Didn't find type to promote to!"); 523 } while (!isTypeLegal(NVT) || 524 getOperationAction(Op, NVT) == Promote); 525 return NVT; 526 } 527 528 /// getValueType - Return the MVT corresponding to this LLVM type. 529 /// This is fixed by the LLVM operations except for the pointer size. If 530 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 531 /// counterpart (e.g. structs), otherwise it will assert. 532 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 533 MVT VT = MVT::getMVT(Ty, AllowUnknown); 534 return VT == MVT::iPTR ? PointerTy : VT; 535 } 536 537 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 538 /// function arguments in the caller parameter area. This is the actual 539 /// alignment, not its logarithm. 540 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 541 542 /// getRegisterType - Return the type of registers that this ValueType will 543 /// eventually require. 544 MVT getRegisterType(MVT VT) const { 545 if (VT.isSimple()) { 546 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT)); 547 return RegisterTypeForVT[VT.getSimpleVT()]; 548 } 549 if (VT.isVector()) { 550 MVT VT1, RegisterVT; 551 unsigned NumIntermediates; 552 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 553 return RegisterVT; 554 } 555 if (VT.isInteger()) { 556 return getRegisterType(getTypeToTransformTo(VT)); 557 } 558 assert(0 && "Unsupported extended type!"); 559 return MVT(MVT::Other); // Not reached 560 } 561 562 /// getNumRegisters - Return the number of registers that this ValueType will 563 /// eventually require. This is one for any types promoted to live in larger 564 /// registers, but may be more than one for types (like i64) that are split 565 /// into pieces. For types like i140, which are first promoted then expanded, 566 /// it is the number of registers needed to hold all the bits of the original 567 /// type. For an i140 on a 32 bit machine this means 5 registers. 568 unsigned getNumRegisters(MVT VT) const { 569 if (VT.isSimple()) { 570 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT)); 571 return NumRegistersForVT[VT.getSimpleVT()]; 572 } 573 if (VT.isVector()) { 574 MVT VT1, VT2; 575 unsigned NumIntermediates; 576 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 577 } 578 if (VT.isInteger()) { 579 unsigned BitWidth = VT.getSizeInBits(); 580 unsigned RegWidth = getRegisterType(VT).getSizeInBits(); 581 return (BitWidth + RegWidth - 1) / RegWidth; 582 } 583 assert(0 && "Unsupported extended type!"); 584 return 0; // Not reached 585 } 586 587 /// ShouldShrinkFPConstant - If true, then instruction selection should 588 /// seek to shrink the FP constant of the specified type to a smaller type 589 /// in order to save space and / or reduce runtime. 590 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; } 591 592 /// hasTargetDAGCombine - If true, the target has custom DAG combine 593 /// transformations that it can perform for the specified node. 594 bool hasTargetDAGCombine(ISD::NodeType NT) const { 595 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 596 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 597 } 598 599 /// This function returns the maximum number of store operations permitted 600 /// to replace a call to llvm.memset. The value is set by the target at the 601 /// performance threshold for such a replacement. 602 /// @brief Get maximum # of store operations permitted for llvm.memset 603 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 604 605 /// This function returns the maximum number of store operations permitted 606 /// to replace a call to llvm.memcpy. The value is set by the target at the 607 /// performance threshold for such a replacement. 608 /// @brief Get maximum # of store operations permitted for llvm.memcpy 609 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 610 611 /// This function returns the maximum number of store operations permitted 612 /// to replace a call to llvm.memmove. The value is set by the target at the 613 /// performance threshold for such a replacement. 614 /// @brief Get maximum # of store operations permitted for llvm.memmove 615 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 616 617 /// This function returns true if the target allows unaligned memory accesses. 618 /// This is used, for example, in situations where an array copy/move/set is 619 /// converted to a sequence of store operations. It's use helps to ensure that 620 /// such replacements don't generate code that causes an alignment error 621 /// (trap) on the target machine. 622 /// @brief Determine if the target supports unaligned memory accesses. 623 bool allowsUnalignedMemoryAccesses() const { 624 return allowUnalignedMemoryAccesses; 625 } 626 627 /// This function returns true if the target would benefit from code placement 628 /// optimization. 629 /// @brief Determine if the target should perform code placement optimization. 630 bool shouldOptimizeCodePlacement() const { 631 return benefitFromCodePlacementOpt; 632 } 633 634 /// getOptimalMemOpType - Returns the target specific optimal type for load 635 /// and store operations as a result of memset, memcpy, and memmove lowering. 636 /// It returns MVT::iAny if SelectionDAG should be responsible for 637 /// determining it. 638 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, 639 bool isSrcConst, bool isSrcStr, 640 SelectionDAG &DAG) const { 641 return MVT::iAny; 642 } 643 644 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 645 /// to implement llvm.setjmp. 646 bool usesUnderscoreSetJmp() const { 647 return UseUnderscoreSetJmp; 648 } 649 650 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 651 /// to implement llvm.longjmp. 652 bool usesUnderscoreLongJmp() const { 653 return UseUnderscoreLongJmp; 654 } 655 656 /// getStackPointerRegisterToSaveRestore - If a physical register, this 657 /// specifies the register that llvm.savestack/llvm.restorestack should save 658 /// and restore. 659 unsigned getStackPointerRegisterToSaveRestore() const { 660 return StackPointerRegisterToSaveRestore; 661 } 662 663 /// getExceptionAddressRegister - If a physical register, this returns 664 /// the register that receives the exception address on entry to a landing 665 /// pad. 666 unsigned getExceptionAddressRegister() const { 667 return ExceptionPointerRegister; 668 } 669 670 /// getExceptionSelectorRegister - If a physical register, this returns 671 /// the register that receives the exception typeid on entry to a landing 672 /// pad. 673 unsigned getExceptionSelectorRegister() const { 674 return ExceptionSelectorRegister; 675 } 676 677 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 678 /// set, the default is 200) 679 unsigned getJumpBufSize() const { 680 return JumpBufSize; 681 } 682 683 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 684 /// (if never set, the default is 0) 685 unsigned getJumpBufAlignment() const { 686 return JumpBufAlignment; 687 } 688 689 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 690 /// limit. Any block whose size is greater should not be predicated. 691 unsigned getIfCvtBlockSizeLimit() const { 692 return IfCvtBlockSizeLimit; 693 } 694 695 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 696 /// block to be considered for duplication. Any block whose size is greater 697 /// should not be duplicated to facilitate its predication. 698 unsigned getIfCvtDupBlockSizeLimit() const { 699 return IfCvtDupBlockSizeLimit; 700 } 701 702 /// getPrefLoopAlignment - return the preferred loop alignment. 703 /// 704 unsigned getPrefLoopAlignment() const { 705 return PrefLoopAlignment; 706 } 707 708 /// getPreIndexedAddressParts - returns true by value, base pointer and 709 /// offset pointer and addressing mode by reference if the node's address 710 /// can be legally represented as pre-indexed load / store address. 711 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 712 SDValue &Offset, 713 ISD::MemIndexedMode &AM, 714 SelectionDAG &DAG) const { 715 return false; 716 } 717 718 /// getPostIndexedAddressParts - returns true by value, base pointer and 719 /// offset pointer and addressing mode by reference if this node can be 720 /// combined with a load / store to form a post-indexed load / store. 721 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 722 SDValue &Base, SDValue &Offset, 723 ISD::MemIndexedMode &AM, 724 SelectionDAG &DAG) const { 725 return false; 726 } 727 728 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 729 /// jumptable. 730 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 731 SelectionDAG &DAG) const; 732 733 /// isOffsetFoldingLegal - Return true if folding a constant offset 734 /// with the given GlobalAddress is legal. It is frequently not legal in 735 /// PIC relocation models. 736 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 737 738 /// getFunctionAlignment - Return the Log2 alignment of this function. 739 virtual unsigned getFunctionAlignment(const Function *) const = 0; 740 741 //===--------------------------------------------------------------------===// 742 // TargetLowering Optimization Methods 743 // 744 745 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 746 /// SDValues for returning information from TargetLowering to its clients 747 /// that want to combine 748 struct TargetLoweringOpt { 749 SelectionDAG &DAG; 750 SDValue Old; 751 SDValue New; 752 753 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 754 755 bool CombineTo(SDValue O, SDValue N) { 756 Old = O; 757 New = N; 758 return true; 759 } 760 761 /// ShrinkDemandedConstant - Check to see if the specified operand of the 762 /// specified instruction is a constant integer. If so, check to see if 763 /// there are any bits set in the constant that are not demanded. If so, 764 /// shrink the constant and return true. 765 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 766 767 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 768 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 769 /// cast, but it could be generalized for targets with other types of 770 /// implicit widening casts. 771 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 772 DebugLoc dl); 773 }; 774 775 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 776 /// DemandedMask bits of the result of Op are ever used downstream. If we can 777 /// use this information to simplify Op, create a new simplified DAG node and 778 /// return true, returning the original and new nodes in Old and New. 779 /// Otherwise, analyze the expression and return a mask of KnownOne and 780 /// KnownZero bits for the expression (used to simplify the caller). 781 /// The KnownZero/One bits may only be accurate for those bits in the 782 /// DemandedMask. 783 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 784 APInt &KnownZero, APInt &KnownOne, 785 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 786 787 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 788 /// Mask are known to be either zero or one and return them in the 789 /// KnownZero/KnownOne bitsets. 790 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 791 const APInt &Mask, 792 APInt &KnownZero, 793 APInt &KnownOne, 794 const SelectionDAG &DAG, 795 unsigned Depth = 0) const; 796 797 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 798 /// targets that want to expose additional information about sign bits to the 799 /// DAG Combiner. 800 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 801 unsigned Depth = 0) const; 802 803 struct DAGCombinerInfo { 804 void *DC; // The DAG Combiner object. 805 bool BeforeLegalize; 806 bool BeforeLegalizeOps; 807 bool CalledByLegalizer; 808 public: 809 SelectionDAG &DAG; 810 811 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 812 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 813 CalledByLegalizer(cl), DAG(dag) {} 814 815 bool isBeforeLegalize() const { return BeforeLegalize; } 816 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 817 bool isCalledByLegalizer() const { return CalledByLegalizer; } 818 819 void AddToWorklist(SDNode *N); 820 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 821 bool AddTo = true); 822 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 823 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 824 825 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 826 }; 827 828 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 829 /// and cc. If it is unable to simplify it, return a null SDValue. 830 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 831 ISD::CondCode Cond, bool foldBooleans, 832 DAGCombinerInfo &DCI, DebugLoc dl) const; 833 834 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 835 /// node is a GlobalAddress + offset. 836 virtual bool 837 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 838 839 /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 840 /// location that is 'Dist' units away from the location that the 'Base' load 841 /// is loading from. 842 bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, 843 int Dist, const MachineFrameInfo *MFI) const; 844 845 /// PerformDAGCombine - This method will be invoked for all target nodes and 846 /// for any target-independent nodes that the target has registered with 847 /// invoke it for. 848 /// 849 /// The semantics are as follows: 850 /// Return Value: 851 /// SDValue.Val == 0 - No change was made 852 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 853 /// otherwise - N should be replaced by the returned Operand. 854 /// 855 /// In addition, methods provided by DAGCombinerInfo may be used to perform 856 /// more complex transformations. 857 /// 858 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 859 860 //===--------------------------------------------------------------------===// 861 // TargetLowering Configuration Methods - These methods should be invoked by 862 // the derived class constructor to configure this object for the target. 863 // 864 865protected: 866 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 867 /// GOT for PC-relative code. 868 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 869 870 /// setShiftAmountType - Describe the type that should be used for shift 871 /// amounts. This type defaults to the pointer type. 872 void setShiftAmountType(MVT::SimpleValueType VT) { ShiftAmountTy = VT; } 873 874 /// setBooleanContents - Specify how the target extends the result of a 875 /// boolean value from i1 to a wider type. See getBooleanContents. 876 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 877 878 /// setSchedulingPreference - Specify the target scheduling preference. 879 void setSchedulingPreference(SchedPreference Pref) { 880 SchedPreferenceInfo = Pref; 881 } 882 883 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 884 /// use _setjmp to implement llvm.setjmp or the non _ version. 885 /// Defaults to false. 886 void setUseUnderscoreSetJmp(bool Val) { 887 UseUnderscoreSetJmp = Val; 888 } 889 890 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 891 /// use _longjmp to implement llvm.longjmp or the non _ version. 892 /// Defaults to false. 893 void setUseUnderscoreLongJmp(bool Val) { 894 UseUnderscoreLongJmp = Val; 895 } 896 897 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 898 /// specifies the register that llvm.savestack/llvm.restorestack should save 899 /// and restore. 900 void setStackPointerRegisterToSaveRestore(unsigned R) { 901 StackPointerRegisterToSaveRestore = R; 902 } 903 904 /// setExceptionPointerRegister - If set to a physical register, this sets 905 /// the register that receives the exception address on entry to a landing 906 /// pad. 907 void setExceptionPointerRegister(unsigned R) { 908 ExceptionPointerRegister = R; 909 } 910 911 /// setExceptionSelectorRegister - If set to a physical register, this sets 912 /// the register that receives the exception typeid on entry to a landing 913 /// pad. 914 void setExceptionSelectorRegister(unsigned R) { 915 ExceptionSelectorRegister = R; 916 } 917 918 /// SelectIsExpensive - Tells the code generator not to expand operations 919 /// into sequences that use the select operations if possible. 920 void setSelectIsExpensive() { SelectIsExpensive = true; } 921 922 /// setIntDivIsCheap - Tells the code generator that integer divide is 923 /// expensive, and if possible, should be replaced by an alternate sequence 924 /// of instructions not containing an integer divide. 925 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 926 927 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 928 /// srl/add/sra for a signed divide by power of two, and let the target handle 929 /// it. 930 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 931 932 /// addRegisterClass - Add the specified register class as an available 933 /// regclass for the specified value type. This indicates the selector can 934 /// handle values of that class natively. 935 void addRegisterClass(MVT VT, TargetRegisterClass *RC) { 936 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 937 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 938 RegClassForVT[VT.getSimpleVT()] = RC; 939 } 940 941 /// computeRegisterProperties - Once all of the register classes are added, 942 /// this allows us to compute derived properties we expose. 943 void computeRegisterProperties(); 944 945 /// setOperationAction - Indicate that the specified operation does not work 946 /// with the specified type and indicate what to do about it. 947 void setOperationAction(unsigned Op, MVT::SimpleValueType VT, 948 LegalizeAction Action) { 949 unsigned I = (unsigned)VT; 950 unsigned J = I & 31; 951 I = I >> 5; 952 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2)); 953 OpActions[I][Op] |= (uint64_t)Action << (J*2); 954 } 955 956 /// setLoadExtAction - Indicate that the specified load with extension does 957 /// not work with the with specified type and indicate what to do about it. 958 void setLoadExtAction(unsigned ExtType, MVT::SimpleValueType VT, 959 LegalizeAction Action) { 960 assert((unsigned)VT < sizeof(LoadExtActions[0])*4 && 961 ExtType < array_lengthof(LoadExtActions) && 962 "Table isn't big enough!"); 963 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 964 LoadExtActions[ExtType] |= (uint64_t)Action << VT*2; 965 } 966 967 /// setTruncStoreAction - Indicate that the specified truncating store does 968 /// not work with the with specified type and indicate what to do about it. 969 void setTruncStoreAction(MVT::SimpleValueType ValVT, 970 MVT::SimpleValueType MemVT, 971 LegalizeAction Action) { 972 assert((unsigned)ValVT < array_lengthof(TruncStoreActions) && 973 (unsigned)MemVT < sizeof(TruncStoreActions[0])*4 && 974 "Table isn't big enough!"); 975 TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2); 976 TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2; 977 } 978 979 /// setIndexedLoadAction - Indicate that the specified indexed load does or 980 /// does not work with the with specified type and indicate what to do abort 981 /// it. NOTE: All indexed mode loads are initialized to Expand in 982 /// TargetLowering.cpp 983 void setIndexedLoadAction(unsigned IdxMode, MVT::SimpleValueType VT, 984 LegalizeAction Action) { 985 assert((unsigned)VT < MVT::LAST_VALUETYPE && 986 IdxMode < array_lengthof(IndexedModeActions[0][0]) && 987 "Table isn't big enough!"); 988 IndexedModeActions[(unsigned)VT][0][IdxMode] = (uint8_t)Action; 989 } 990 991 /// setIndexedStoreAction - Indicate that the specified indexed store does or 992 /// does not work with the with specified type and indicate what to do about 993 /// it. NOTE: All indexed mode stores are initialized to Expand in 994 /// TargetLowering.cpp 995 void setIndexedStoreAction(unsigned IdxMode, MVT::SimpleValueType VT, 996 LegalizeAction Action) { 997 assert((unsigned)VT < MVT::LAST_VALUETYPE && 998 IdxMode < array_lengthof(IndexedModeActions[0][1] ) && 999 "Table isn't big enough!"); 1000 IndexedModeActions[(unsigned)VT][1][IdxMode] = (uint8_t)Action; 1001 } 1002 1003 /// setConvertAction - Indicate that the specified conversion does or does 1004 /// not work with the with specified type and indicate what to do about it. 1005 void setConvertAction(MVT::SimpleValueType FromVT, MVT::SimpleValueType ToVT, 1006 LegalizeAction Action) { 1007 assert((unsigned)FromVT < array_lengthof(ConvertActions) && 1008 (unsigned)ToVT < sizeof(ConvertActions[0])*4 && 1009 "Table isn't big enough!"); 1010 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2); 1011 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2; 1012 } 1013 1014 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1015 /// supported on the target and indicate what to do about it. 1016 void setCondCodeAction(ISD::CondCode CC, MVT::SimpleValueType VT, 1017 LegalizeAction Action) { 1018 assert((unsigned)VT < sizeof(CondCodeActions[0])*4 && 1019 (unsigned)CC < array_lengthof(CondCodeActions) && 1020 "Table isn't big enough!"); 1021 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT*2); 1022 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT*2; 1023 } 1024 1025 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1026 /// promotion code defaults to trying a larger integer/fp until it can find 1027 /// one that works. If that default is insufficient, this method can be used 1028 /// by the target to override the default. 1029 void AddPromotedToType(unsigned Opc, MVT::SimpleValueType OrigVT, 1030 MVT::SimpleValueType DestVT) { 1031 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 1032 } 1033 1034 /// addLegalFPImmediate - Indicate that this target can instruction select 1035 /// the specified FP immediate natively. 1036 void addLegalFPImmediate(const APFloat& Imm) { 1037 LegalFPImmediates.push_back(Imm); 1038 } 1039 1040 /// setTargetDAGCombine - Targets should invoke this method for each target 1041 /// independent node that they want to provide a custom DAG combiner for by 1042 /// implementing the PerformDAGCombine virtual method. 1043 void setTargetDAGCombine(ISD::NodeType NT) { 1044 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1045 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1046 } 1047 1048 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1049 /// bytes); default is 200 1050 void setJumpBufSize(unsigned Size) { 1051 JumpBufSize = Size; 1052 } 1053 1054 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1055 /// alignment (in bytes); default is 0 1056 void setJumpBufAlignment(unsigned Align) { 1057 JumpBufAlignment = Align; 1058 } 1059 1060 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1061 /// limit (in number of instructions); default is 2. 1062 void setIfCvtBlockSizeLimit(unsigned Limit) { 1063 IfCvtBlockSizeLimit = Limit; 1064 } 1065 1066 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1067 /// of instructions) to be considered for code duplication during 1068 /// if-conversion; default is 2. 1069 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1070 IfCvtDupBlockSizeLimit = Limit; 1071 } 1072 1073 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1074 /// alignment is zero, it means the target does not care about loop alignment. 1075 void setPrefLoopAlignment(unsigned Align) { 1076 PrefLoopAlignment = Align; 1077 } 1078 1079public: 1080 1081 virtual const TargetSubtarget *getSubtarget() { 1082 assert(0 && "Not Implemented"); 1083 return NULL; // this is here to silence compiler errors 1084 } 1085 1086 //===--------------------------------------------------------------------===// 1087 // Lowering methods - These methods must be implemented by targets so that 1088 // the SelectionDAGLowering code knows how to lower these. 1089 // 1090 1091 /// LowerFormalArguments - This hook must be implemented to lower the 1092 /// incoming (formal) arguments, described by the Ins array, into the 1093 /// specified DAG. The implementation should fill in the InVals array 1094 /// with legal-type argument values, and return the resulting token 1095 /// chain value. 1096 /// 1097 virtual SDValue 1098 LowerFormalArguments(SDValue Chain, 1099 unsigned CallConv, bool isVarArg, 1100 const SmallVectorImpl<ISD::InputArg> &Ins, 1101 DebugLoc dl, SelectionDAG &DAG, 1102 SmallVectorImpl<SDValue> &InVals) { 1103 assert(0 && "Not Implemented"); 1104 return SDValue(); // this is here to silence compiler errors 1105 } 1106 1107 /// LowerCallTo - This function lowers an abstract call to a function into an 1108 /// actual call. This returns a pair of operands. The first element is the 1109 /// return value for the function (if RetTy is not VoidTy). The second 1110 /// element is the outgoing token chain. It calls LowerCall to do the actual 1111 /// lowering. 1112 struct ArgListEntry { 1113 SDValue Node; 1114 const Type* Ty; 1115 bool isSExt : 1; 1116 bool isZExt : 1; 1117 bool isInReg : 1; 1118 bool isSRet : 1; 1119 bool isNest : 1; 1120 bool isByVal : 1; 1121 uint16_t Alignment; 1122 1123 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1124 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1125 }; 1126 typedef std::vector<ArgListEntry> ArgListTy; 1127 std::pair<SDValue, SDValue> 1128 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1129 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1130 unsigned CallConv, bool isTailCall, bool isReturnValueUsed, 1131 SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl); 1132 1133 /// LowerCall - This hook must be implemented to lower calls into the 1134 /// the specified DAG. The outgoing arguments to the call are described 1135 /// by the Outs array, and the values to be returned by the call are 1136 /// described by the Ins array. The implementation should fill in the 1137 /// InVals array with legal-type return values from the call, and return 1138 /// the resulting token chain value. 1139 /// 1140 /// The isTailCall flag here is normative. If it is true, the 1141 /// implementation must emit a tail call. The 1142 /// IsEligibleForTailCallOptimization hook should be used to catch 1143 /// cases that cannot be handled. 1144 /// 1145 virtual SDValue 1146 LowerCall(SDValue Chain, SDValue Callee, 1147 unsigned CallConv, bool isVarArg, bool isTailCall, 1148 const SmallVectorImpl<ISD::OutputArg> &Outs, 1149 const SmallVectorImpl<ISD::InputArg> &Ins, 1150 DebugLoc dl, SelectionDAG &DAG, 1151 SmallVectorImpl<SDValue> &InVals) { 1152 assert(0 && "Not Implemented"); 1153 return SDValue(); // this is here to silence compiler errors 1154 } 1155 1156 /// LowerReturn - This hook must be implemented to lower outgoing 1157 /// return values, described by the Outs array, into the specified 1158 /// DAG. The implementation should return the resulting token chain 1159 /// value. 1160 /// 1161 virtual SDValue 1162 LowerReturn(SDValue Chain, unsigned CallConv, bool isVarArg, 1163 const SmallVectorImpl<ISD::OutputArg> &Outs, 1164 DebugLoc dl, SelectionDAG &DAG) { 1165 assert(0 && "Not Implemented"); 1166 return SDValue(); // this is here to silence compiler errors 1167 } 1168 1169 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1170 /// memcpy. This can be used by targets to provide code sequences for cases 1171 /// that don't fit the target's parameters for simple loads/stores and can be 1172 /// more efficient than using a library call. This function can return a null 1173 /// SDValue if the target declines to use custom code and a different 1174 /// lowering strategy should be used. 1175 /// 1176 /// If AlwaysInline is true, the size is constant and the target should not 1177 /// emit any calls and is strongly encouraged to attempt to emit inline code 1178 /// even if it is beyond the usual threshold because this intrinsic is being 1179 /// expanded in a place where calls are not feasible (e.g. within the prologue 1180 /// for another call). If the target chooses to decline an AlwaysInline 1181 /// request here, legalize will resort to using simple loads and stores. 1182 virtual SDValue 1183 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1184 SDValue Chain, 1185 SDValue Op1, SDValue Op2, 1186 SDValue Op3, unsigned Align, 1187 bool AlwaysInline, 1188 const Value *DstSV, uint64_t DstOff, 1189 const Value *SrcSV, uint64_t SrcOff) { 1190 return SDValue(); 1191 } 1192 1193 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1194 /// memmove. This can be used by targets to provide code sequences for cases 1195 /// that don't fit the target's parameters for simple loads/stores and can be 1196 /// more efficient than using a library call. This function can return a null 1197 /// SDValue if the target declines to use custom code and a different 1198 /// lowering strategy should be used. 1199 virtual SDValue 1200 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, 1201 SDValue Chain, 1202 SDValue Op1, SDValue Op2, 1203 SDValue Op3, unsigned Align, 1204 const Value *DstSV, uint64_t DstOff, 1205 const Value *SrcSV, uint64_t SrcOff) { 1206 return SDValue(); 1207 } 1208 1209 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1210 /// memset. This can be used by targets to provide code sequences for cases 1211 /// that don't fit the target's parameters for simple stores and can be more 1212 /// efficient than using a library call. This function can return a null 1213 /// SDValue if the target declines to use custom code and a different 1214 /// lowering strategy should be used. 1215 virtual SDValue 1216 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 1217 SDValue Chain, 1218 SDValue Op1, SDValue Op2, 1219 SDValue Op3, unsigned Align, 1220 const Value *DstSV, uint64_t DstOff) { 1221 return SDValue(); 1222 } 1223 1224 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1225 /// to legalize nodes with an illegal operand type but legal result types. 1226 /// It replaces the LowerOperation callback in the type Legalizer. 1227 /// The reason we can not do away with LowerOperation entirely is that 1228 /// LegalizeDAG isn't yet ready to use this callback. 1229 /// TODO: Consider merging with ReplaceNodeResults. 1230 1231 /// The target places new result values for the node in Results (their number 1232 /// and types must exactly match those of the original return values of 1233 /// the node), or leaves Results empty, which indicates that the node is not 1234 /// to be custom lowered after all. 1235 /// The default implementation calls LowerOperation. 1236 virtual void LowerOperationWrapper(SDNode *N, 1237 SmallVectorImpl<SDValue> &Results, 1238 SelectionDAG &DAG); 1239 1240 /// LowerOperation - This callback is invoked for operations that are 1241 /// unsupported by the target, which are registered to use 'custom' lowering, 1242 /// and whose defined values are all legal. 1243 /// If the target has no operations that require custom lowering, it need not 1244 /// implement this. The default implementation of this aborts. 1245 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1246 1247 /// ReplaceNodeResults - This callback is invoked when a node result type is 1248 /// illegal for the target, and the operation was registered to use 'custom' 1249 /// lowering for that result type. The target places new result values for 1250 /// the node in Results (their number and types must exactly match those of 1251 /// the original return values of the node), or leaves Results empty, which 1252 /// indicates that the node is not to be custom lowered after all. 1253 /// 1254 /// If the target has no operations that require custom lowering, it need not 1255 /// implement this. The default implementation aborts. 1256 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1257 SelectionDAG &DAG) { 1258 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1259 } 1260 1261 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1262 /// tail call optimization. Targets which want to do tail call optimization 1263 /// should override this function. 1264 virtual bool 1265 IsEligibleForTailCallOptimization(SDValue Callee, 1266 unsigned CalleeCC, 1267 bool isVarArg, 1268 const SmallVectorImpl<ISD::InputArg> &Ins, 1269 SelectionDAG& DAG) const { 1270 // Conservative default: no calls are eligible. 1271 return false; 1272 } 1273 1274 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if 1275 /// it exists. Skip a possible ISD::TokenFactor. 1276 static SDValue GetPossiblePreceedingTailCall(SDValue Chain, 1277 unsigned TailCallNodeOpCode) { 1278 if (Chain.getOpcode() == TailCallNodeOpCode) { 1279 return Chain; 1280 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1281 if (Chain.getNumOperands() && 1282 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode) 1283 return Chain.getOperand(0); 1284 } 1285 return Chain; 1286 } 1287 1288 /// getTargetNodeName() - This method returns the name of a target specific 1289 /// DAG node. 1290 virtual const char *getTargetNodeName(unsigned Opcode) const; 1291 1292 /// createFastISel - This method returns a target specific FastISel object, 1293 /// or null if the target does not support "fast" ISel. 1294 virtual FastISel * 1295 createFastISel(MachineFunction &, 1296 MachineModuleInfo *, DwarfWriter *, 1297 DenseMap<const Value *, unsigned> &, 1298 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1299 DenseMap<const AllocaInst *, int> & 1300#ifndef NDEBUG 1301 , SmallSet<Instruction*, 8> &CatchInfoLost 1302#endif 1303 ) { 1304 return 0; 1305 } 1306 1307 //===--------------------------------------------------------------------===// 1308 // Inline Asm Support hooks 1309 // 1310 1311 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1312 /// call to be explicit llvm code if it wants to. This is useful for 1313 /// turning simple inline asms into LLVM intrinsics, which gives the 1314 /// compiler more information about the behavior of the code. 1315 virtual bool ExpandInlineAsm(CallInst *CI) const { 1316 return false; 1317 } 1318 1319 enum ConstraintType { 1320 C_Register, // Constraint represents specific register(s). 1321 C_RegisterClass, // Constraint represents any of register(s) in class. 1322 C_Memory, // Memory constraint. 1323 C_Other, // Something else. 1324 C_Unknown // Unsupported constraint. 1325 }; 1326 1327 /// AsmOperandInfo - This contains information for each constraint that we are 1328 /// lowering. 1329 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1330 /// ConstraintCode - This contains the actual string for the code, like "m". 1331 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1332 /// most closely matches the operand. 1333 std::string ConstraintCode; 1334 1335 /// ConstraintType - Information about the constraint code, e.g. Register, 1336 /// RegisterClass, Memory, Other, Unknown. 1337 TargetLowering::ConstraintType ConstraintType; 1338 1339 /// CallOperandval - If this is the result output operand or a 1340 /// clobber, this is null, otherwise it is the incoming operand to the 1341 /// CallInst. This gets modified as the asm is processed. 1342 Value *CallOperandVal; 1343 1344 /// ConstraintVT - The ValueType for the operand value. 1345 MVT ConstraintVT; 1346 1347 /// isMatchingInputConstraint - Return true of this is an input operand that 1348 /// is a matching constraint like "4". 1349 bool isMatchingInputConstraint() const; 1350 1351 /// getMatchedOperand - If this is an input matching constraint, this method 1352 /// returns the output operand it matches. 1353 unsigned getMatchedOperand() const; 1354 1355 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1356 : InlineAsm::ConstraintInfo(info), 1357 ConstraintType(TargetLowering::C_Unknown), 1358 CallOperandVal(0), ConstraintVT(MVT::Other) { 1359 } 1360 }; 1361 1362 /// ComputeConstraintToUse - Determines the constraint code and constraint 1363 /// type to use for the specific AsmOperandInfo, setting 1364 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1365 /// being passed in is available, it can be passed in as Op, otherwise an 1366 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1367 /// constraint of the inline asm instruction being processed is 'm'. 1368 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1369 SDValue Op, 1370 bool hasMemory, 1371 SelectionDAG *DAG = 0) const; 1372 1373 /// getConstraintType - Given a constraint, return the type of constraint it 1374 /// is for this target. 1375 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1376 1377 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1378 /// return a list of registers that can be used to satisfy the constraint. 1379 /// This should only be used for C_RegisterClass constraints. 1380 virtual std::vector<unsigned> 1381 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1382 MVT VT) const; 1383 1384 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1385 /// {edx}), return the register number and the register class for the 1386 /// register. 1387 /// 1388 /// Given a register class constraint, like 'r', if this corresponds directly 1389 /// to an LLVM register class, return a register of 0 and the register class 1390 /// pointer. 1391 /// 1392 /// This should only be used for C_Register constraints. On error, 1393 /// this returns a register number of 0 and a null register class pointer.. 1394 virtual std::pair<unsigned, const TargetRegisterClass*> 1395 getRegForInlineAsmConstraint(const std::string &Constraint, 1396 MVT VT) const; 1397 1398 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1399 /// with another that has more specific requirements based on the type of the 1400 /// corresponding operand. This returns null if there is no replacement to 1401 /// make. 1402 virtual const char *LowerXConstraint(MVT ConstraintVT) const; 1403 1404 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1405 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1406 /// it means one of the asm constraint of the inline asm instruction being 1407 /// processed is 'm'. 1408 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1409 bool hasMemory, 1410 std::vector<SDValue> &Ops, 1411 SelectionDAG &DAG) const; 1412 1413 //===--------------------------------------------------------------------===// 1414 // Scheduler hooks 1415 // 1416 1417 // EmitInstrWithCustomInserter - This method should be implemented by targets 1418 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1419 // instructions are special in various ways, which require special support to 1420 // insert. The specified MachineInstr is created but not inserted into any 1421 // basic blocks, and the scheduler passes ownership of it to this method. 1422 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1423 MachineBasicBlock *MBB) const; 1424 1425 //===--------------------------------------------------------------------===// 1426 // Addressing mode description hooks (used by LSR etc). 1427 // 1428 1429 /// AddrMode - This represents an addressing mode of: 1430 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1431 /// If BaseGV is null, there is no BaseGV. 1432 /// If BaseOffs is zero, there is no base offset. 1433 /// If HasBaseReg is false, there is no base register. 1434 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1435 /// no scale. 1436 /// 1437 struct AddrMode { 1438 GlobalValue *BaseGV; 1439 int64_t BaseOffs; 1440 bool HasBaseReg; 1441 int64_t Scale; 1442 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1443 }; 1444 1445 /// isLegalAddressingMode - Return true if the addressing mode represented by 1446 /// AM is legal for this target, for a load/store of the specified type. 1447 /// The type may be VoidTy, in which case only return true if the addressing 1448 /// mode is legal for a load/store of any legal type. 1449 /// TODO: Handle pre/postinc as well. 1450 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1451 1452 /// isTruncateFree - Return true if it's free to truncate a value of 1453 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1454 /// register EAX to i16 by referencing its sub-register AX. 1455 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1456 return false; 1457 } 1458 1459 virtual bool isTruncateFree(MVT VT1, MVT VT2) const { 1460 return false; 1461 } 1462 1463 /// isZExtFree - Return true if any actual instruction that defines a 1464 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 1465 /// register. This does not necessarily include registers defined in 1466 /// unknown ways, such as incoming arguments, or copies from unknown 1467 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1468 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1469 /// all instructions that define 32-bit values implicit zero-extend the 1470 /// result out to 64 bits. 1471 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1472 return false; 1473 } 1474 1475 virtual bool isZExtFree(MVT VT1, MVT VT2) const { 1476 return false; 1477 } 1478 1479 /// isNarrowingProfitable - Return true if it's profitable to narrow 1480 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1481 /// from i32 to i8 but not from i32 to i16. 1482 virtual bool isNarrowingProfitable(MVT VT1, MVT VT2) const { 1483 return false; 1484 } 1485 1486 //===--------------------------------------------------------------------===// 1487 // Div utility functions 1488 // 1489 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1490 std::vector<SDNode*>* Created) const; 1491 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1492 std::vector<SDNode*>* Created) const; 1493 1494 1495 //===--------------------------------------------------------------------===// 1496 // Runtime Library hooks 1497 // 1498 1499 /// setLibcallName - Rename the default libcall routine name for the specified 1500 /// libcall. 1501 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1502 LibcallRoutineNames[Call] = Name; 1503 } 1504 1505 /// getLibcallName - Get the libcall routine name for the specified libcall. 1506 /// 1507 const char *getLibcallName(RTLIB::Libcall Call) const { 1508 return LibcallRoutineNames[Call]; 1509 } 1510 1511 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1512 /// result of the comparison libcall against zero. 1513 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1514 CmpLibcallCCs[Call] = CC; 1515 } 1516 1517 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1518 /// the comparison libcall against zero. 1519 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1520 return CmpLibcallCCs[Call]; 1521 } 1522 1523private: 1524 TargetMachine &TM; 1525 const TargetData *TD; 1526 TargetLoweringObjectFile &TLOF; 1527 1528 /// PointerTy - The type to use for pointers, usually i32 or i64. 1529 /// 1530 MVT::SimpleValueType PointerTy; 1531 1532 /// IsLittleEndian - True if this is a little endian target. 1533 /// 1534 bool IsLittleEndian; 1535 1536 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1537 /// 1538 bool UsesGlobalOffsetTable; 1539 1540 /// SelectIsExpensive - Tells the code generator not to expand operations 1541 /// into sequences that use the select operations if possible. 1542 bool SelectIsExpensive; 1543 1544 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1545 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1546 /// a real cost model is in place. If we ever optimize for size, this will be 1547 /// set to true unconditionally. 1548 bool IntDivIsCheap; 1549 1550 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1551 /// srl/add/sra for a signed divide by power of two, and let the target handle 1552 /// it. 1553 bool Pow2DivIsCheap; 1554 1555 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1556 /// llvm.setjmp. Defaults to false. 1557 bool UseUnderscoreSetJmp; 1558 1559 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1560 /// llvm.longjmp. Defaults to false. 1561 bool UseUnderscoreLongJmp; 1562 1563 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1564 /// PointerTy is. 1565 MVT::SimpleValueType ShiftAmountTy; 1566 1567 /// BooleanContents - Information about the contents of the high-bits in 1568 /// boolean values held in a type wider than i1. See getBooleanContents. 1569 BooleanContent BooleanContents; 1570 1571 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1572 /// total cycles or lowest register usage. 1573 SchedPreference SchedPreferenceInfo; 1574 1575 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1576 unsigned JumpBufSize; 1577 1578 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1579 /// buffers 1580 unsigned JumpBufAlignment; 1581 1582 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1583 /// if-converted. 1584 unsigned IfCvtBlockSizeLimit; 1585 1586 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1587 /// duplicated during if-conversion. 1588 unsigned IfCvtDupBlockSizeLimit; 1589 1590 /// PrefLoopAlignment - The perferred loop alignment. 1591 /// 1592 unsigned PrefLoopAlignment; 1593 1594 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1595 /// specifies the register that llvm.savestack/llvm.restorestack should save 1596 /// and restore. 1597 unsigned StackPointerRegisterToSaveRestore; 1598 1599 /// ExceptionPointerRegister - If set to a physical register, this specifies 1600 /// the register that receives the exception address on entry to a landing 1601 /// pad. 1602 unsigned ExceptionPointerRegister; 1603 1604 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1605 /// the register that receives the exception typeid on entry to a landing 1606 /// pad. 1607 unsigned ExceptionSelectorRegister; 1608 1609 /// RegClassForVT - This indicates the default register class to use for 1610 /// each ValueType the target supports natively. 1611 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1612 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1613 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1614 1615 /// TransformToType - For any value types we are promoting or expanding, this 1616 /// contains the value type that we are changing to. For Expanded types, this 1617 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1618 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1619 /// by the system, this holds the same type (e.g. i32 -> i32). 1620 MVT TransformToType[MVT::LAST_VALUETYPE]; 1621 1622 /// OpActions - For each operation and each value type, keep a LegalizeAction 1623 /// that indicates how instruction selection should deal with the operation. 1624 /// Most operations are Legal (aka, supported natively by the target), but 1625 /// operations that are not should be described. Note that operations on 1626 /// non-legal value types are not described here. 1627 /// This array is accessed using VT.getSimpleVT(), so it is subject to 1628 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits. 1629 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END]; 1630 1631 /// LoadExtActions - For each load of load extension type and each value type, 1632 /// keep a LegalizeAction that indicates how instruction selection should deal 1633 /// with the load. 1634 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1635 1636 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1637 /// indicates how instruction selection should deal with the store. 1638 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1639 1640 /// IndexedModeActions - For each indexed mode and each value type, 1641 /// keep a pair of LegalizeAction that indicates how instruction 1642 /// selection should deal with the load / store. The first 1643 /// dimension is now the value_type for the reference. The second 1644 /// dimension is the load [0] vs. store[1]. The third dimension 1645 /// represents the various modes for load store. 1646 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE]; 1647 1648 /// ConvertActions - For each conversion from source type to destination type, 1649 /// keep a LegalizeAction that indicates how instruction selection should 1650 /// deal with the conversion. 1651 /// Currently, this is used only for floating->floating conversions 1652 /// (FP_EXTEND and FP_ROUND). 1653 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1654 1655 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1656 /// LegalizeAction that indicates how instruction selection should 1657 /// deal with the condition code. 1658 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1659 1660 ValueTypeActionImpl ValueTypeActions; 1661 1662 std::vector<APFloat> LegalFPImmediates; 1663 1664 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses; 1665 1666 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1667 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1668 /// which sets a bit in this array. 1669 unsigned char 1670 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1671 1672 /// PromoteToType - For operations that must be promoted to a specific type, 1673 /// this holds the destination type. This map should be sparse, so don't hold 1674 /// it as an array. 1675 /// 1676 /// Targets add entries to this map with AddPromotedToType(..), clients access 1677 /// this with getTypeToPromoteTo(..). 1678 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1679 PromoteToType; 1680 1681 /// LibcallRoutineNames - Stores the name each libcall. 1682 /// 1683 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1684 1685 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1686 /// of each of the comparison libcall against zero. 1687 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1688 1689protected: 1690 /// When lowering \@llvm.memset this field specifies the maximum number of 1691 /// store operations that may be substituted for the call to memset. Targets 1692 /// must set this value based on the cost threshold for that target. Targets 1693 /// should assume that the memset will be done using as many of the largest 1694 /// store operations first, followed by smaller ones, if necessary, per 1695 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1696 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1697 /// store. This only applies to setting a constant array of a constant size. 1698 /// @brief Specify maximum number of store instructions per memset call. 1699 unsigned maxStoresPerMemset; 1700 1701 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1702 /// store operations that may be substituted for a call to memcpy. Targets 1703 /// must set this value based on the cost threshold for that target. Targets 1704 /// should assume that the memcpy will be done using as many of the largest 1705 /// store operations first, followed by smaller ones, if necessary, per 1706 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1707 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1708 /// and one 1-byte store. This only applies to copying a constant array of 1709 /// constant size. 1710 /// @brief Specify maximum bytes of store instructions per memcpy call. 1711 unsigned maxStoresPerMemcpy; 1712 1713 /// When lowering \@llvm.memmove this field specifies the maximum number of 1714 /// store instructions that may be substituted for a call to memmove. Targets 1715 /// must set this value based on the cost threshold for that target. Targets 1716 /// should assume that the memmove will be done using as many of the largest 1717 /// store operations first, followed by smaller ones, if necessary, per 1718 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1719 /// with 8-bit alignment would result in nine 1-byte stores. This only 1720 /// applies to copying a constant array of constant size. 1721 /// @brief Specify maximum bytes of store instructions per memmove call. 1722 unsigned maxStoresPerMemmove; 1723 1724 /// This field specifies whether the target machine permits unaligned memory 1725 /// accesses. This is used, for example, to determine the size of store 1726 /// operations when copying small arrays and other similar tasks. 1727 /// @brief Indicate whether the target permits unaligned memory accesses. 1728 bool allowUnalignedMemoryAccesses; 1729 1730 /// This field specifies whether the target can benefit from code placement 1731 /// optimization. 1732 bool benefitFromCodePlacementOpt; 1733}; 1734} // end llvm namespace 1735 1736#endif 1737