TargetLowering.h revision d70f57b254114841892425a40944268d38ae0bcd
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Attributes.h" 28#include "llvm/CodeGen/SelectionDAGNodes.h" 29#include "llvm/CodeGen/RuntimeLibcalls.h" 30#include "llvm/ADT/APFloat.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/SmallSet.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/STLExtras.h" 35#include "llvm/Support/DebugLoc.h" 36#include "llvm/Target/TargetCallingConv.h" 37#include "llvm/Target/TargetMachine.h" 38#include <climits> 39#include <map> 40#include <vector> 41 42namespace llvm { 43 class AllocaInst; 44 class CallInst; 45 class Function; 46 class FastISel; 47 class FunctionLoweringInfo; 48 class MachineBasicBlock; 49 class MachineFunction; 50 class MachineFrameInfo; 51 class MachineInstr; 52 class MachineJumpTableInfo; 53 class MCContext; 54 class MCExpr; 55 class SDNode; 56 class SDValue; 57 class SelectionDAG; 58 class TargetData; 59 class TargetMachine; 60 class TargetRegisterClass; 61 class TargetLoweringObjectFile; 62 class Value; 63 64 // FIXME: should this be here? 65 namespace TLSModel { 66 enum Model { 67 GeneralDynamic, 68 LocalDynamic, 69 InitialExec, 70 LocalExec 71 }; 72 } 73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 74 75 76//===----------------------------------------------------------------------===// 77/// TargetLowering - This class defines information used to lower LLVM code to 78/// legal SelectionDAG operators that the target instruction selector can accept 79/// natively. 80/// 81/// This class also defines callbacks that targets must implement to lower 82/// target-specific constructs to SelectionDAG operators. 83/// 84class TargetLowering { 85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 87public: 88 /// LegalizeAction - This enum indicates whether operations are valid for a 89 /// target, and if not, what action should be used to make them valid. 90 enum LegalizeAction { 91 Legal, // The target natively supports this operation. 92 Promote, // This operation should be executed in a larger type. 93 Expand, // Try to expand this to other ops, otherwise use a libcall. 94 Custom // Use the LowerOperation hook to implement custom lowering. 95 }; 96 97 enum BooleanContent { // How the target represents true/false values. 98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 99 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 101 }; 102 103 /// NOTE: The constructor takes ownership of TLOF. 104 explicit TargetLowering(const TargetMachine &TM, 105 const TargetLoweringObjectFile *TLOF); 106 virtual ~TargetLowering(); 107 108 const TargetMachine &getTargetMachine() const { return TM; } 109 const TargetData *getTargetData() const { return TD; } 110 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 111 112 bool isBigEndian() const { return !IsLittleEndian; } 113 bool isLittleEndian() const { return IsLittleEndian; } 114 MVT getPointerTy() const { return PointerTy; } 115 MVT getShiftAmountTy() const { return ShiftAmountTy; } 116 117 /// isSelectExpensive - Return true if the select operation is expensive for 118 /// this target. 119 bool isSelectExpensive() const { return SelectIsExpensive; } 120 121 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 122 /// a sequence of several shifts, adds, and multiplies for this target. 123 bool isIntDivCheap() const { return IntDivIsCheap; } 124 125 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 126 /// srl/add/sra. 127 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 128 129 /// getSetCCResultType - Return the ValueType of the result of SETCC 130 /// operations. Also used to obtain the target's preferred type for 131 /// the condition operand of SELECT and BRCOND nodes. In the case of 132 /// BRCOND the argument passed is MVT::Other since there are no other 133 /// operands to get a type hint from. 134 virtual 135 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 136 137 /// getCmpLibcallReturnType - Return the ValueType for comparison 138 /// libcalls. Comparions libcalls include floating point comparion calls, 139 /// and Ordered/Unordered check calls on floating point numbers. 140 virtual 141 MVT::SimpleValueType getCmpLibcallReturnType() const; 142 143 /// getBooleanContents - For targets without i1 registers, this gives the 144 /// nature of the high-bits of boolean values held in types wider than i1. 145 /// "Boolean values" are special true/false values produced by nodes like 146 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 147 /// Not to be confused with general values promoted from i1. 148 BooleanContent getBooleanContents() const { return BooleanContents;} 149 150 /// getSchedulingPreference - Return target scheduling preference. 151 Sched::Preference getSchedulingPreference() const { 152 return SchedPreferenceInfo; 153 } 154 155 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 156 /// different scheduling heuristics for different nodes. This function returns 157 /// the preference (or none) for the given node. 158 virtual Sched::Preference getSchedulingPreference(SDNode *N) const { 159 return Sched::None; 160 } 161 162 /// getRegClassFor - Return the register class that should be used for the 163 /// specified value type. 164 virtual TargetRegisterClass *getRegClassFor(EVT VT) const { 165 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 166 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 167 assert(RC && "This value type is not natively supported!"); 168 return RC; 169 } 170 171 /// getRepRegClassFor - Return the 'representative' register class for the 172 /// specified value type. The 'representative' register class is the largest 173 /// legal super-reg register class for the register class of the value type. 174 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 175 /// while the rep register class is GR64 on x86_64. 176 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { 177 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 178 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; 179 assert(RC && "This value type is not natively supported!"); 180 return RC; 181 } 182 183 /// isTypeLegal - Return true if the target has native support for the 184 /// specified value type. This means that it has a register that directly 185 /// holds it without promotions or expansions. 186 bool isTypeLegal(EVT VT) const { 187 assert(!VT.isSimple() || 188 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 189 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 190 } 191 192 /// isTypeSynthesizable - Return true if it's OK for the compiler to create 193 /// new operations of this type. All Legal types are synthesizable except 194 /// MMX vector types on X86. Non-Legal types are not synthesizable. 195 bool isTypeSynthesizable(EVT VT) const { 196 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy]; 197 } 198 199 class ValueTypeActionImpl { 200 /// ValueTypeActions - For each value type, keep a LegalizeAction enum 201 /// that indicates how instruction selection should deal with the type. 202 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 203 public: 204 ValueTypeActionImpl() { 205 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 206 } 207 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 208 if (VT.isExtended()) { 209 if (VT.isVector()) { 210 return VT.isPow2VectorType() ? Expand : Promote; 211 } 212 if (VT.isInteger()) 213 // First promote to a power-of-two size, then expand if necessary. 214 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote; 215 assert(0 && "Unsupported extended type!"); 216 return Legal; 217 } 218 unsigned I = VT.getSimpleVT().SimpleTy; 219 return (LegalizeAction)ValueTypeActions[I]; 220 } 221 void setTypeAction(EVT VT, LegalizeAction Action) { 222 unsigned I = VT.getSimpleVT().SimpleTy; 223 ValueTypeActions[I] = Action; 224 } 225 }; 226 227 const ValueTypeActionImpl &getValueTypeActions() const { 228 return ValueTypeActions; 229 } 230 231 /// getTypeAction - Return how we should legalize values of this type, either 232 /// it is already legal (return 'Legal') or we need to promote it to a larger 233 /// type (return 'Promote'), or we need to expand it into multiple registers 234 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 235 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 236 return ValueTypeActions.getTypeAction(Context, VT); 237 } 238 239 /// getTypeToTransformTo - For types supported by the target, this is an 240 /// identity function. For types that must be promoted to larger types, this 241 /// returns the larger type to promote to. For integer types that are larger 242 /// than the largest integer register, this contains one step in the expansion 243 /// to get to the smaller register. For illegal floating point types, this 244 /// returns the integer type to transform to. 245 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 246 if (VT.isSimple()) { 247 assert((unsigned)VT.getSimpleVT().SimpleTy < 248 array_lengthof(TransformToType)); 249 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 250 assert(getTypeAction(Context, NVT) != Promote && 251 "Promote may not follow Expand or Promote"); 252 return NVT; 253 } 254 255 if (VT.isVector()) { 256 EVT NVT = VT.getPow2VectorType(Context); 257 if (NVT == VT) { 258 // Vector length is a power of 2 - split to half the size. 259 unsigned NumElts = VT.getVectorNumElements(); 260 EVT EltVT = VT.getVectorElementType(); 261 return (NumElts == 1) ? 262 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 263 } 264 // Promote to a power of two size, avoiding multi-step promotion. 265 return getTypeAction(Context, NVT) == Promote ? 266 getTypeToTransformTo(Context, NVT) : NVT; 267 } else if (VT.isInteger()) { 268 EVT NVT = VT.getRoundIntegerType(Context); 269 if (NVT == VT) 270 // Size is a power of two - expand to half the size. 271 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 272 else 273 // Promote to a power of two size, avoiding multi-step promotion. 274 return getTypeAction(Context, NVT) == Promote ? 275 getTypeToTransformTo(Context, NVT) : NVT; 276 } 277 assert(0 && "Unsupported extended type!"); 278 return MVT(MVT::Other); // Not reached 279 } 280 281 /// getTypeToExpandTo - For types supported by the target, this is an 282 /// identity function. For types that must be expanded (i.e. integer types 283 /// that are larger than the largest integer register or illegal floating 284 /// point types), this returns the largest legal type it will be expanded to. 285 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 286 assert(!VT.isVector()); 287 while (true) { 288 switch (getTypeAction(Context, VT)) { 289 case Legal: 290 return VT; 291 case Expand: 292 VT = getTypeToTransformTo(Context, VT); 293 break; 294 default: 295 assert(false && "Type is not legal nor is it to be expanded!"); 296 return VT; 297 } 298 } 299 return VT; 300 } 301 302 /// getVectorTypeBreakdown - Vector types are broken down into some number of 303 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 304 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 305 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 306 /// 307 /// This method returns the number of registers needed, and the VT for each 308 /// register. It also returns the VT and quantity of the intermediate values 309 /// before they are promoted/expanded. 310 /// 311 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 312 EVT &IntermediateVT, 313 unsigned &NumIntermediates, 314 EVT &RegisterVT) const; 315 316 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 317 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 318 /// this is the case, it returns true and store the intrinsic 319 /// information into the IntrinsicInfo that was passed to the function. 320 struct IntrinsicInfo { 321 unsigned opc; // target opcode 322 EVT memVT; // memory VT 323 const Value* ptrVal; // value representing memory location 324 int offset; // offset off of ptrVal 325 unsigned align; // alignment 326 bool vol; // is volatile? 327 bool readMem; // reads memory? 328 bool writeMem; // writes memory? 329 }; 330 331 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 332 const CallInst &I, unsigned Intrinsic) const { 333 return false; 334 } 335 336 /// isFPImmLegal - Returns true if the target can instruction select the 337 /// specified FP immediate natively. If false, the legalizer will materialize 338 /// the FP immediate as a load from a constant pool. 339 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const { 340 return false; 341 } 342 343 /// isShuffleMaskLegal - Targets can use this to indicate that they only 344 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 345 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 346 /// are assumed to be legal. 347 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 348 EVT VT) const { 349 return true; 350 } 351 352 /// canOpTrap - Returns true if the operation can trap for the value type. 353 /// VT must be a legal type. By default, we optimistically assume most 354 /// operations don't trap except for divide and remainder. 355 virtual bool canOpTrap(unsigned Op, EVT VT) const; 356 357 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 358 /// used by Targets can use this to indicate if there is a suitable 359 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 360 /// pool entry. 361 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 362 EVT VT) const { 363 return false; 364 } 365 366 /// getOperationAction - Return how this operation should be treated: either 367 /// it is legal, needs to be promoted to a larger size, needs to be 368 /// expanded to some other code sequence, or the target has a custom expander 369 /// for it. 370 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 371 if (VT.isExtended()) return Expand; 372 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 373 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 374 return (LegalizeAction)OpActions[I][Op]; 375 } 376 377 /// isOperationLegalOrCustom - Return true if the specified operation is 378 /// legal on this target or can be made legal with custom lowering. This 379 /// is used to help guide high-level lowering decisions. 380 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 381 return (VT == MVT::Other || isTypeLegal(VT)) && 382 (getOperationAction(Op, VT) == Legal || 383 getOperationAction(Op, VT) == Custom); 384 } 385 386 /// isOperationLegal - Return true if the specified operation is legal on this 387 /// target. 388 bool isOperationLegal(unsigned Op, EVT VT) const { 389 return (VT == MVT::Other || isTypeLegal(VT)) && 390 getOperationAction(Op, VT) == Legal; 391 } 392 393 /// getLoadExtAction - Return how this load with extension should be treated: 394 /// either it is legal, needs to be promoted to a larger size, needs to be 395 /// expanded to some other code sequence, or the target has a custom expander 396 /// for it. 397 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { 398 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 399 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 400 "Table isn't big enough!"); 401 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 402 } 403 404 /// isLoadExtLegal - Return true if the specified load with extension is legal 405 /// on this target. 406 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 407 return VT.isSimple() && 408 (getLoadExtAction(ExtType, VT) == Legal || 409 getLoadExtAction(ExtType, VT) == Custom); 410 } 411 412 /// getTruncStoreAction - Return how this store with truncation should be 413 /// treated: either it is legal, needs to be promoted to a larger size, needs 414 /// to be expanded to some other code sequence, or the target has a custom 415 /// expander for it. 416 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 417 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 418 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 419 "Table isn't big enough!"); 420 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] 421 [MemVT.getSimpleVT().SimpleTy]; 422 } 423 424 /// isTruncStoreLegal - Return true if the specified store with truncation is 425 /// legal on this target. 426 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 427 return isTypeLegal(ValVT) && MemVT.isSimple() && 428 (getTruncStoreAction(ValVT, MemVT) == Legal || 429 getTruncStoreAction(ValVT, MemVT) == Custom); 430 } 431 432 /// getIndexedLoadAction - Return how the indexed load should be treated: 433 /// either it is legal, needs to be promoted to a larger size, needs to be 434 /// expanded to some other code sequence, or the target has a custom expander 435 /// for it. 436 LegalizeAction 437 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 438 assert( IdxMode < ISD::LAST_INDEXED_MODE && 439 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 440 "Table isn't big enough!"); 441 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 442 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 443 } 444 445 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 446 /// on this target. 447 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 448 return VT.isSimple() && 449 (getIndexedLoadAction(IdxMode, VT) == Legal || 450 getIndexedLoadAction(IdxMode, VT) == Custom); 451 } 452 453 /// getIndexedStoreAction - Return how the indexed store should be treated: 454 /// either it is legal, needs to be promoted to a larger size, needs to be 455 /// expanded to some other code sequence, or the target has a custom expander 456 /// for it. 457 LegalizeAction 458 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 459 assert( IdxMode < ISD::LAST_INDEXED_MODE && 460 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 461 "Table isn't big enough!"); 462 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 463 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 464 } 465 466 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 467 /// on this target. 468 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 469 return VT.isSimple() && 470 (getIndexedStoreAction(IdxMode, VT) == Legal || 471 getIndexedStoreAction(IdxMode, VT) == Custom); 472 } 473 474 /// getCondCodeAction - Return how the condition code should be treated: 475 /// either it is legal, needs to be expanded to some other code sequence, 476 /// or the target has a custom expander for it. 477 LegalizeAction 478 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 479 assert((unsigned)CC < array_lengthof(CondCodeActions) && 480 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 481 "Table isn't big enough!"); 482 LegalizeAction Action = (LegalizeAction) 483 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 484 assert(Action != Promote && "Can't promote condition code!"); 485 return Action; 486 } 487 488 /// isCondCodeLegal - Return true if the specified condition code is legal 489 /// on this target. 490 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 491 return getCondCodeAction(CC, VT) == Legal || 492 getCondCodeAction(CC, VT) == Custom; 493 } 494 495 496 /// getTypeToPromoteTo - If the action for this operation is to promote, this 497 /// method returns the ValueType to promote to. 498 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 499 assert(getOperationAction(Op, VT) == Promote && 500 "This operation isn't promoted!"); 501 502 // See if this has an explicit type specified. 503 std::map<std::pair<unsigned, MVT::SimpleValueType>, 504 MVT::SimpleValueType>::const_iterator PTTI = 505 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 506 if (PTTI != PromoteToType.end()) return PTTI->second; 507 508 assert((VT.isInteger() || VT.isFloatingPoint()) && 509 "Cannot autopromote this type, add it with AddPromotedToType."); 510 511 EVT NVT = VT; 512 do { 513 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 514 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 515 "Didn't find type to promote to!"); 516 } while (!isTypeLegal(NVT) || 517 getOperationAction(Op, NVT) == Promote); 518 return NVT; 519 } 520 521 /// getValueType - Return the EVT corresponding to this LLVM type. 522 /// This is fixed by the LLVM operations except for the pointer size. If 523 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 524 /// counterpart (e.g. structs), otherwise it will assert. 525 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 526 EVT VT = EVT::getEVT(Ty, AllowUnknown); 527 return VT == MVT::iPTR ? PointerTy : VT; 528 } 529 530 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 531 /// function arguments in the caller parameter area. This is the actual 532 /// alignment, not its logarithm. 533 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 534 535 /// getRegisterType - Return the type of registers that this ValueType will 536 /// eventually require. 537 EVT getRegisterType(MVT VT) const { 538 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 539 return RegisterTypeForVT[VT.SimpleTy]; 540 } 541 542 /// getRegisterType - Return the type of registers that this ValueType will 543 /// eventually require. 544 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 545 if (VT.isSimple()) { 546 assert((unsigned)VT.getSimpleVT().SimpleTy < 547 array_lengthof(RegisterTypeForVT)); 548 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 549 } 550 if (VT.isVector()) { 551 EVT VT1, RegisterVT; 552 unsigned NumIntermediates; 553 (void)getVectorTypeBreakdown(Context, VT, VT1, 554 NumIntermediates, RegisterVT); 555 return RegisterVT; 556 } 557 if (VT.isInteger()) { 558 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 559 } 560 assert(0 && "Unsupported extended type!"); 561 return EVT(MVT::Other); // Not reached 562 } 563 564 /// getNumRegisters - Return the number of registers that this ValueType will 565 /// eventually require. This is one for any types promoted to live in larger 566 /// registers, but may be more than one for types (like i64) that are split 567 /// into pieces. For types like i140, which are first promoted then expanded, 568 /// it is the number of registers needed to hold all the bits of the original 569 /// type. For an i140 on a 32 bit machine this means 5 registers. 570 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 571 if (VT.isSimple()) { 572 assert((unsigned)VT.getSimpleVT().SimpleTy < 573 array_lengthof(NumRegistersForVT)); 574 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 575 } 576 if (VT.isVector()) { 577 EVT VT1, VT2; 578 unsigned NumIntermediates; 579 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 580 } 581 if (VT.isInteger()) { 582 unsigned BitWidth = VT.getSizeInBits(); 583 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 584 return (BitWidth + RegWidth - 1) / RegWidth; 585 } 586 assert(0 && "Unsupported extended type!"); 587 return 0; // Not reached 588 } 589 590 /// ShouldShrinkFPConstant - If true, then instruction selection should 591 /// seek to shrink the FP constant of the specified type to a smaller type 592 /// in order to save space and / or reduce runtime. 593 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 594 595 /// hasTargetDAGCombine - If true, the target has custom DAG combine 596 /// transformations that it can perform for the specified node. 597 bool hasTargetDAGCombine(ISD::NodeType NT) const { 598 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 599 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 600 } 601 602 /// This function returns the maximum number of store operations permitted 603 /// to replace a call to llvm.memset. The value is set by the target at the 604 /// performance threshold for such a replacement. 605 /// @brief Get maximum # of store operations permitted for llvm.memset 606 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 607 608 /// This function returns the maximum number of store operations permitted 609 /// to replace a call to llvm.memcpy. The value is set by the target at the 610 /// performance threshold for such a replacement. 611 /// @brief Get maximum # of store operations permitted for llvm.memcpy 612 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 613 614 /// This function returns the maximum number of store operations permitted 615 /// to replace a call to llvm.memmove. The value is set by the target at the 616 /// performance threshold for such a replacement. 617 /// @brief Get maximum # of store operations permitted for llvm.memmove 618 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 619 620 /// This function returns true if the target allows unaligned memory accesses. 621 /// of the specified type. This is used, for example, in situations where an 622 /// array copy/move/set is converted to a sequence of store operations. It's 623 /// use helps to ensure that such replacements don't generate code that causes 624 /// an alignment error (trap) on the target machine. 625 /// @brief Determine if the target supports unaligned memory accesses. 626 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 627 return false; 628 } 629 630 /// This function returns true if the target would benefit from code placement 631 /// optimization. 632 /// @brief Determine if the target should perform code placement optimization. 633 bool shouldOptimizeCodePlacement() const { 634 return benefitFromCodePlacementOpt; 635 } 636 637 /// getOptimalMemOpType - Returns the target specific optimal type for load 638 /// and store operations as a result of memset, memcpy, and memmove 639 /// lowering. If DstAlign is zero that means it's safe to destination 640 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 641 /// means there isn't a need to check it against alignment requirement, 642 /// probably because the source does not need to be loaded. If 643 /// 'NonScalarIntSafe' is true, that means it's safe to return a 644 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 645 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 646 /// constant so it does not need to be loaded. 647 /// It returns EVT::Other if the type should be determined using generic 648 /// target-independent logic. 649 virtual EVT getOptimalMemOpType(uint64_t Size, 650 unsigned DstAlign, unsigned SrcAlign, 651 bool NonScalarIntSafe, bool MemcpyStrSrc, 652 MachineFunction &MF) const { 653 return MVT::Other; 654 } 655 656 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 657 /// to implement llvm.setjmp. 658 bool usesUnderscoreSetJmp() const { 659 return UseUnderscoreSetJmp; 660 } 661 662 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 663 /// to implement llvm.longjmp. 664 bool usesUnderscoreLongJmp() const { 665 return UseUnderscoreLongJmp; 666 } 667 668 /// getStackPointerRegisterToSaveRestore - If a physical register, this 669 /// specifies the register that llvm.savestack/llvm.restorestack should save 670 /// and restore. 671 unsigned getStackPointerRegisterToSaveRestore() const { 672 return StackPointerRegisterToSaveRestore; 673 } 674 675 /// getExceptionAddressRegister - If a physical register, this returns 676 /// the register that receives the exception address on entry to a landing 677 /// pad. 678 unsigned getExceptionAddressRegister() const { 679 return ExceptionPointerRegister; 680 } 681 682 /// getExceptionSelectorRegister - If a physical register, this returns 683 /// the register that receives the exception typeid on entry to a landing 684 /// pad. 685 unsigned getExceptionSelectorRegister() const { 686 return ExceptionSelectorRegister; 687 } 688 689 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 690 /// set, the default is 200) 691 unsigned getJumpBufSize() const { 692 return JumpBufSize; 693 } 694 695 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 696 /// (if never set, the default is 0) 697 unsigned getJumpBufAlignment() const { 698 return JumpBufAlignment; 699 } 700 701 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 702 /// argument. 703 unsigned getMinStackArgumentAlignment() const { 704 return MinStackArgumentAlignment; 705 } 706 707 /// getPrefLoopAlignment - return the preferred loop alignment. 708 /// 709 unsigned getPrefLoopAlignment() const { 710 return PrefLoopAlignment; 711 } 712 713 /// getShouldFoldAtomicFences - return whether the combiner should fold 714 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 715 /// 716 bool getShouldFoldAtomicFences() const { 717 return ShouldFoldAtomicFences; 718 } 719 720 /// getPreIndexedAddressParts - returns true by value, base pointer and 721 /// offset pointer and addressing mode by reference if the node's address 722 /// can be legally represented as pre-indexed load / store address. 723 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 724 SDValue &Offset, 725 ISD::MemIndexedMode &AM, 726 SelectionDAG &DAG) const { 727 return false; 728 } 729 730 /// getPostIndexedAddressParts - returns true by value, base pointer and 731 /// offset pointer and addressing mode by reference if this node can be 732 /// combined with a load / store to form a post-indexed load / store. 733 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 734 SDValue &Base, SDValue &Offset, 735 ISD::MemIndexedMode &AM, 736 SelectionDAG &DAG) const { 737 return false; 738 } 739 740 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 741 /// current function. The returned value is a member of the 742 /// MachineJumpTableInfo::JTEntryKind enum. 743 virtual unsigned getJumpTableEncoding() const; 744 745 virtual const MCExpr * 746 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 747 const MachineBasicBlock *MBB, unsigned uid, 748 MCContext &Ctx) const { 749 assert(0 && "Need to implement this hook if target has custom JTIs"); 750 return 0; 751 } 752 753 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 754 /// jumptable. 755 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 756 SelectionDAG &DAG) const; 757 758 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 759 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 760 /// MCExpr. 761 virtual const MCExpr * 762 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 763 unsigned JTI, MCContext &Ctx) const; 764 765 /// isOffsetFoldingLegal - Return true if folding a constant offset 766 /// with the given GlobalAddress is legal. It is frequently not legal in 767 /// PIC relocation models. 768 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 769 770 /// getFunctionAlignment - Return the Log2 alignment of this function. 771 virtual unsigned getFunctionAlignment(const Function *) const = 0; 772 773 /// getStackCookieLocation - Return true if the target stores stack 774 /// protector cookies at a fixed offset in some non-standard address 775 /// space, and populates the address space and offset as 776 /// appropriate. 777 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const { 778 return false; 779 } 780 781 //===--------------------------------------------------------------------===// 782 // TargetLowering Optimization Methods 783 // 784 785 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 786 /// SDValues for returning information from TargetLowering to its clients 787 /// that want to combine 788 struct TargetLoweringOpt { 789 SelectionDAG &DAG; 790 bool LegalTys; 791 bool LegalOps; 792 SDValue Old; 793 SDValue New; 794 795 explicit TargetLoweringOpt(SelectionDAG &InDAG, 796 bool LT, bool LO) : 797 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 798 799 bool LegalTypes() const { return LegalTys; } 800 bool LegalOperations() const { return LegalOps; } 801 802 bool CombineTo(SDValue O, SDValue N) { 803 Old = O; 804 New = N; 805 return true; 806 } 807 808 /// ShrinkDemandedConstant - Check to see if the specified operand of the 809 /// specified instruction is a constant integer. If so, check to see if 810 /// there are any bits set in the constant that are not demanded. If so, 811 /// shrink the constant and return true. 812 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 813 814 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 815 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 816 /// cast, but it could be generalized for targets with other types of 817 /// implicit widening casts. 818 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 819 DebugLoc dl); 820 }; 821 822 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 823 /// DemandedMask bits of the result of Op are ever used downstream. If we can 824 /// use this information to simplify Op, create a new simplified DAG node and 825 /// return true, returning the original and new nodes in Old and New. 826 /// Otherwise, analyze the expression and return a mask of KnownOne and 827 /// KnownZero bits for the expression (used to simplify the caller). 828 /// The KnownZero/One bits may only be accurate for those bits in the 829 /// DemandedMask. 830 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 831 APInt &KnownZero, APInt &KnownOne, 832 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 833 834 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 835 /// Mask are known to be either zero or one and return them in the 836 /// KnownZero/KnownOne bitsets. 837 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 838 const APInt &Mask, 839 APInt &KnownZero, 840 APInt &KnownOne, 841 const SelectionDAG &DAG, 842 unsigned Depth = 0) const; 843 844 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 845 /// targets that want to expose additional information about sign bits to the 846 /// DAG Combiner. 847 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 848 unsigned Depth = 0) const; 849 850 struct DAGCombinerInfo { 851 void *DC; // The DAG Combiner object. 852 bool BeforeLegalize; 853 bool BeforeLegalizeOps; 854 bool CalledByLegalizer; 855 public: 856 SelectionDAG &DAG; 857 858 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 859 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 860 CalledByLegalizer(cl), DAG(dag) {} 861 862 bool isBeforeLegalize() const { return BeforeLegalize; } 863 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 864 bool isCalledByLegalizer() const { return CalledByLegalizer; } 865 866 void AddToWorklist(SDNode *N); 867 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 868 bool AddTo = true); 869 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 870 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 871 872 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 873 }; 874 875 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 876 /// and cc. If it is unable to simplify it, return a null SDValue. 877 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 878 ISD::CondCode Cond, bool foldBooleans, 879 DAGCombinerInfo &DCI, DebugLoc dl) const; 880 881 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 882 /// node is a GlobalAddress + offset. 883 virtual bool 884 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 885 886 /// PerformDAGCombine - This method will be invoked for all target nodes and 887 /// for any target-independent nodes that the target has registered with 888 /// invoke it for. 889 /// 890 /// The semantics are as follows: 891 /// Return Value: 892 /// SDValue.Val == 0 - No change was made 893 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 894 /// otherwise - N should be replaced by the returned Operand. 895 /// 896 /// In addition, methods provided by DAGCombinerInfo may be used to perform 897 /// more complex transformations. 898 /// 899 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 900 901 /// isTypeDesirableForOp - Return true if the target has native support for 902 /// the specified value type and it is 'desirable' to use the type for the 903 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 904 /// instruction encodings are longer and some i16 instructions are slow. 905 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const { 906 // By default, assume all legal types are desirable. 907 return isTypeLegal(VT); 908 } 909 910 /// IsDesirableToPromoteOp - This method query the target whether it is 911 /// beneficial for dag combiner to promote the specified node. If true, it 912 /// should return the desired promotion type by reference. 913 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 914 return false; 915 } 916 917 //===--------------------------------------------------------------------===// 918 // TargetLowering Configuration Methods - These methods should be invoked by 919 // the derived class constructor to configure this object for the target. 920 // 921 922protected: 923 /// setShiftAmountType - Describe the type that should be used for shift 924 /// amounts. This type defaults to the pointer type. 925 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 926 927 /// setBooleanContents - Specify how the target extends the result of a 928 /// boolean value from i1 to a wider type. See getBooleanContents. 929 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 930 931 /// setSchedulingPreference - Specify the target scheduling preference. 932 void setSchedulingPreference(Sched::Preference Pref) { 933 SchedPreferenceInfo = Pref; 934 } 935 936 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 937 /// use _setjmp to implement llvm.setjmp or the non _ version. 938 /// Defaults to false. 939 void setUseUnderscoreSetJmp(bool Val) { 940 UseUnderscoreSetJmp = Val; 941 } 942 943 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 944 /// use _longjmp to implement llvm.longjmp or the non _ version. 945 /// Defaults to false. 946 void setUseUnderscoreLongJmp(bool Val) { 947 UseUnderscoreLongJmp = Val; 948 } 949 950 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 951 /// specifies the register that llvm.savestack/llvm.restorestack should save 952 /// and restore. 953 void setStackPointerRegisterToSaveRestore(unsigned R) { 954 StackPointerRegisterToSaveRestore = R; 955 } 956 957 /// setExceptionPointerRegister - If set to a physical register, this sets 958 /// the register that receives the exception address on entry to a landing 959 /// pad. 960 void setExceptionPointerRegister(unsigned R) { 961 ExceptionPointerRegister = R; 962 } 963 964 /// setExceptionSelectorRegister - If set to a physical register, this sets 965 /// the register that receives the exception typeid on entry to a landing 966 /// pad. 967 void setExceptionSelectorRegister(unsigned R) { 968 ExceptionSelectorRegister = R; 969 } 970 971 /// SelectIsExpensive - Tells the code generator not to expand operations 972 /// into sequences that use the select operations if possible. 973 void setSelectIsExpensive() { SelectIsExpensive = true; } 974 975 /// setIntDivIsCheap - Tells the code generator that integer divide is 976 /// expensive, and if possible, should be replaced by an alternate sequence 977 /// of instructions not containing an integer divide. 978 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 979 980 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 981 /// srl/add/sra for a signed divide by power of two, and let the target handle 982 /// it. 983 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 984 985 /// addRegisterClass - Add the specified register class as an available 986 /// regclass for the specified value type. This indicates the selector can 987 /// handle values of that class natively. 988 void addRegisterClass(EVT VT, TargetRegisterClass *RC, 989 bool isSynthesizable = true) { 990 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 991 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 992 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 993 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable; 994 } 995 996 /// findRepresentativeClass - Return the largest legal super-reg register class 997 /// of the specified register class. 998 virtual const TargetRegisterClass * 999 findRepresentativeClass(const TargetRegisterClass *RC) const; 1000 1001 /// computeRegisterProperties - Once all of the register classes are added, 1002 /// this allows us to compute derived properties we expose. 1003 void computeRegisterProperties(); 1004 1005 /// setOperationAction - Indicate that the specified operation does not work 1006 /// with the specified type and indicate what to do about it. 1007 void setOperationAction(unsigned Op, MVT VT, 1008 LegalizeAction Action) { 1009 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 1010 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 1011 } 1012 1013 /// setLoadExtAction - Indicate that the specified load with extension does 1014 /// not work with the specified type and indicate what to do about it. 1015 void setLoadExtAction(unsigned ExtType, MVT VT, 1016 LegalizeAction Action) { 1017 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 1018 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1019 "Table isn't big enough!"); 1020 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 1021 } 1022 1023 /// setTruncStoreAction - Indicate that the specified truncating store does 1024 /// not work with the specified type and indicate what to do about it. 1025 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1026 LegalizeAction Action) { 1027 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE && 1028 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE && 1029 "Table isn't big enough!"); 1030 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 1031 } 1032 1033 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1034 /// does not work with the specified type and indicate what to do abort 1035 /// it. NOTE: All indexed mode loads are initialized to Expand in 1036 /// TargetLowering.cpp 1037 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1038 LegalizeAction Action) { 1039 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1040 IdxMode < ISD::LAST_INDEXED_MODE && 1041 (unsigned)Action < 0xf && 1042 "Table isn't big enough!"); 1043 // Load action are kept in the upper half. 1044 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1045 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1046 } 1047 1048 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1049 /// does not work with the specified type and indicate what to do about 1050 /// it. NOTE: All indexed mode stores are initialized to Expand in 1051 /// TargetLowering.cpp 1052 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1053 LegalizeAction Action) { 1054 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1055 IdxMode < ISD::LAST_INDEXED_MODE && 1056 (unsigned)Action < 0xf && 1057 "Table isn't big enough!"); 1058 // Store action are kept in the lower half. 1059 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1060 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1061 } 1062 1063 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1064 /// supported on the target and indicate what to do about it. 1065 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1066 LegalizeAction Action) { 1067 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1068 (unsigned)CC < array_lengthof(CondCodeActions) && 1069 "Table isn't big enough!"); 1070 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1071 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1072 } 1073 1074 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1075 /// promotion code defaults to trying a larger integer/fp until it can find 1076 /// one that works. If that default is insufficient, this method can be used 1077 /// by the target to override the default. 1078 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1079 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1080 } 1081 1082 /// setTargetDAGCombine - Targets should invoke this method for each target 1083 /// independent node that they want to provide a custom DAG combiner for by 1084 /// implementing the PerformDAGCombine virtual method. 1085 void setTargetDAGCombine(ISD::NodeType NT) { 1086 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1087 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1088 } 1089 1090 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1091 /// bytes); default is 200 1092 void setJumpBufSize(unsigned Size) { 1093 JumpBufSize = Size; 1094 } 1095 1096 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1097 /// alignment (in bytes); default is 0 1098 void setJumpBufAlignment(unsigned Align) { 1099 JumpBufAlignment = Align; 1100 } 1101 1102 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1103 /// alignment is zero, it means the target does not care about loop alignment. 1104 void setPrefLoopAlignment(unsigned Align) { 1105 PrefLoopAlignment = Align; 1106 } 1107 1108 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1109 /// argument. 1110 void setMinStackArgumentAlignment(unsigned Align) { 1111 MinStackArgumentAlignment = Align; 1112 } 1113 1114 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1115 /// atomic operation intrinsics includes locking. Default is false. 1116 void setShouldFoldAtomicFences(bool fold) { 1117 ShouldFoldAtomicFences = fold; 1118 } 1119 1120public: 1121 //===--------------------------------------------------------------------===// 1122 // Lowering methods - These methods must be implemented by targets so that 1123 // the SelectionDAGLowering code knows how to lower these. 1124 // 1125 1126 /// LowerFormalArguments - This hook must be implemented to lower the 1127 /// incoming (formal) arguments, described by the Ins array, into the 1128 /// specified DAG. The implementation should fill in the InVals array 1129 /// with legal-type argument values, and return the resulting token 1130 /// chain value. 1131 /// 1132 virtual SDValue 1133 LowerFormalArguments(SDValue Chain, 1134 CallingConv::ID CallConv, bool isVarArg, 1135 const SmallVectorImpl<ISD::InputArg> &Ins, 1136 DebugLoc dl, SelectionDAG &DAG, 1137 SmallVectorImpl<SDValue> &InVals) const { 1138 assert(0 && "Not Implemented"); 1139 return SDValue(); // this is here to silence compiler errors 1140 } 1141 1142 /// LowerCallTo - This function lowers an abstract call to a function into an 1143 /// actual call. This returns a pair of operands. The first element is the 1144 /// return value for the function (if RetTy is not VoidTy). The second 1145 /// element is the outgoing token chain. It calls LowerCall to do the actual 1146 /// lowering. 1147 struct ArgListEntry { 1148 SDValue Node; 1149 const Type* Ty; 1150 bool isSExt : 1; 1151 bool isZExt : 1; 1152 bool isInReg : 1; 1153 bool isSRet : 1; 1154 bool isNest : 1; 1155 bool isByVal : 1; 1156 uint16_t Alignment; 1157 1158 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1159 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1160 }; 1161 typedef std::vector<ArgListEntry> ArgListTy; 1162 std::pair<SDValue, SDValue> 1163 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1164 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1165 CallingConv::ID CallConv, bool isTailCall, 1166 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1167 SelectionDAG &DAG, DebugLoc dl) const; 1168 1169 /// LowerCall - This hook must be implemented to lower calls into the 1170 /// the specified DAG. The outgoing arguments to the call are described 1171 /// by the Outs array, and the values to be returned by the call are 1172 /// described by the Ins array. The implementation should fill in the 1173 /// InVals array with legal-type return values from the call, and return 1174 /// the resulting token chain value. 1175 virtual SDValue 1176 LowerCall(SDValue Chain, SDValue Callee, 1177 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 1178 const SmallVectorImpl<ISD::OutputArg> &Outs, 1179 const SmallVectorImpl<SDValue> &OutVals, 1180 const SmallVectorImpl<ISD::InputArg> &Ins, 1181 DebugLoc dl, SelectionDAG &DAG, 1182 SmallVectorImpl<SDValue> &InVals) const { 1183 assert(0 && "Not Implemented"); 1184 return SDValue(); // this is here to silence compiler errors 1185 } 1186 1187 /// CanLowerReturn - This hook should be implemented to check whether the 1188 /// return values described by the Outs array can fit into the return 1189 /// registers. If false is returned, an sret-demotion is performed. 1190 /// 1191 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1192 const SmallVectorImpl<ISD::OutputArg> &Outs, 1193 LLVMContext &Context) const 1194 { 1195 // Return true by default to get preexisting behavior. 1196 return true; 1197 } 1198 1199 /// LowerReturn - This hook must be implemented to lower outgoing 1200 /// return values, described by the Outs array, into the specified 1201 /// DAG. The implementation should return the resulting token chain 1202 /// value. 1203 /// 1204 virtual SDValue 1205 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1206 const SmallVectorImpl<ISD::OutputArg> &Outs, 1207 const SmallVectorImpl<SDValue> &OutVals, 1208 DebugLoc dl, SelectionDAG &DAG) const { 1209 assert(0 && "Not Implemented"); 1210 return SDValue(); // this is here to silence compiler errors 1211 } 1212 1213 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1214 /// to legalize nodes with an illegal operand type but legal result types. 1215 /// It replaces the LowerOperation callback in the type Legalizer. 1216 /// The reason we can not do away with LowerOperation entirely is that 1217 /// LegalizeDAG isn't yet ready to use this callback. 1218 /// TODO: Consider merging with ReplaceNodeResults. 1219 1220 /// The target places new result values for the node in Results (their number 1221 /// and types must exactly match those of the original return values of 1222 /// the node), or leaves Results empty, which indicates that the node is not 1223 /// to be custom lowered after all. 1224 /// The default implementation calls LowerOperation. 1225 virtual void LowerOperationWrapper(SDNode *N, 1226 SmallVectorImpl<SDValue> &Results, 1227 SelectionDAG &DAG) const; 1228 1229 /// LowerOperation - This callback is invoked for operations that are 1230 /// unsupported by the target, which are registered to use 'custom' lowering, 1231 /// and whose defined values are all legal. 1232 /// If the target has no operations that require custom lowering, it need not 1233 /// implement this. The default implementation of this aborts. 1234 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1235 1236 /// ReplaceNodeResults - This callback is invoked when a node result type is 1237 /// illegal for the target, and the operation was registered to use 'custom' 1238 /// lowering for that result type. The target places new result values for 1239 /// the node in Results (their number and types must exactly match those of 1240 /// the original return values of the node), or leaves Results empty, which 1241 /// indicates that the node is not to be custom lowered after all. 1242 /// 1243 /// If the target has no operations that require custom lowering, it need not 1244 /// implement this. The default implementation aborts. 1245 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1246 SelectionDAG &DAG) const { 1247 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1248 } 1249 1250 /// getTargetNodeName() - This method returns the name of a target specific 1251 /// DAG node. 1252 virtual const char *getTargetNodeName(unsigned Opcode) const; 1253 1254 /// createFastISel - This method returns a target specific FastISel object, 1255 /// or null if the target does not support "fast" ISel. 1256 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const { 1257 return 0; 1258 } 1259 1260 //===--------------------------------------------------------------------===// 1261 // Inline Asm Support hooks 1262 // 1263 1264 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1265 /// call to be explicit llvm code if it wants to. This is useful for 1266 /// turning simple inline asms into LLVM intrinsics, which gives the 1267 /// compiler more information about the behavior of the code. 1268 virtual bool ExpandInlineAsm(CallInst *CI) const { 1269 return false; 1270 } 1271 1272 enum ConstraintType { 1273 C_Register, // Constraint represents specific register(s). 1274 C_RegisterClass, // Constraint represents any of register(s) in class. 1275 C_Memory, // Memory constraint. 1276 C_Other, // Something else. 1277 C_Unknown // Unsupported constraint. 1278 }; 1279 1280 /// AsmOperandInfo - This contains information for each constraint that we are 1281 /// lowering. 1282 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1283 /// ConstraintCode - This contains the actual string for the code, like "m". 1284 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1285 /// most closely matches the operand. 1286 std::string ConstraintCode; 1287 1288 /// ConstraintType - Information about the constraint code, e.g. Register, 1289 /// RegisterClass, Memory, Other, Unknown. 1290 TargetLowering::ConstraintType ConstraintType; 1291 1292 /// CallOperandval - If this is the result output operand or a 1293 /// clobber, this is null, otherwise it is the incoming operand to the 1294 /// CallInst. This gets modified as the asm is processed. 1295 Value *CallOperandVal; 1296 1297 /// ConstraintVT - The ValueType for the operand value. 1298 EVT ConstraintVT; 1299 1300 /// isMatchingInputConstraint - Return true of this is an input operand that 1301 /// is a matching constraint like "4". 1302 bool isMatchingInputConstraint() const; 1303 1304 /// getMatchedOperand - If this is an input matching constraint, this method 1305 /// returns the output operand it matches. 1306 unsigned getMatchedOperand() const; 1307 1308 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1309 : InlineAsm::ConstraintInfo(info), 1310 ConstraintType(TargetLowering::C_Unknown), 1311 CallOperandVal(0), ConstraintVT(MVT::Other) { 1312 } 1313 }; 1314 1315 /// ComputeConstraintToUse - Determines the constraint code and constraint 1316 /// type to use for the specific AsmOperandInfo, setting 1317 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1318 /// being passed in is available, it can be passed in as Op, otherwise an 1319 /// empty SDValue can be passed. 1320 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1321 SDValue Op, 1322 SelectionDAG *DAG = 0) const; 1323 1324 /// getConstraintType - Given a constraint, return the type of constraint it 1325 /// is for this target. 1326 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1327 1328 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1329 /// return a list of registers that can be used to satisfy the constraint. 1330 /// This should only be used for C_RegisterClass constraints. 1331 virtual std::vector<unsigned> 1332 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1333 EVT VT) const; 1334 1335 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1336 /// {edx}), return the register number and the register class for the 1337 /// register. 1338 /// 1339 /// Given a register class constraint, like 'r', if this corresponds directly 1340 /// to an LLVM register class, return a register of 0 and the register class 1341 /// pointer. 1342 /// 1343 /// This should only be used for C_Register constraints. On error, 1344 /// this returns a register number of 0 and a null register class pointer.. 1345 virtual std::pair<unsigned, const TargetRegisterClass*> 1346 getRegForInlineAsmConstraint(const std::string &Constraint, 1347 EVT VT) const; 1348 1349 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1350 /// with another that has more specific requirements based on the type of the 1351 /// corresponding operand. This returns null if there is no replacement to 1352 /// make. 1353 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1354 1355 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1356 /// vector. If it is invalid, don't add anything to Ops. 1357 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1358 std::vector<SDValue> &Ops, 1359 SelectionDAG &DAG) const; 1360 1361 //===--------------------------------------------------------------------===// 1362 // Instruction Emitting Hooks 1363 // 1364 1365 // EmitInstrWithCustomInserter - This method should be implemented by targets 1366 // that mark instructions with the 'usesCustomInserter' flag. These 1367 // instructions are special in various ways, which require special support to 1368 // insert. The specified MachineInstr is created but not inserted into any 1369 // basic blocks, and this method is called to expand it into a sequence of 1370 // instructions, potentially also creating new basic blocks and control flow. 1371 virtual MachineBasicBlock * 1372 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 1373 1374 //===--------------------------------------------------------------------===// 1375 // Addressing mode description hooks (used by LSR etc). 1376 // 1377 1378 /// AddrMode - This represents an addressing mode of: 1379 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1380 /// If BaseGV is null, there is no BaseGV. 1381 /// If BaseOffs is zero, there is no base offset. 1382 /// If HasBaseReg is false, there is no base register. 1383 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1384 /// no scale. 1385 /// 1386 struct AddrMode { 1387 GlobalValue *BaseGV; 1388 int64_t BaseOffs; 1389 bool HasBaseReg; 1390 int64_t Scale; 1391 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1392 }; 1393 1394 /// isLegalAddressingMode - Return true if the addressing mode represented by 1395 /// AM is legal for this target, for a load/store of the specified type. 1396 /// The type may be VoidTy, in which case only return true if the addressing 1397 /// mode is legal for a load/store of any legal type. 1398 /// TODO: Handle pre/postinc as well. 1399 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1400 1401 /// isTruncateFree - Return true if it's free to truncate a value of 1402 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1403 /// register EAX to i16 by referencing its sub-register AX. 1404 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1405 return false; 1406 } 1407 1408 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1409 return false; 1410 } 1411 1412 /// isZExtFree - Return true if any actual instruction that defines a 1413 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1414 /// register. This does not necessarily include registers defined in 1415 /// unknown ways, such as incoming arguments, or copies from unknown 1416 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1417 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1418 /// all instructions that define 32-bit values implicit zero-extend the 1419 /// result out to 64 bits. 1420 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1421 return false; 1422 } 1423 1424 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1425 return false; 1426 } 1427 1428 /// isNarrowingProfitable - Return true if it's profitable to narrow 1429 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1430 /// from i32 to i8 but not from i32 to i16. 1431 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1432 return false; 1433 } 1434 1435 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1436 /// icmp immediate, that is the target has icmp instructions which can compare 1437 /// a register against the immediate without having to materialize the 1438 /// immediate into a register. 1439 virtual bool isLegalICmpImmediate(int64_t Imm) const { 1440 return true; 1441 } 1442 1443 //===--------------------------------------------------------------------===// 1444 // Div utility functions 1445 // 1446 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1447 std::vector<SDNode*>* Created) const; 1448 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1449 std::vector<SDNode*>* Created) const; 1450 1451 1452 //===--------------------------------------------------------------------===// 1453 // Runtime Library hooks 1454 // 1455 1456 /// setLibcallName - Rename the default libcall routine name for the specified 1457 /// libcall. 1458 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1459 LibcallRoutineNames[Call] = Name; 1460 } 1461 1462 /// getLibcallName - Get the libcall routine name for the specified libcall. 1463 /// 1464 const char *getLibcallName(RTLIB::Libcall Call) const { 1465 return LibcallRoutineNames[Call]; 1466 } 1467 1468 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1469 /// result of the comparison libcall against zero. 1470 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1471 CmpLibcallCCs[Call] = CC; 1472 } 1473 1474 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1475 /// the comparison libcall against zero. 1476 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1477 return CmpLibcallCCs[Call]; 1478 } 1479 1480 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1481 /// specified libcall. 1482 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1483 LibcallCallingConvs[Call] = CC; 1484 } 1485 1486 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1487 /// specified libcall. 1488 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1489 return LibcallCallingConvs[Call]; 1490 } 1491 1492private: 1493 const TargetMachine &TM; 1494 const TargetData *TD; 1495 const TargetLoweringObjectFile &TLOF; 1496 1497 /// PointerTy - The type to use for pointers, usually i32 or i64. 1498 /// 1499 MVT PointerTy; 1500 1501 /// IsLittleEndian - True if this is a little endian target. 1502 /// 1503 bool IsLittleEndian; 1504 1505 /// SelectIsExpensive - Tells the code generator not to expand operations 1506 /// into sequences that use the select operations if possible. 1507 bool SelectIsExpensive; 1508 1509 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1510 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1511 /// a real cost model is in place. If we ever optimize for size, this will be 1512 /// set to true unconditionally. 1513 bool IntDivIsCheap; 1514 1515 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1516 /// srl/add/sra for a signed divide by power of two, and let the target handle 1517 /// it. 1518 bool Pow2DivIsCheap; 1519 1520 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1521 /// llvm.setjmp. Defaults to false. 1522 bool UseUnderscoreSetJmp; 1523 1524 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1525 /// llvm.longjmp. Defaults to false. 1526 bool UseUnderscoreLongJmp; 1527 1528 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1529 /// PointerTy is. 1530 MVT ShiftAmountTy; 1531 1532 /// BooleanContents - Information about the contents of the high-bits in 1533 /// boolean values held in a type wider than i1. See getBooleanContents. 1534 BooleanContent BooleanContents; 1535 1536 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1537 /// total cycles or lowest register usage. 1538 Sched::Preference SchedPreferenceInfo; 1539 1540 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1541 unsigned JumpBufSize; 1542 1543 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1544 /// buffers 1545 unsigned JumpBufAlignment; 1546 1547 /// MinStackArgumentAlignment - The minimum alignment that any argument 1548 /// on the stack needs to have. 1549 /// 1550 unsigned MinStackArgumentAlignment; 1551 1552 /// PrefLoopAlignment - The perferred loop alignment. 1553 /// 1554 unsigned PrefLoopAlignment; 1555 1556 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1557 /// be folded into the enclosed atomic intrinsic instruction by the 1558 /// combiner. 1559 bool ShouldFoldAtomicFences; 1560 1561 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1562 /// specifies the register that llvm.savestack/llvm.restorestack should save 1563 /// and restore. 1564 unsigned StackPointerRegisterToSaveRestore; 1565 1566 /// ExceptionPointerRegister - If set to a physical register, this specifies 1567 /// the register that receives the exception address on entry to a landing 1568 /// pad. 1569 unsigned ExceptionPointerRegister; 1570 1571 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1572 /// the register that receives the exception typeid on entry to a landing 1573 /// pad. 1574 unsigned ExceptionSelectorRegister; 1575 1576 /// RegClassForVT - This indicates the default register class to use for 1577 /// each ValueType the target supports natively. 1578 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1579 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1580 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1581 1582 /// RepRegClassForVT - This indicates the "representative" register class to 1583 /// use for each ValueType the target supports natively. This information is 1584 /// used by the scheduler to track register pressure. e.g. On x86, i8, i16, 1585 /// and i32's representative class would be GR32. 1586 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1587 1588 /// Synthesizable indicates whether it is OK for the compiler to create new 1589 /// operations using this type. All Legal types are Synthesizable except 1590 /// MMX types on X86. Non-Legal types are not Synthesizable. 1591 bool Synthesizable[MVT::LAST_VALUETYPE]; 1592 1593 /// TransformToType - For any value types we are promoting or expanding, this 1594 /// contains the value type that we are changing to. For Expanded types, this 1595 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1596 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1597 /// by the system, this holds the same type (e.g. i32 -> i32). 1598 EVT TransformToType[MVT::LAST_VALUETYPE]; 1599 1600 /// OpActions - For each operation and each value type, keep a LegalizeAction 1601 /// that indicates how instruction selection should deal with the operation. 1602 /// Most operations are Legal (aka, supported natively by the target), but 1603 /// operations that are not should be described. Note that operations on 1604 /// non-legal value types are not described here. 1605 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1606 1607 /// LoadExtActions - For each load extension type and each value type, 1608 /// keep a LegalizeAction that indicates how instruction selection should deal 1609 /// with a load of a specific value type and extension type. 1610 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1611 1612 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1613 /// indicates whether a truncating store of a specific value type and 1614 /// truncating type is legal. 1615 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1616 1617 /// IndexedModeActions - For each indexed mode and each value type, 1618 /// keep a pair of LegalizeAction that indicates how instruction 1619 /// selection should deal with the load / store. The first dimension is the 1620 /// value_type for the reference. The second dimension represents the various 1621 /// modes for load store. 1622 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1623 1624 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1625 /// LegalizeAction that indicates how instruction selection should 1626 /// deal with the condition code. 1627 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1628 1629 ValueTypeActionImpl ValueTypeActions; 1630 1631 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1632 1633 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1634 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1635 /// which sets a bit in this array. 1636 unsigned char 1637 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1638 1639 /// PromoteToType - For operations that must be promoted to a specific type, 1640 /// this holds the destination type. This map should be sparse, so don't hold 1641 /// it as an array. 1642 /// 1643 /// Targets add entries to this map with AddPromotedToType(..), clients access 1644 /// this with getTypeToPromoteTo(..). 1645 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1646 PromoteToType; 1647 1648 /// LibcallRoutineNames - Stores the name each libcall. 1649 /// 1650 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1651 1652 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1653 /// of each of the comparison libcall against zero. 1654 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1655 1656 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1657 /// libcall. 1658 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1659 1660protected: 1661 /// When lowering \@llvm.memset this field specifies the maximum number of 1662 /// store operations that may be substituted for the call to memset. Targets 1663 /// must set this value based on the cost threshold for that target. Targets 1664 /// should assume that the memset will be done using as many of the largest 1665 /// store operations first, followed by smaller ones, if necessary, per 1666 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1667 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1668 /// store. This only applies to setting a constant array of a constant size. 1669 /// @brief Specify maximum number of store instructions per memset call. 1670 unsigned maxStoresPerMemset; 1671 1672 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1673 /// store operations that may be substituted for a call to memcpy. Targets 1674 /// must set this value based on the cost threshold for that target. Targets 1675 /// should assume that the memcpy will be done using as many of the largest 1676 /// store operations first, followed by smaller ones, if necessary, per 1677 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1678 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1679 /// and one 1-byte store. This only applies to copying a constant array of 1680 /// constant size. 1681 /// @brief Specify maximum bytes of store instructions per memcpy call. 1682 unsigned maxStoresPerMemcpy; 1683 1684 /// When lowering \@llvm.memmove this field specifies the maximum number of 1685 /// store instructions that may be substituted for a call to memmove. Targets 1686 /// must set this value based on the cost threshold for that target. Targets 1687 /// should assume that the memmove will be done using as many of the largest 1688 /// store operations first, followed by smaller ones, if necessary, per 1689 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1690 /// with 8-bit alignment would result in nine 1-byte stores. This only 1691 /// applies to copying a constant array of constant size. 1692 /// @brief Specify maximum bytes of store instructions per memmove call. 1693 unsigned maxStoresPerMemmove; 1694 1695 /// This field specifies whether the target can benefit from code placement 1696 /// optimization. 1697 bool benefitFromCodePlacementOpt; 1698 1699private: 1700 /// isLegalRC - Return true if the value types that can be represented by the 1701 /// specified register class are all legal. 1702 bool isLegalRC(const TargetRegisterClass *RC) const; 1703 1704 /// hasLegalSuperRegRegClasses - Return true if the specified register class 1705 /// has one or more super-reg register classes that are legal. 1706 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const; 1707}; 1708 1709/// GetReturnInfo - Given an LLVM IR type and return type attributes, 1710/// compute the return value EVTs and flags, and optionally also 1711/// the offsets, if the return value is being lowered to memory. 1712void GetReturnInfo(const Type* ReturnType, Attributes attr, 1713 SmallVectorImpl<ISD::OutputArg> &Outs, 1714 const TargetLowering &TLI, 1715 SmallVectorImpl<uint64_t> *Offsets = 0); 1716 1717} // end llvm namespace 1718 1719#endif 1720