TargetLowering.h revision eac6e1d0c748afc3d1496be0753ffbe5f5a4279b
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/Attributes.h" 28#include "llvm/CodeGen/SelectionDAGNodes.h" 29#include "llvm/CodeGen/RuntimeLibcalls.h" 30#include "llvm/ADT/APFloat.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/SmallSet.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/STLExtras.h" 35#include "llvm/Support/DebugLoc.h" 36#include "llvm/Target/TargetCallingConv.h" 37#include "llvm/Target/TargetMachine.h" 38#include <climits> 39#include <map> 40#include <vector> 41 42namespace llvm { 43 class AllocaInst; 44 class CallInst; 45 class Function; 46 class FastISel; 47 class FunctionLoweringInfo; 48 class ImmutableCallSite; 49 class MachineBasicBlock; 50 class MachineFunction; 51 class MachineFrameInfo; 52 class MachineInstr; 53 class MachineJumpTableInfo; 54 class MCContext; 55 class MCExpr; 56 class SDNode; 57 class SDValue; 58 class SelectionDAG; 59 class TargetData; 60 class TargetMachine; 61 class TargetRegisterClass; 62 class TargetLoweringObjectFile; 63 class Value; 64 65 // FIXME: should this be here? 66 namespace TLSModel { 67 enum Model { 68 GeneralDynamic, 69 LocalDynamic, 70 InitialExec, 71 LocalExec 72 }; 73 } 74 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 75 76 77//===----------------------------------------------------------------------===// 78/// TargetLowering - This class defines information used to lower LLVM code to 79/// legal SelectionDAG operators that the target instruction selector can accept 80/// natively. 81/// 82/// This class also defines callbacks that targets must implement to lower 83/// target-specific constructs to SelectionDAG operators. 84/// 85class TargetLowering { 86 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 87 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 88public: 89 /// LegalizeAction - This enum indicates whether operations are valid for a 90 /// target, and if not, what action should be used to make them valid. 91 enum LegalizeAction { 92 Legal, // The target natively supports this operation. 93 Promote, // This operation should be executed in a larger type. 94 Expand, // Try to expand this to other ops, otherwise use a libcall. 95 Custom // Use the LowerOperation hook to implement custom lowering. 96 }; 97 98 enum BooleanContent { // How the target represents true/false values. 99 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 100 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 101 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 102 }; 103 104 /// NOTE: The constructor takes ownership of TLOF. 105 explicit TargetLowering(const TargetMachine &TM, 106 const TargetLoweringObjectFile *TLOF); 107 virtual ~TargetLowering(); 108 109 const TargetMachine &getTargetMachine() const { return TM; } 110 const TargetData *getTargetData() const { return TD; } 111 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 112 113 bool isBigEndian() const { return !IsLittleEndian; } 114 bool isLittleEndian() const { return IsLittleEndian; } 115 MVT getPointerTy() const { return PointerTy; } 116 MVT getShiftAmountTy() const { return ShiftAmountTy; } 117 118 /// isSelectExpensive - Return true if the select operation is expensive for 119 /// this target. 120 bool isSelectExpensive() const { return SelectIsExpensive; } 121 122 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 123 /// a sequence of several shifts, adds, and multiplies for this target. 124 bool isIntDivCheap() const { return IntDivIsCheap; } 125 126 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 127 /// srl/add/sra. 128 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 129 130 /// getSetCCResultType - Return the ValueType of the result of SETCC 131 /// operations. Also used to obtain the target's preferred type for 132 /// the condition operand of SELECT and BRCOND nodes. In the case of 133 /// BRCOND the argument passed is MVT::Other since there are no other 134 /// operands to get a type hint from. 135 virtual 136 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 137 138 /// getCmpLibcallReturnType - Return the ValueType for comparison 139 /// libcalls. Comparions libcalls include floating point comparion calls, 140 /// and Ordered/Unordered check calls on floating point numbers. 141 virtual 142 MVT::SimpleValueType getCmpLibcallReturnType() const; 143 144 /// getBooleanContents - For targets without i1 registers, this gives the 145 /// nature of the high-bits of boolean values held in types wider than i1. 146 /// "Boolean values" are special true/false values produced by nodes like 147 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 148 /// Not to be confused with general values promoted from i1. 149 BooleanContent getBooleanContents() const { return BooleanContents;} 150 151 /// getSchedulingPreference - Return target scheduling preference. 152 Sched::Preference getSchedulingPreference() const { 153 return SchedPreferenceInfo; 154 } 155 156 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 157 /// different scheduling heuristics for different nodes. This function returns 158 /// the preference (or none) for the given node. 159 virtual Sched::Preference getSchedulingPreference(SDNode *N) const { 160 return Sched::None; 161 } 162 163 /// getRegClassFor - Return the register class that should be used for the 164 /// specified value type. 165 virtual TargetRegisterClass *getRegClassFor(EVT VT) const { 166 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 167 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 168 assert(RC && "This value type is not natively supported!"); 169 return RC; 170 } 171 172 /// getRepRegClassFor - Return the 'representative' register class for the 173 /// specified value type. The 'representative' register class is the largest 174 /// legal super-reg register class for the register class of the value type. 175 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 176 /// while the rep register class is GR64 on x86_64. 177 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { 178 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!"); 179 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; 180 return RC; 181 } 182 183 /// getRepRegClassCostFor - Return the cost of the 'representative' register 184 /// class for the specified value type. 185 virtual uint8_t getRepRegClassCostFor(EVT VT) const { 186 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!"); 187 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; 188 } 189 190 /// getRegPressureLimit - Return the register pressure "high water mark" for 191 /// the specific register class. The scheduler is in high register pressure 192 /// mode (for the specific register class) if it goes over the limit. 193 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 194 MachineFunction &MF) const { 195 return 0; 196 } 197 198 /// isTypeLegal - Return true if the target has native support for the 199 /// specified value type. This means that it has a register that directly 200 /// holds it without promotions or expansions. 201 bool isTypeLegal(EVT VT) const { 202 assert(!VT.isSimple() || 203 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 204 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 205 } 206 207 /// isTypeSynthesizable - Return true if it's OK for the compiler to create 208 /// new operations of this type. All Legal types are synthesizable except 209 /// MMX vector types on X86. Non-Legal types are not synthesizable. 210 bool isTypeSynthesizable(EVT VT) const { 211 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy]; 212 } 213 214 class ValueTypeActionImpl { 215 /// ValueTypeActions - For each value type, keep a LegalizeAction enum 216 /// that indicates how instruction selection should deal with the type. 217 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 218 219 LegalizeAction getExtendedTypeAction(EVT VT) const { 220 // Handle non-vector integers. 221 if (!VT.isVector()) { 222 assert(VT.isInteger() && "Unsupported extended type!"); 223 unsigned BitSize = VT.getSizeInBits(); 224 // First promote to a power-of-two size, then expand if necessary. 225 if (BitSize < 8 || !isPowerOf2_32(BitSize)) 226 return Promote; 227 return Expand; 228 } 229 230 // If this is a type smaller than a legal vector type, promote to that 231 // type, e.g. <2 x float> -> <4 x float>. 232 if (VT.getVectorElementType().isSimple() && 233 VT.getVectorNumElements() != 1) { 234 MVT EltType = VT.getVectorElementType().getSimpleVT(); 235 unsigned NumElts = VT.getVectorNumElements(); 236 while (1) { 237 // Round up to the nearest power of 2. 238 NumElts = (unsigned)NextPowerOf2(NumElts); 239 240 MVT LargerVector = MVT::getVectorVT(EltType, NumElts); 241 if (LargerVector == MVT()) break; 242 243 // If this the larger type is legal, promote to it. 244 if (getTypeAction(LargerVector) == Legal) return Promote; 245 } 246 } 247 248 return VT.isPow2VectorType() ? Expand : Promote; 249 } 250 public: 251 ValueTypeActionImpl() { 252 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 253 } 254 255 LegalizeAction getTypeAction(EVT VT) const { 256 if (!VT.isExtended()) 257 return getTypeAction(VT.getSimpleVT()); 258 return getExtendedTypeAction(VT); 259 } 260 261 LegalizeAction getTypeAction(MVT VT) const { 262 return (LegalizeAction)ValueTypeActions[VT.SimpleTy]; 263 } 264 265 void setTypeAction(EVT VT, LegalizeAction Action) { 266 unsigned I = VT.getSimpleVT().SimpleTy; 267 ValueTypeActions[I] = Action; 268 } 269 }; 270 271 const ValueTypeActionImpl &getValueTypeActions() const { 272 return ValueTypeActions; 273 } 274 275 /// getTypeAction - Return how we should legalize values of this type, either 276 /// it is already legal (return 'Legal') or we need to promote it to a larger 277 /// type (return 'Promote'), or we need to expand it into multiple registers 278 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 279 LegalizeAction getTypeAction(EVT VT) const { 280 return ValueTypeActions.getTypeAction(VT); 281 } 282 LegalizeAction getTypeAction(MVT VT) const { 283 return ValueTypeActions.getTypeAction(VT); 284 } 285 286 /// getTypeToTransformTo - For types supported by the target, this is an 287 /// identity function. For types that must be promoted to larger types, this 288 /// returns the larger type to promote to. For integer types that are larger 289 /// than the largest integer register, this contains one step in the expansion 290 /// to get to the smaller register. For illegal floating point types, this 291 /// returns the integer type to transform to. 292 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 293 if (VT.isSimple()) { 294 assert((unsigned)VT.getSimpleVT().SimpleTy < 295 array_lengthof(TransformToType)); 296 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 297 assert(getTypeAction(NVT) != Promote && 298 "Promote may not follow Expand or Promote"); 299 return NVT; 300 } 301 302 if (VT.isVector()) { 303 EVT NVT = VT.getPow2VectorType(Context); 304 if (NVT == VT) { 305 // Vector length is a power of 2 - split to half the size. 306 unsigned NumElts = VT.getVectorNumElements(); 307 EVT EltVT = VT.getVectorElementType(); 308 return (NumElts == 1) ? 309 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 310 } 311 // Promote to a power of two size, avoiding multi-step promotion. 312 return getTypeAction(NVT) == Promote ? 313 getTypeToTransformTo(Context, NVT) : NVT; 314 } else if (VT.isInteger()) { 315 EVT NVT = VT.getRoundIntegerType(Context); 316 if (NVT == VT) // Size is a power of two - expand to half the size. 317 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 318 319 // Promote to a power of two size, avoiding multi-step promotion. 320 return getTypeAction(NVT) == Promote ? 321 getTypeToTransformTo(Context, NVT) : NVT; 322 } 323 assert(0 && "Unsupported extended type!"); 324 return MVT(MVT::Other); // Not reached 325 } 326 327 /// getTypeToExpandTo - For types supported by the target, this is an 328 /// identity function. For types that must be expanded (i.e. integer types 329 /// that are larger than the largest integer register or illegal floating 330 /// point types), this returns the largest legal type it will be expanded to. 331 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 332 assert(!VT.isVector()); 333 while (true) { 334 switch (getTypeAction(VT)) { 335 case Legal: 336 return VT; 337 case Expand: 338 VT = getTypeToTransformTo(Context, VT); 339 break; 340 default: 341 assert(false && "Type is not legal nor is it to be expanded!"); 342 return VT; 343 } 344 } 345 return VT; 346 } 347 348 /// getVectorTypeBreakdown - Vector types are broken down into some number of 349 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 350 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 351 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 352 /// 353 /// This method returns the number of registers needed, and the VT for each 354 /// register. It also returns the VT and quantity of the intermediate values 355 /// before they are promoted/expanded. 356 /// 357 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 358 EVT &IntermediateVT, 359 unsigned &NumIntermediates, 360 EVT &RegisterVT) const; 361 362 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 363 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 364 /// this is the case, it returns true and store the intrinsic 365 /// information into the IntrinsicInfo that was passed to the function. 366 struct IntrinsicInfo { 367 unsigned opc; // target opcode 368 EVT memVT; // memory VT 369 const Value* ptrVal; // value representing memory location 370 int offset; // offset off of ptrVal 371 unsigned align; // alignment 372 bool vol; // is volatile? 373 bool readMem; // reads memory? 374 bool writeMem; // writes memory? 375 }; 376 377 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 378 const CallInst &I, unsigned Intrinsic) const { 379 return false; 380 } 381 382 /// isFPImmLegal - Returns true if the target can instruction select the 383 /// specified FP immediate natively. If false, the legalizer will materialize 384 /// the FP immediate as a load from a constant pool. 385 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const { 386 return false; 387 } 388 389 /// isShuffleMaskLegal - Targets can use this to indicate that they only 390 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 391 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 392 /// are assumed to be legal. 393 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 394 EVT VT) const { 395 return true; 396 } 397 398 /// canOpTrap - Returns true if the operation can trap for the value type. 399 /// VT must be a legal type. By default, we optimistically assume most 400 /// operations don't trap except for divide and remainder. 401 virtual bool canOpTrap(unsigned Op, EVT VT) const; 402 403 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 404 /// used by Targets can use this to indicate if there is a suitable 405 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 406 /// pool entry. 407 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 408 EVT VT) const { 409 return false; 410 } 411 412 /// getOperationAction - Return how this operation should be treated: either 413 /// it is legal, needs to be promoted to a larger size, needs to be 414 /// expanded to some other code sequence, or the target has a custom expander 415 /// for it. 416 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 417 if (VT.isExtended()) return Expand; 418 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 419 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 420 return (LegalizeAction)OpActions[I][Op]; 421 } 422 423 /// isOperationLegalOrCustom - Return true if the specified operation is 424 /// legal on this target or can be made legal with custom lowering. This 425 /// is used to help guide high-level lowering decisions. 426 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 427 return (VT == MVT::Other || isTypeLegal(VT)) && 428 (getOperationAction(Op, VT) == Legal || 429 getOperationAction(Op, VT) == Custom); 430 } 431 432 /// isOperationLegal - Return true if the specified operation is legal on this 433 /// target. 434 bool isOperationLegal(unsigned Op, EVT VT) const { 435 return (VT == MVT::Other || isTypeLegal(VT)) && 436 getOperationAction(Op, VT) == Legal; 437 } 438 439 /// getLoadExtAction - Return how this load with extension should be treated: 440 /// either it is legal, needs to be promoted to a larger size, needs to be 441 /// expanded to some other code sequence, or the target has a custom expander 442 /// for it. 443 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { 444 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 445 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 446 "Table isn't big enough!"); 447 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 448 } 449 450 /// isLoadExtLegal - Return true if the specified load with extension is legal 451 /// on this target. 452 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 453 return VT.isSimple() && 454 (getLoadExtAction(ExtType, VT) == Legal || 455 getLoadExtAction(ExtType, VT) == Custom); 456 } 457 458 /// getTruncStoreAction - Return how this store with truncation should be 459 /// treated: either it is legal, needs to be promoted to a larger size, needs 460 /// to be expanded to some other code sequence, or the target has a custom 461 /// expander for it. 462 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 463 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 464 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 465 "Table isn't big enough!"); 466 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] 467 [MemVT.getSimpleVT().SimpleTy]; 468 } 469 470 /// isTruncStoreLegal - Return true if the specified store with truncation is 471 /// legal on this target. 472 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 473 return isTypeLegal(ValVT) && MemVT.isSimple() && 474 (getTruncStoreAction(ValVT, MemVT) == Legal || 475 getTruncStoreAction(ValVT, MemVT) == Custom); 476 } 477 478 /// getIndexedLoadAction - Return how the indexed load should be treated: 479 /// either it is legal, needs to be promoted to a larger size, needs to be 480 /// expanded to some other code sequence, or the target has a custom expander 481 /// for it. 482 LegalizeAction 483 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 484 assert( IdxMode < ISD::LAST_INDEXED_MODE && 485 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 486 "Table isn't big enough!"); 487 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 488 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 489 } 490 491 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 492 /// on this target. 493 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 494 return VT.isSimple() && 495 (getIndexedLoadAction(IdxMode, VT) == Legal || 496 getIndexedLoadAction(IdxMode, VT) == Custom); 497 } 498 499 /// getIndexedStoreAction - Return how the indexed store should be treated: 500 /// either it is legal, needs to be promoted to a larger size, needs to be 501 /// expanded to some other code sequence, or the target has a custom expander 502 /// for it. 503 LegalizeAction 504 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 505 assert( IdxMode < ISD::LAST_INDEXED_MODE && 506 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 507 "Table isn't big enough!"); 508 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 509 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 510 } 511 512 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 513 /// on this target. 514 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 515 return VT.isSimple() && 516 (getIndexedStoreAction(IdxMode, VT) == Legal || 517 getIndexedStoreAction(IdxMode, VT) == Custom); 518 } 519 520 /// getCondCodeAction - Return how the condition code should be treated: 521 /// either it is legal, needs to be expanded to some other code sequence, 522 /// or the target has a custom expander for it. 523 LegalizeAction 524 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 525 assert((unsigned)CC < array_lengthof(CondCodeActions) && 526 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 527 "Table isn't big enough!"); 528 LegalizeAction Action = (LegalizeAction) 529 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 530 assert(Action != Promote && "Can't promote condition code!"); 531 return Action; 532 } 533 534 /// isCondCodeLegal - Return true if the specified condition code is legal 535 /// on this target. 536 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 537 return getCondCodeAction(CC, VT) == Legal || 538 getCondCodeAction(CC, VT) == Custom; 539 } 540 541 542 /// getTypeToPromoteTo - If the action for this operation is to promote, this 543 /// method returns the ValueType to promote to. 544 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 545 assert(getOperationAction(Op, VT) == Promote && 546 "This operation isn't promoted!"); 547 548 // See if this has an explicit type specified. 549 std::map<std::pair<unsigned, MVT::SimpleValueType>, 550 MVT::SimpleValueType>::const_iterator PTTI = 551 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 552 if (PTTI != PromoteToType.end()) return PTTI->second; 553 554 assert((VT.isInteger() || VT.isFloatingPoint()) && 555 "Cannot autopromote this type, add it with AddPromotedToType."); 556 557 EVT NVT = VT; 558 do { 559 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 560 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 561 "Didn't find type to promote to!"); 562 } while (!isTypeLegal(NVT) || 563 getOperationAction(Op, NVT) == Promote); 564 return NVT; 565 } 566 567 /// getValueType - Return the EVT corresponding to this LLVM type. 568 /// This is fixed by the LLVM operations except for the pointer size. If 569 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 570 /// counterpart (e.g. structs), otherwise it will assert. 571 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 572 EVT VT = EVT::getEVT(Ty, AllowUnknown); 573 return VT == MVT::iPTR ? PointerTy : VT; 574 } 575 576 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 577 /// function arguments in the caller parameter area. This is the actual 578 /// alignment, not its logarithm. 579 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 580 581 /// getRegisterType - Return the type of registers that this ValueType will 582 /// eventually require. 583 EVT getRegisterType(MVT VT) const { 584 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 585 return RegisterTypeForVT[VT.SimpleTy]; 586 } 587 588 /// getRegisterType - Return the type of registers that this ValueType will 589 /// eventually require. 590 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 591 if (VT.isSimple()) { 592 assert((unsigned)VT.getSimpleVT().SimpleTy < 593 array_lengthof(RegisterTypeForVT)); 594 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 595 } 596 if (VT.isVector()) { 597 EVT VT1, RegisterVT; 598 unsigned NumIntermediates; 599 (void)getVectorTypeBreakdown(Context, VT, VT1, 600 NumIntermediates, RegisterVT); 601 return RegisterVT; 602 } 603 if (VT.isInteger()) { 604 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 605 } 606 assert(0 && "Unsupported extended type!"); 607 return EVT(MVT::Other); // Not reached 608 } 609 610 /// getNumRegisters - Return the number of registers that this ValueType will 611 /// eventually require. This is one for any types promoted to live in larger 612 /// registers, but may be more than one for types (like i64) that are split 613 /// into pieces. For types like i140, which are first promoted then expanded, 614 /// it is the number of registers needed to hold all the bits of the original 615 /// type. For an i140 on a 32 bit machine this means 5 registers. 616 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 617 if (VT.isSimple()) { 618 assert((unsigned)VT.getSimpleVT().SimpleTy < 619 array_lengthof(NumRegistersForVT)); 620 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 621 } 622 if (VT.isVector()) { 623 EVT VT1, VT2; 624 unsigned NumIntermediates; 625 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 626 } 627 if (VT.isInteger()) { 628 unsigned BitWidth = VT.getSizeInBits(); 629 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 630 return (BitWidth + RegWidth - 1) / RegWidth; 631 } 632 assert(0 && "Unsupported extended type!"); 633 return 0; // Not reached 634 } 635 636 /// ShouldShrinkFPConstant - If true, then instruction selection should 637 /// seek to shrink the FP constant of the specified type to a smaller type 638 /// in order to save space and / or reduce runtime. 639 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 640 641 /// hasTargetDAGCombine - If true, the target has custom DAG combine 642 /// transformations that it can perform for the specified node. 643 bool hasTargetDAGCombine(ISD::NodeType NT) const { 644 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 645 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 646 } 647 648 /// This function returns the maximum number of store operations permitted 649 /// to replace a call to llvm.memset. The value is set by the target at the 650 /// performance threshold for such a replacement. 651 /// @brief Get maximum # of store operations permitted for llvm.memset 652 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 653 654 /// This function returns the maximum number of store operations permitted 655 /// to replace a call to llvm.memcpy. The value is set by the target at the 656 /// performance threshold for such a replacement. 657 /// @brief Get maximum # of store operations permitted for llvm.memcpy 658 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 659 660 /// This function returns the maximum number of store operations permitted 661 /// to replace a call to llvm.memmove. The value is set by the target at the 662 /// performance threshold for such a replacement. 663 /// @brief Get maximum # of store operations permitted for llvm.memmove 664 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 665 666 /// This function returns true if the target allows unaligned memory accesses. 667 /// of the specified type. This is used, for example, in situations where an 668 /// array copy/move/set is converted to a sequence of store operations. It's 669 /// use helps to ensure that such replacements don't generate code that causes 670 /// an alignment error (trap) on the target machine. 671 /// @brief Determine if the target supports unaligned memory accesses. 672 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 673 return false; 674 } 675 676 /// This function returns true if the target would benefit from code placement 677 /// optimization. 678 /// @brief Determine if the target should perform code placement optimization. 679 bool shouldOptimizeCodePlacement() const { 680 return benefitFromCodePlacementOpt; 681 } 682 683 /// getOptimalMemOpType - Returns the target specific optimal type for load 684 /// and store operations as a result of memset, memcpy, and memmove 685 /// lowering. If DstAlign is zero that means it's safe to destination 686 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 687 /// means there isn't a need to check it against alignment requirement, 688 /// probably because the source does not need to be loaded. If 689 /// 'NonScalarIntSafe' is true, that means it's safe to return a 690 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 691 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 692 /// constant so it does not need to be loaded. 693 /// It returns EVT::Other if the type should be determined using generic 694 /// target-independent logic. 695 virtual EVT getOptimalMemOpType(uint64_t Size, 696 unsigned DstAlign, unsigned SrcAlign, 697 bool NonScalarIntSafe, bool MemcpyStrSrc, 698 MachineFunction &MF) const { 699 return MVT::Other; 700 } 701 702 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 703 /// to implement llvm.setjmp. 704 bool usesUnderscoreSetJmp() const { 705 return UseUnderscoreSetJmp; 706 } 707 708 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 709 /// to implement llvm.longjmp. 710 bool usesUnderscoreLongJmp() const { 711 return UseUnderscoreLongJmp; 712 } 713 714 /// getStackPointerRegisterToSaveRestore - If a physical register, this 715 /// specifies the register that llvm.savestack/llvm.restorestack should save 716 /// and restore. 717 unsigned getStackPointerRegisterToSaveRestore() const { 718 return StackPointerRegisterToSaveRestore; 719 } 720 721 /// getExceptionAddressRegister - If a physical register, this returns 722 /// the register that receives the exception address on entry to a landing 723 /// pad. 724 unsigned getExceptionAddressRegister() const { 725 return ExceptionPointerRegister; 726 } 727 728 /// getExceptionSelectorRegister - If a physical register, this returns 729 /// the register that receives the exception typeid on entry to a landing 730 /// pad. 731 unsigned getExceptionSelectorRegister() const { 732 return ExceptionSelectorRegister; 733 } 734 735 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 736 /// set, the default is 200) 737 unsigned getJumpBufSize() const { 738 return JumpBufSize; 739 } 740 741 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 742 /// (if never set, the default is 0) 743 unsigned getJumpBufAlignment() const { 744 return JumpBufAlignment; 745 } 746 747 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 748 /// argument. 749 unsigned getMinStackArgumentAlignment() const { 750 return MinStackArgumentAlignment; 751 } 752 753 /// getPrefLoopAlignment - return the preferred loop alignment. 754 /// 755 unsigned getPrefLoopAlignment() const { 756 return PrefLoopAlignment; 757 } 758 759 /// getShouldFoldAtomicFences - return whether the combiner should fold 760 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 761 /// 762 bool getShouldFoldAtomicFences() const { 763 return ShouldFoldAtomicFences; 764 } 765 766 /// getPreIndexedAddressParts - returns true by value, base pointer and 767 /// offset pointer and addressing mode by reference if the node's address 768 /// can be legally represented as pre-indexed load / store address. 769 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 770 SDValue &Offset, 771 ISD::MemIndexedMode &AM, 772 SelectionDAG &DAG) const { 773 return false; 774 } 775 776 /// getPostIndexedAddressParts - returns true by value, base pointer and 777 /// offset pointer and addressing mode by reference if this node can be 778 /// combined with a load / store to form a post-indexed load / store. 779 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 780 SDValue &Base, SDValue &Offset, 781 ISD::MemIndexedMode &AM, 782 SelectionDAG &DAG) const { 783 return false; 784 } 785 786 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 787 /// current function. The returned value is a member of the 788 /// MachineJumpTableInfo::JTEntryKind enum. 789 virtual unsigned getJumpTableEncoding() const; 790 791 virtual const MCExpr * 792 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 793 const MachineBasicBlock *MBB, unsigned uid, 794 MCContext &Ctx) const { 795 assert(0 && "Need to implement this hook if target has custom JTIs"); 796 return 0; 797 } 798 799 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 800 /// jumptable. 801 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 802 SelectionDAG &DAG) const; 803 804 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 805 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 806 /// MCExpr. 807 virtual const MCExpr * 808 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 809 unsigned JTI, MCContext &Ctx) const; 810 811 /// isOffsetFoldingLegal - Return true if folding a constant offset 812 /// with the given GlobalAddress is legal. It is frequently not legal in 813 /// PIC relocation models. 814 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 815 816 /// getFunctionAlignment - Return the Log2 alignment of this function. 817 virtual unsigned getFunctionAlignment(const Function *) const = 0; 818 819 /// getStackCookieLocation - Return true if the target stores stack 820 /// protector cookies at a fixed offset in some non-standard address 821 /// space, and populates the address space and offset as 822 /// appropriate. 823 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const { 824 return false; 825 } 826 827 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be 828 /// used for loads / stores from the global. 829 virtual unsigned getMaximalGlobalOffset() const { 830 return 0; 831 } 832 833 //===--------------------------------------------------------------------===// 834 // TargetLowering Optimization Methods 835 // 836 837 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 838 /// SDValues for returning information from TargetLowering to its clients 839 /// that want to combine 840 struct TargetLoweringOpt { 841 SelectionDAG &DAG; 842 bool LegalTys; 843 bool LegalOps; 844 SDValue Old; 845 SDValue New; 846 847 explicit TargetLoweringOpt(SelectionDAG &InDAG, 848 bool LT, bool LO) : 849 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 850 851 bool LegalTypes() const { return LegalTys; } 852 bool LegalOperations() const { return LegalOps; } 853 854 bool CombineTo(SDValue O, SDValue N) { 855 Old = O; 856 New = N; 857 return true; 858 } 859 860 /// ShrinkDemandedConstant - Check to see if the specified operand of the 861 /// specified instruction is a constant integer. If so, check to see if 862 /// there are any bits set in the constant that are not demanded. If so, 863 /// shrink the constant and return true. 864 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 865 866 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 867 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 868 /// cast, but it could be generalized for targets with other types of 869 /// implicit widening casts. 870 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 871 DebugLoc dl); 872 }; 873 874 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 875 /// DemandedMask bits of the result of Op are ever used downstream. If we can 876 /// use this information to simplify Op, create a new simplified DAG node and 877 /// return true, returning the original and new nodes in Old and New. 878 /// Otherwise, analyze the expression and return a mask of KnownOne and 879 /// KnownZero bits for the expression (used to simplify the caller). 880 /// The KnownZero/One bits may only be accurate for those bits in the 881 /// DemandedMask. 882 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 883 APInt &KnownZero, APInt &KnownOne, 884 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 885 886 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 887 /// Mask are known to be either zero or one and return them in the 888 /// KnownZero/KnownOne bitsets. 889 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 890 const APInt &Mask, 891 APInt &KnownZero, 892 APInt &KnownOne, 893 const SelectionDAG &DAG, 894 unsigned Depth = 0) const; 895 896 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 897 /// targets that want to expose additional information about sign bits to the 898 /// DAG Combiner. 899 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 900 unsigned Depth = 0) const; 901 902 struct DAGCombinerInfo { 903 void *DC; // The DAG Combiner object. 904 bool BeforeLegalize; 905 bool BeforeLegalizeOps; 906 bool CalledByLegalizer; 907 public: 908 SelectionDAG &DAG; 909 910 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 911 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 912 CalledByLegalizer(cl), DAG(dag) {} 913 914 bool isBeforeLegalize() const { return BeforeLegalize; } 915 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 916 bool isCalledByLegalizer() const { return CalledByLegalizer; } 917 918 void AddToWorklist(SDNode *N); 919 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 920 bool AddTo = true); 921 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 922 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 923 924 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 925 }; 926 927 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 928 /// and cc. If it is unable to simplify it, return a null SDValue. 929 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 930 ISD::CondCode Cond, bool foldBooleans, 931 DAGCombinerInfo &DCI, DebugLoc dl) const; 932 933 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 934 /// node is a GlobalAddress + offset. 935 virtual bool 936 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 937 938 /// PerformDAGCombine - This method will be invoked for all target nodes and 939 /// for any target-independent nodes that the target has registered with 940 /// invoke it for. 941 /// 942 /// The semantics are as follows: 943 /// Return Value: 944 /// SDValue.Val == 0 - No change was made 945 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 946 /// otherwise - N should be replaced by the returned Operand. 947 /// 948 /// In addition, methods provided by DAGCombinerInfo may be used to perform 949 /// more complex transformations. 950 /// 951 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 952 953 /// isTypeDesirableForOp - Return true if the target has native support for 954 /// the specified value type and it is 'desirable' to use the type for the 955 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 956 /// instruction encodings are longer and some i16 instructions are slow. 957 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const { 958 // By default, assume all legal types are desirable. 959 return isTypeLegal(VT); 960 } 961 962 /// IsDesirableToPromoteOp - This method query the target whether it is 963 /// beneficial for dag combiner to promote the specified node. If true, it 964 /// should return the desired promotion type by reference. 965 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 966 return false; 967 } 968 969 //===--------------------------------------------------------------------===// 970 // TargetLowering Configuration Methods - These methods should be invoked by 971 // the derived class constructor to configure this object for the target. 972 // 973 974protected: 975 /// setShiftAmountType - Describe the type that should be used for shift 976 /// amounts. This type defaults to the pointer type. 977 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 978 979 /// setBooleanContents - Specify how the target extends the result of a 980 /// boolean value from i1 to a wider type. See getBooleanContents. 981 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 982 983 /// setSchedulingPreference - Specify the target scheduling preference. 984 void setSchedulingPreference(Sched::Preference Pref) { 985 SchedPreferenceInfo = Pref; 986 } 987 988 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 989 /// use _setjmp to implement llvm.setjmp or the non _ version. 990 /// Defaults to false. 991 void setUseUnderscoreSetJmp(bool Val) { 992 UseUnderscoreSetJmp = Val; 993 } 994 995 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 996 /// use _longjmp to implement llvm.longjmp or the non _ version. 997 /// Defaults to false. 998 void setUseUnderscoreLongJmp(bool Val) { 999 UseUnderscoreLongJmp = Val; 1000 } 1001 1002 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 1003 /// specifies the register that llvm.savestack/llvm.restorestack should save 1004 /// and restore. 1005 void setStackPointerRegisterToSaveRestore(unsigned R) { 1006 StackPointerRegisterToSaveRestore = R; 1007 } 1008 1009 /// setExceptionPointerRegister - If set to a physical register, this sets 1010 /// the register that receives the exception address on entry to a landing 1011 /// pad. 1012 void setExceptionPointerRegister(unsigned R) { 1013 ExceptionPointerRegister = R; 1014 } 1015 1016 /// setExceptionSelectorRegister - If set to a physical register, this sets 1017 /// the register that receives the exception typeid on entry to a landing 1018 /// pad. 1019 void setExceptionSelectorRegister(unsigned R) { 1020 ExceptionSelectorRegister = R; 1021 } 1022 1023 /// SelectIsExpensive - Tells the code generator not to expand operations 1024 /// into sequences that use the select operations if possible. 1025 void setSelectIsExpensive() { SelectIsExpensive = true; } 1026 1027 /// setIntDivIsCheap - Tells the code generator that integer divide is 1028 /// expensive, and if possible, should be replaced by an alternate sequence 1029 /// of instructions not containing an integer divide. 1030 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 1031 1032 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 1033 /// srl/add/sra for a signed divide by power of two, and let the target handle 1034 /// it. 1035 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 1036 1037 /// addRegisterClass - Add the specified register class as an available 1038 /// regclass for the specified value type. This indicates the selector can 1039 /// handle values of that class natively. 1040 void addRegisterClass(EVT VT, TargetRegisterClass *RC, 1041 bool isSynthesizable = true) { 1042 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 1043 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 1044 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 1045 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable; 1046 } 1047 1048 /// findRepresentativeClass - Return the largest legal super-reg register class 1049 /// of the register class for the specified type and its associated "cost". 1050 virtual std::pair<const TargetRegisterClass*, uint8_t> 1051 findRepresentativeClass(EVT VT) const; 1052 1053 /// computeRegisterProperties - Once all of the register classes are added, 1054 /// this allows us to compute derived properties we expose. 1055 void computeRegisterProperties(); 1056 1057 /// setOperationAction - Indicate that the specified operation does not work 1058 /// with the specified type and indicate what to do about it. 1059 void setOperationAction(unsigned Op, MVT VT, 1060 LegalizeAction Action) { 1061 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 1062 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 1063 } 1064 1065 /// setLoadExtAction - Indicate that the specified load with extension does 1066 /// not work with the specified type and indicate what to do about it. 1067 void setLoadExtAction(unsigned ExtType, MVT VT, 1068 LegalizeAction Action) { 1069 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 1070 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1071 "Table isn't big enough!"); 1072 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 1073 } 1074 1075 /// setTruncStoreAction - Indicate that the specified truncating store does 1076 /// not work with the specified type and indicate what to do about it. 1077 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1078 LegalizeAction Action) { 1079 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE && 1080 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE && 1081 "Table isn't big enough!"); 1082 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 1083 } 1084 1085 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1086 /// does not work with the specified type and indicate what to do abort 1087 /// it. NOTE: All indexed mode loads are initialized to Expand in 1088 /// TargetLowering.cpp 1089 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1090 LegalizeAction Action) { 1091 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1092 IdxMode < ISD::LAST_INDEXED_MODE && 1093 (unsigned)Action < 0xf && 1094 "Table isn't big enough!"); 1095 // Load action are kept in the upper half. 1096 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1097 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1098 } 1099 1100 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1101 /// does not work with the specified type and indicate what to do about 1102 /// it. NOTE: All indexed mode stores are initialized to Expand in 1103 /// TargetLowering.cpp 1104 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1105 LegalizeAction Action) { 1106 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1107 IdxMode < ISD::LAST_INDEXED_MODE && 1108 (unsigned)Action < 0xf && 1109 "Table isn't big enough!"); 1110 // Store action are kept in the lower half. 1111 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1112 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1113 } 1114 1115 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1116 /// supported on the target and indicate what to do about it. 1117 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1118 LegalizeAction Action) { 1119 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1120 (unsigned)CC < array_lengthof(CondCodeActions) && 1121 "Table isn't big enough!"); 1122 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1123 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1124 } 1125 1126 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1127 /// promotion code defaults to trying a larger integer/fp until it can find 1128 /// one that works. If that default is insufficient, this method can be used 1129 /// by the target to override the default. 1130 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1131 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1132 } 1133 1134 /// setTargetDAGCombine - Targets should invoke this method for each target 1135 /// independent node that they want to provide a custom DAG combiner for by 1136 /// implementing the PerformDAGCombine virtual method. 1137 void setTargetDAGCombine(ISD::NodeType NT) { 1138 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1139 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1140 } 1141 1142 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1143 /// bytes); default is 200 1144 void setJumpBufSize(unsigned Size) { 1145 JumpBufSize = Size; 1146 } 1147 1148 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1149 /// alignment (in bytes); default is 0 1150 void setJumpBufAlignment(unsigned Align) { 1151 JumpBufAlignment = Align; 1152 } 1153 1154 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1155 /// alignment is zero, it means the target does not care about loop alignment. 1156 void setPrefLoopAlignment(unsigned Align) { 1157 PrefLoopAlignment = Align; 1158 } 1159 1160 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1161 /// argument. 1162 void setMinStackArgumentAlignment(unsigned Align) { 1163 MinStackArgumentAlignment = Align; 1164 } 1165 1166 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1167 /// atomic operation intrinsics includes locking. Default is false. 1168 void setShouldFoldAtomicFences(bool fold) { 1169 ShouldFoldAtomicFences = fold; 1170 } 1171 1172public: 1173 //===--------------------------------------------------------------------===// 1174 // Lowering methods - These methods must be implemented by targets so that 1175 // the SelectionDAGLowering code knows how to lower these. 1176 // 1177 1178 /// LowerFormalArguments - This hook must be implemented to lower the 1179 /// incoming (formal) arguments, described by the Ins array, into the 1180 /// specified DAG. The implementation should fill in the InVals array 1181 /// with legal-type argument values, and return the resulting token 1182 /// chain value. 1183 /// 1184 virtual SDValue 1185 LowerFormalArguments(SDValue Chain, 1186 CallingConv::ID CallConv, bool isVarArg, 1187 const SmallVectorImpl<ISD::InputArg> &Ins, 1188 DebugLoc dl, SelectionDAG &DAG, 1189 SmallVectorImpl<SDValue> &InVals) const { 1190 assert(0 && "Not Implemented"); 1191 return SDValue(); // this is here to silence compiler errors 1192 } 1193 1194 /// LowerCallTo - This function lowers an abstract call to a function into an 1195 /// actual call. This returns a pair of operands. The first element is the 1196 /// return value for the function (if RetTy is not VoidTy). The second 1197 /// element is the outgoing token chain. It calls LowerCall to do the actual 1198 /// lowering. 1199 struct ArgListEntry { 1200 SDValue Node; 1201 const Type* Ty; 1202 bool isSExt : 1; 1203 bool isZExt : 1; 1204 bool isInReg : 1; 1205 bool isSRet : 1; 1206 bool isNest : 1; 1207 bool isByVal : 1; 1208 uint16_t Alignment; 1209 1210 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1211 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1212 }; 1213 typedef std::vector<ArgListEntry> ArgListTy; 1214 std::pair<SDValue, SDValue> 1215 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1216 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1217 CallingConv::ID CallConv, bool isTailCall, 1218 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1219 SelectionDAG &DAG, DebugLoc dl) const; 1220 1221 /// LowerCall - This hook must be implemented to lower calls into the 1222 /// the specified DAG. The outgoing arguments to the call are described 1223 /// by the Outs array, and the values to be returned by the call are 1224 /// described by the Ins array. The implementation should fill in the 1225 /// InVals array with legal-type return values from the call, and return 1226 /// the resulting token chain value. 1227 virtual SDValue 1228 LowerCall(SDValue Chain, SDValue Callee, 1229 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 1230 const SmallVectorImpl<ISD::OutputArg> &Outs, 1231 const SmallVectorImpl<SDValue> &OutVals, 1232 const SmallVectorImpl<ISD::InputArg> &Ins, 1233 DebugLoc dl, SelectionDAG &DAG, 1234 SmallVectorImpl<SDValue> &InVals) const { 1235 assert(0 && "Not Implemented"); 1236 return SDValue(); // this is here to silence compiler errors 1237 } 1238 1239 /// CanLowerReturn - This hook should be implemented to check whether the 1240 /// return values described by the Outs array can fit into the return 1241 /// registers. If false is returned, an sret-demotion is performed. 1242 /// 1243 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1244 const SmallVectorImpl<ISD::OutputArg> &Outs, 1245 LLVMContext &Context) const 1246 { 1247 // Return true by default to get preexisting behavior. 1248 return true; 1249 } 1250 1251 /// LowerReturn - This hook must be implemented to lower outgoing 1252 /// return values, described by the Outs array, into the specified 1253 /// DAG. The implementation should return the resulting token chain 1254 /// value. 1255 /// 1256 virtual SDValue 1257 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1258 const SmallVectorImpl<ISD::OutputArg> &Outs, 1259 const SmallVectorImpl<SDValue> &OutVals, 1260 DebugLoc dl, SelectionDAG &DAG) const { 1261 assert(0 && "Not Implemented"); 1262 return SDValue(); // this is here to silence compiler errors 1263 } 1264 1265 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1266 /// to legalize nodes with an illegal operand type but legal result types. 1267 /// It replaces the LowerOperation callback in the type Legalizer. 1268 /// The reason we can not do away with LowerOperation entirely is that 1269 /// LegalizeDAG isn't yet ready to use this callback. 1270 /// TODO: Consider merging with ReplaceNodeResults. 1271 1272 /// The target places new result values for the node in Results (their number 1273 /// and types must exactly match those of the original return values of 1274 /// the node), or leaves Results empty, which indicates that the node is not 1275 /// to be custom lowered after all. 1276 /// The default implementation calls LowerOperation. 1277 virtual void LowerOperationWrapper(SDNode *N, 1278 SmallVectorImpl<SDValue> &Results, 1279 SelectionDAG &DAG) const; 1280 1281 /// LowerOperation - This callback is invoked for operations that are 1282 /// unsupported by the target, which are registered to use 'custom' lowering, 1283 /// and whose defined values are all legal. 1284 /// If the target has no operations that require custom lowering, it need not 1285 /// implement this. The default implementation of this aborts. 1286 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1287 1288 /// ReplaceNodeResults - This callback is invoked when a node result type is 1289 /// illegal for the target, and the operation was registered to use 'custom' 1290 /// lowering for that result type. The target places new result values for 1291 /// the node in Results (their number and types must exactly match those of 1292 /// the original return values of the node), or leaves Results empty, which 1293 /// indicates that the node is not to be custom lowered after all. 1294 /// 1295 /// If the target has no operations that require custom lowering, it need not 1296 /// implement this. The default implementation aborts. 1297 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1298 SelectionDAG &DAG) const { 1299 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1300 } 1301 1302 /// getTargetNodeName() - This method returns the name of a target specific 1303 /// DAG node. 1304 virtual const char *getTargetNodeName(unsigned Opcode) const; 1305 1306 /// createFastISel - This method returns a target specific FastISel object, 1307 /// or null if the target does not support "fast" ISel. 1308 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const { 1309 return 0; 1310 } 1311 1312 //===--------------------------------------------------------------------===// 1313 // Inline Asm Support hooks 1314 // 1315 1316 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1317 /// call to be explicit llvm code if it wants to. This is useful for 1318 /// turning simple inline asms into LLVM intrinsics, which gives the 1319 /// compiler more information about the behavior of the code. 1320 virtual bool ExpandInlineAsm(CallInst *CI) const { 1321 return false; 1322 } 1323 1324 enum ConstraintType { 1325 C_Register, // Constraint represents specific register(s). 1326 C_RegisterClass, // Constraint represents any of register(s) in class. 1327 C_Memory, // Memory constraint. 1328 C_Other, // Something else. 1329 C_Unknown // Unsupported constraint. 1330 }; 1331 1332 /// AsmOperandInfo - This contains information for each constraint that we are 1333 /// lowering. 1334 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1335 /// ConstraintCode - This contains the actual string for the code, like "m". 1336 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1337 /// most closely matches the operand. 1338 std::string ConstraintCode; 1339 1340 /// ConstraintType - Information about the constraint code, e.g. Register, 1341 /// RegisterClass, Memory, Other, Unknown. 1342 TargetLowering::ConstraintType ConstraintType; 1343 1344 /// CallOperandval - If this is the result output operand or a 1345 /// clobber, this is null, otherwise it is the incoming operand to the 1346 /// CallInst. This gets modified as the asm is processed. 1347 Value *CallOperandVal; 1348 1349 /// ConstraintVT - The ValueType for the operand value. 1350 EVT ConstraintVT; 1351 1352 /// isMatchingInputConstraint - Return true of this is an input operand that 1353 /// is a matching constraint like "4". 1354 bool isMatchingInputConstraint() const; 1355 1356 /// getMatchedOperand - If this is an input matching constraint, this method 1357 /// returns the output operand it matches. 1358 unsigned getMatchedOperand() const; 1359 1360 /// Copy constructor for copying from an AsmOperandInfo. 1361 AsmOperandInfo(const AsmOperandInfo &info) 1362 : InlineAsm::ConstraintInfo(info), 1363 ConstraintCode(info.ConstraintCode), 1364 ConstraintType(info.ConstraintType), 1365 CallOperandVal(info.CallOperandVal), 1366 ConstraintVT(info.ConstraintVT) { 1367 } 1368 1369 /// Copy constructor for copying from a ConstraintInfo. 1370 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1371 : InlineAsm::ConstraintInfo(info), 1372 ConstraintType(TargetLowering::C_Unknown), 1373 CallOperandVal(0), ConstraintVT(MVT::Other) { 1374 } 1375 }; 1376 1377 /// ParseConstraints - Split up the constraint string from the inline 1378 /// assembly value into the specific constraints and their prefixes, 1379 /// and also tie in the associated operand values. 1380 /// If this returns an empty vector, and if the constraint string itself 1381 /// isn't empty, there was an error parsing. 1382 virtual std::vector<AsmOperandInfo> ParseConstraints( 1383 ImmutableCallSite CS) const; 1384 1385 /// Examine constraint type and operand type and determine a weight value, 1386 /// where: -1 = invalid match, and 0 = so-so match to 5 = good match. 1387 /// The operand object must already have been set up with the operand type. 1388 virtual int getMultipleConstraintMatchWeight( 1389 AsmOperandInfo &info, int maIndex) const; 1390 1391 /// Examine constraint string and operand type and determine a weight value, 1392 /// where: -1 = invalid match, and 0 = so-so match to 3 = good match. 1393 /// The operand object must already have been set up with the operand type. 1394 virtual int getSingleConstraintMatchWeight( 1395 AsmOperandInfo &info, const char *constraint) const; 1396 1397 /// ComputeConstraintToUse - Determines the constraint code and constraint 1398 /// type to use for the specific AsmOperandInfo, setting 1399 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1400 /// being passed in is available, it can be passed in as Op, otherwise an 1401 /// empty SDValue can be passed. 1402 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1403 SDValue Op, 1404 SelectionDAG *DAG = 0) const; 1405 1406 /// getConstraintType - Given a constraint, return the type of constraint it 1407 /// is for this target. 1408 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1409 1410 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1411 /// return a list of registers that can be used to satisfy the constraint. 1412 /// This should only be used for C_RegisterClass constraints. 1413 virtual std::vector<unsigned> 1414 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1415 EVT VT) const; 1416 1417 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1418 /// {edx}), return the register number and the register class for the 1419 /// register. 1420 /// 1421 /// Given a register class constraint, like 'r', if this corresponds directly 1422 /// to an LLVM register class, return a register of 0 and the register class 1423 /// pointer. 1424 /// 1425 /// This should only be used for C_Register constraints. On error, 1426 /// this returns a register number of 0 and a null register class pointer.. 1427 virtual std::pair<unsigned, const TargetRegisterClass*> 1428 getRegForInlineAsmConstraint(const std::string &Constraint, 1429 EVT VT) const; 1430 1431 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1432 /// with another that has more specific requirements based on the type of the 1433 /// corresponding operand. This returns null if there is no replacement to 1434 /// make. 1435 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1436 1437 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1438 /// vector. If it is invalid, don't add anything to Ops. 1439 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1440 std::vector<SDValue> &Ops, 1441 SelectionDAG &DAG) const; 1442 1443 //===--------------------------------------------------------------------===// 1444 // Instruction Emitting Hooks 1445 // 1446 1447 // EmitInstrWithCustomInserter - This method should be implemented by targets 1448 // that mark instructions with the 'usesCustomInserter' flag. These 1449 // instructions are special in various ways, which require special support to 1450 // insert. The specified MachineInstr is created but not inserted into any 1451 // basic blocks, and this method is called to expand it into a sequence of 1452 // instructions, potentially also creating new basic blocks and control flow. 1453 virtual MachineBasicBlock * 1454 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 1455 1456 //===--------------------------------------------------------------------===// 1457 // Addressing mode description hooks (used by LSR etc). 1458 // 1459 1460 /// AddrMode - This represents an addressing mode of: 1461 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1462 /// If BaseGV is null, there is no BaseGV. 1463 /// If BaseOffs is zero, there is no base offset. 1464 /// If HasBaseReg is false, there is no base register. 1465 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1466 /// no scale. 1467 /// 1468 struct AddrMode { 1469 GlobalValue *BaseGV; 1470 int64_t BaseOffs; 1471 bool HasBaseReg; 1472 int64_t Scale; 1473 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1474 }; 1475 1476 /// isLegalAddressingMode - Return true if the addressing mode represented by 1477 /// AM is legal for this target, for a load/store of the specified type. 1478 /// The type may be VoidTy, in which case only return true if the addressing 1479 /// mode is legal for a load/store of any legal type. 1480 /// TODO: Handle pre/postinc as well. 1481 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1482 1483 /// isTruncateFree - Return true if it's free to truncate a value of 1484 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1485 /// register EAX to i16 by referencing its sub-register AX. 1486 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1487 return false; 1488 } 1489 1490 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1491 return false; 1492 } 1493 1494 /// isZExtFree - Return true if any actual instruction that defines a 1495 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1496 /// register. This does not necessarily include registers defined in 1497 /// unknown ways, such as incoming arguments, or copies from unknown 1498 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1499 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1500 /// all instructions that define 32-bit values implicit zero-extend the 1501 /// result out to 64 bits. 1502 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1503 return false; 1504 } 1505 1506 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1507 return false; 1508 } 1509 1510 /// isNarrowingProfitable - Return true if it's profitable to narrow 1511 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1512 /// from i32 to i8 but not from i32 to i16. 1513 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1514 return false; 1515 } 1516 1517 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1518 /// icmp immediate, that is the target has icmp instructions which can compare 1519 /// a register against the immediate without having to materialize the 1520 /// immediate into a register. 1521 virtual bool isLegalICmpImmediate(int64_t Imm) const { 1522 return true; 1523 } 1524 1525 //===--------------------------------------------------------------------===// 1526 // Div utility functions 1527 // 1528 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1529 std::vector<SDNode*>* Created) const; 1530 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1531 std::vector<SDNode*>* Created) const; 1532 1533 1534 //===--------------------------------------------------------------------===// 1535 // Runtime Library hooks 1536 // 1537 1538 /// setLibcallName - Rename the default libcall routine name for the specified 1539 /// libcall. 1540 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1541 LibcallRoutineNames[Call] = Name; 1542 } 1543 1544 /// getLibcallName - Get the libcall routine name for the specified libcall. 1545 /// 1546 const char *getLibcallName(RTLIB::Libcall Call) const { 1547 return LibcallRoutineNames[Call]; 1548 } 1549 1550 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1551 /// result of the comparison libcall against zero. 1552 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1553 CmpLibcallCCs[Call] = CC; 1554 } 1555 1556 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1557 /// the comparison libcall against zero. 1558 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1559 return CmpLibcallCCs[Call]; 1560 } 1561 1562 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1563 /// specified libcall. 1564 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1565 LibcallCallingConvs[Call] = CC; 1566 } 1567 1568 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1569 /// specified libcall. 1570 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1571 return LibcallCallingConvs[Call]; 1572 } 1573 1574private: 1575 const TargetMachine &TM; 1576 const TargetData *TD; 1577 const TargetLoweringObjectFile &TLOF; 1578 1579 /// PointerTy - The type to use for pointers, usually i32 or i64. 1580 /// 1581 MVT PointerTy; 1582 1583 /// IsLittleEndian - True if this is a little endian target. 1584 /// 1585 bool IsLittleEndian; 1586 1587 /// SelectIsExpensive - Tells the code generator not to expand operations 1588 /// into sequences that use the select operations if possible. 1589 bool SelectIsExpensive; 1590 1591 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1592 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1593 /// a real cost model is in place. If we ever optimize for size, this will be 1594 /// set to true unconditionally. 1595 bool IntDivIsCheap; 1596 1597 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1598 /// srl/add/sra for a signed divide by power of two, and let the target handle 1599 /// it. 1600 bool Pow2DivIsCheap; 1601 1602 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1603 /// llvm.setjmp. Defaults to false. 1604 bool UseUnderscoreSetJmp; 1605 1606 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1607 /// llvm.longjmp. Defaults to false. 1608 bool UseUnderscoreLongJmp; 1609 1610 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1611 /// PointerTy is. 1612 MVT ShiftAmountTy; 1613 1614 /// BooleanContents - Information about the contents of the high-bits in 1615 /// boolean values held in a type wider than i1. See getBooleanContents. 1616 BooleanContent BooleanContents; 1617 1618 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1619 /// total cycles or lowest register usage. 1620 Sched::Preference SchedPreferenceInfo; 1621 1622 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1623 unsigned JumpBufSize; 1624 1625 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1626 /// buffers 1627 unsigned JumpBufAlignment; 1628 1629 /// MinStackArgumentAlignment - The minimum alignment that any argument 1630 /// on the stack needs to have. 1631 /// 1632 unsigned MinStackArgumentAlignment; 1633 1634 /// PrefLoopAlignment - The perferred loop alignment. 1635 /// 1636 unsigned PrefLoopAlignment; 1637 1638 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1639 /// be folded into the enclosed atomic intrinsic instruction by the 1640 /// combiner. 1641 bool ShouldFoldAtomicFences; 1642 1643 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1644 /// specifies the register that llvm.savestack/llvm.restorestack should save 1645 /// and restore. 1646 unsigned StackPointerRegisterToSaveRestore; 1647 1648 /// ExceptionPointerRegister - If set to a physical register, this specifies 1649 /// the register that receives the exception address on entry to a landing 1650 /// pad. 1651 unsigned ExceptionPointerRegister; 1652 1653 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1654 /// the register that receives the exception typeid on entry to a landing 1655 /// pad. 1656 unsigned ExceptionSelectorRegister; 1657 1658 /// RegClassForVT - This indicates the default register class to use for 1659 /// each ValueType the target supports natively. 1660 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1661 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1662 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1663 1664 /// RepRegClassForVT - This indicates the "representative" register class to 1665 /// use for each ValueType the target supports natively. This information is 1666 /// used by the scheduler to track register pressure. By default, the 1667 /// representative register class is the largest legal super-reg register 1668 /// class of the register class of the specified type. e.g. On x86, i8, i16, 1669 /// and i32's representative class would be GR32. 1670 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1671 1672 /// RepRegClassCostForVT - This indicates the "cost" of the "representative" 1673 /// register class for each ValueType. The cost is used by the scheduler to 1674 /// approximate register pressure. 1675 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1676 1677 /// Synthesizable indicates whether it is OK for the compiler to create new 1678 /// operations using this type. All Legal types are Synthesizable except 1679 /// MMX types on X86. Non-Legal types are not Synthesizable. 1680 bool Synthesizable[MVT::LAST_VALUETYPE]; 1681 1682 /// TransformToType - For any value types we are promoting or expanding, this 1683 /// contains the value type that we are changing to. For Expanded types, this 1684 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1685 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1686 /// by the system, this holds the same type (e.g. i32 -> i32). 1687 EVT TransformToType[MVT::LAST_VALUETYPE]; 1688 1689 /// OpActions - For each operation and each value type, keep a LegalizeAction 1690 /// that indicates how instruction selection should deal with the operation. 1691 /// Most operations are Legal (aka, supported natively by the target), but 1692 /// operations that are not should be described. Note that operations on 1693 /// non-legal value types are not described here. 1694 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1695 1696 /// LoadExtActions - For each load extension type and each value type, 1697 /// keep a LegalizeAction that indicates how instruction selection should deal 1698 /// with a load of a specific value type and extension type. 1699 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1700 1701 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1702 /// indicates whether a truncating store of a specific value type and 1703 /// truncating type is legal. 1704 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1705 1706 /// IndexedModeActions - For each indexed mode and each value type, 1707 /// keep a pair of LegalizeAction that indicates how instruction 1708 /// selection should deal with the load / store. The first dimension is the 1709 /// value_type for the reference. The second dimension represents the various 1710 /// modes for load store. 1711 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1712 1713 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1714 /// LegalizeAction that indicates how instruction selection should 1715 /// deal with the condition code. 1716 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1717 1718 ValueTypeActionImpl ValueTypeActions; 1719 1720 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1721 1722 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1723 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1724 /// which sets a bit in this array. 1725 unsigned char 1726 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1727 1728 /// PromoteToType - For operations that must be promoted to a specific type, 1729 /// this holds the destination type. This map should be sparse, so don't hold 1730 /// it as an array. 1731 /// 1732 /// Targets add entries to this map with AddPromotedToType(..), clients access 1733 /// this with getTypeToPromoteTo(..). 1734 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1735 PromoteToType; 1736 1737 /// LibcallRoutineNames - Stores the name each libcall. 1738 /// 1739 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1740 1741 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1742 /// of each of the comparison libcall against zero. 1743 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1744 1745 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1746 /// libcall. 1747 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1748 1749protected: 1750 /// When lowering \@llvm.memset this field specifies the maximum number of 1751 /// store operations that may be substituted for the call to memset. Targets 1752 /// must set this value based on the cost threshold for that target. Targets 1753 /// should assume that the memset will be done using as many of the largest 1754 /// store operations first, followed by smaller ones, if necessary, per 1755 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1756 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1757 /// store. This only applies to setting a constant array of a constant size. 1758 /// @brief Specify maximum number of store instructions per memset call. 1759 unsigned maxStoresPerMemset; 1760 1761 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1762 /// store operations that may be substituted for a call to memcpy. Targets 1763 /// must set this value based on the cost threshold for that target. Targets 1764 /// should assume that the memcpy will be done using as many of the largest 1765 /// store operations first, followed by smaller ones, if necessary, per 1766 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1767 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1768 /// and one 1-byte store. This only applies to copying a constant array of 1769 /// constant size. 1770 /// @brief Specify maximum bytes of store instructions per memcpy call. 1771 unsigned maxStoresPerMemcpy; 1772 1773 /// When lowering \@llvm.memmove this field specifies the maximum number of 1774 /// store instructions that may be substituted for a call to memmove. Targets 1775 /// must set this value based on the cost threshold for that target. Targets 1776 /// should assume that the memmove will be done using as many of the largest 1777 /// store operations first, followed by smaller ones, if necessary, per 1778 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1779 /// with 8-bit alignment would result in nine 1-byte stores. This only 1780 /// applies to copying a constant array of constant size. 1781 /// @brief Specify maximum bytes of store instructions per memmove call. 1782 unsigned maxStoresPerMemmove; 1783 1784 /// This field specifies whether the target can benefit from code placement 1785 /// optimization. 1786 bool benefitFromCodePlacementOpt; 1787 1788private: 1789 /// isLegalRC - Return true if the value types that can be represented by the 1790 /// specified register class are all legal. 1791 bool isLegalRC(const TargetRegisterClass *RC) const; 1792 1793 /// hasLegalSuperRegRegClasses - Return true if the specified register class 1794 /// has one or more super-reg register classes that are legal. 1795 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const; 1796}; 1797 1798/// GetReturnInfo - Given an LLVM IR type and return type attributes, 1799/// compute the return value EVTs and flags, and optionally also 1800/// the offsets, if the return value is being lowered to memory. 1801void GetReturnInfo(const Type* ReturnType, Attributes attr, 1802 SmallVectorImpl<ISD::OutputArg> &Outs, 1803 const TargetLowering &TLI, 1804 SmallVectorImpl<uint64_t> *Offsets = 0); 1805 1806} // end llvm namespace 1807 1808#endif 1809