TargetLowering.h revision f2e19d5dcfa13472493bb18339555686182b7df9
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/InlineAsm.h" 26#include "llvm/CodeGen/SelectionDAGNodes.h" 27#include "llvm/CodeGen/RuntimeLibcalls.h" 28#include "llvm/ADT/APFloat.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallSet.h" 31#include "llvm/ADT/SmallVector.h" 32#include "llvm/ADT/STLExtras.h" 33#include "llvm/Support/DebugLoc.h" 34#include "llvm/Target/TargetMachine.h" 35#include <climits> 36#include <map> 37#include <vector> 38 39namespace llvm { 40 class AllocaInst; 41 class CallInst; 42 class Function; 43 class FastISel; 44 class MachineBasicBlock; 45 class MachineFunction; 46 class MachineFrameInfo; 47 class MachineInstr; 48 class MachineModuleInfo; 49 class DwarfWriter; 50 class SDNode; 51 class SDValue; 52 class SelectionDAG; 53 class TargetData; 54 class TargetMachine; 55 class TargetRegisterClass; 56 class TargetSubtarget; 57 class Value; 58 59 // FIXME: should this be here? 60 namespace TLSModel { 61 enum Model { 62 GeneralDynamic, 63 LocalDynamic, 64 InitialExec, 65 LocalExec 66 }; 67 } 68 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 69 70 71//===----------------------------------------------------------------------===// 72/// TargetLowering - This class defines information used to lower LLVM code to 73/// legal SelectionDAG operators that the target instruction selector can accept 74/// natively. 75/// 76/// This class also defines callbacks that targets must implement to lower 77/// target-specific constructs to SelectionDAG operators. 78/// 79class TargetLowering { 80public: 81 /// LegalizeAction - This enum indicates whether operations are valid for a 82 /// target, and if not, what action should be used to make them valid. 83 enum LegalizeAction { 84 Legal, // The target natively supports this operation. 85 Promote, // This operation should be executed in a larger type. 86 Expand, // Try to expand this to other ops, otherwise use a libcall. 87 Custom // Use the LowerOperation hook to implement custom lowering. 88 }; 89 90 enum OutOfRangeShiftAmount { 91 Undefined, // Oversized shift amounts are undefined (default). 92 Mask, // Shift amounts are auto masked (anded) to value size. 93 Extend // Oversized shift pulls in zeros or sign bits. 94 }; 95 96 enum BooleanContent { // How the target represents true/false values. 97 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 98 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 99 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 100 }; 101 102 enum SchedPreference { 103 SchedulingForLatency, // Scheduling for shortest total latency. 104 SchedulingForRegPressure // Scheduling for lowest register pressure. 105 }; 106 107 explicit TargetLowering(TargetMachine &TM); 108 virtual ~TargetLowering(); 109 110 TargetMachine &getTargetMachine() const { return TM; } 111 const TargetData *getTargetData() const { return TD; } 112 113 bool isBigEndian() const { return !IsLittleEndian; } 114 bool isLittleEndian() const { return IsLittleEndian; } 115 MVT getPointerTy() const { return PointerTy; } 116 MVT getShiftAmountTy() const { return ShiftAmountTy; } 117 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 118 119 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 120 /// codegen. 121 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 122 123 /// isSelectExpensive - Return true if the select operation is expensive for 124 /// this target. 125 bool isSelectExpensive() const { return SelectIsExpensive; } 126 127 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 128 /// a sequence of several shifts, adds, and multiplies for this target. 129 bool isIntDivCheap() const { return IntDivIsCheap; } 130 131 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 132 /// srl/add/sra. 133 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 134 135 /// getSetCCResultType - Return the ValueType of the result of SETCC 136 /// operations. Also used to obtain the target's preferred type for 137 /// the condition operand of SELECT and BRCOND nodes. In the case of 138 /// BRCOND the argument passed is MVT::Other since there are no other 139 /// operands to get a type hint from. 140 virtual MVT getSetCCResultType(MVT VT) const; 141 142 /// getBooleanContents - For targets without i1 registers, this gives the 143 /// nature of the high-bits of boolean values held in types wider than i1. 144 /// "Boolean values" are special true/false values produced by nodes like 145 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 146 /// Not to be confused with general values promoted from i1. 147 BooleanContent getBooleanContents() const { return BooleanContents;} 148 149 /// getSchedulingPreference - Return target scheduling preference. 150 SchedPreference getSchedulingPreference() const { 151 return SchedPreferenceInfo; 152 } 153 154 /// getRegClassFor - Return the register class that should be used for the 155 /// specified value type. This may only be called on legal types. 156 TargetRegisterClass *getRegClassFor(MVT VT) const { 157 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 158 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()]; 159 assert(RC && "This value type is not natively supported!"); 160 return RC; 161 } 162 163 /// isTypeLegal - Return true if the target has native support for the 164 /// specified value type. This means that it has a register that directly 165 /// holds it without promotions or expansions. 166 bool isTypeLegal(MVT VT) const { 167 assert(!VT.isSimple() || 168 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 169 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0; 170 } 171 172 class ValueTypeActionImpl { 173 /// ValueTypeActions - This is a bitvector that contains two bits for each 174 /// value type, where the two bits correspond to the LegalizeAction enum. 175 /// This can be queried with "getTypeAction(VT)". 176 /// dimension by (MVT::MAX_ALLOWED_LAST_VALUETYPE/32) * 2 177 uint32_t ValueTypeActions[4]; 178 public: 179 ValueTypeActionImpl() { 180 ValueTypeActions[0] = ValueTypeActions[1] = 0; 181 ValueTypeActions[2] = ValueTypeActions[3] = 0; 182 } 183 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 184 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 185 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 186 ValueTypeActions[2] = RHS.ValueTypeActions[2]; 187 ValueTypeActions[3] = RHS.ValueTypeActions[3]; 188 } 189 190 LegalizeAction getTypeAction(MVT VT) const { 191 if (VT.isExtended()) { 192 if (VT.isVector()) { 193 return VT.isPow2VectorType() ? Expand : Promote; 194 } 195 if (VT.isInteger()) 196 // First promote to a power-of-two size, then expand if necessary. 197 return VT == VT.getRoundIntegerType() ? Expand : Promote; 198 assert(0 && "Unsupported extended type!"); 199 return Legal; 200 } 201 unsigned I = VT.getSimpleVT(); 202 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 203 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 204 } 205 void setTypeAction(MVT VT, LegalizeAction Action) { 206 unsigned I = VT.getSimpleVT(); 207 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 208 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 209 } 210 }; 211 212 const ValueTypeActionImpl &getValueTypeActions() const { 213 return ValueTypeActions; 214 } 215 216 /// getTypeAction - Return how we should legalize values of this type, either 217 /// it is already legal (return 'Legal') or we need to promote it to a larger 218 /// type (return 'Promote'), or we need to expand it into multiple registers 219 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 220 LegalizeAction getTypeAction(MVT VT) const { 221 return ValueTypeActions.getTypeAction(VT); 222 } 223 224 /// getTypeToTransformTo - For types supported by the target, this is an 225 /// identity function. For types that must be promoted to larger types, this 226 /// returns the larger type to promote to. For integer types that are larger 227 /// than the largest integer register, this contains one step in the expansion 228 /// to get to the smaller register. For illegal floating point types, this 229 /// returns the integer type to transform to. 230 MVT getTypeToTransformTo(MVT VT) const { 231 if (VT.isSimple()) { 232 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType)); 233 MVT NVT = TransformToType[VT.getSimpleVT()]; 234 assert(getTypeAction(NVT) != Promote && 235 "Promote may not follow Expand or Promote"); 236 return NVT; 237 } 238 239 if (VT.isVector()) { 240 MVT NVT = VT.getPow2VectorType(); 241 if (NVT == VT) { 242 // Vector length is a power of 2 - split to half the size. 243 unsigned NumElts = VT.getVectorNumElements(); 244 MVT EltVT = VT.getVectorElementType(); 245 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2); 246 } 247 // Promote to a power of two size, avoiding multi-step promotion. 248 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 249 } else if (VT.isInteger()) { 250 MVT NVT = VT.getRoundIntegerType(); 251 if (NVT == VT) 252 // Size is a power of two - expand to half the size. 253 return MVT::getIntegerVT(VT.getSizeInBits() / 2); 254 else 255 // Promote to a power of two size, avoiding multi-step promotion. 256 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; 257 } 258 assert(0 && "Unsupported extended type!"); 259 return MVT(); // Not reached 260 } 261 262 /// getTypeToExpandTo - For types supported by the target, this is an 263 /// identity function. For types that must be expanded (i.e. integer types 264 /// that are larger than the largest integer register or illegal floating 265 /// point types), this returns the largest legal type it will be expanded to. 266 MVT getTypeToExpandTo(MVT VT) const { 267 assert(!VT.isVector()); 268 while (true) { 269 switch (getTypeAction(VT)) { 270 case Legal: 271 return VT; 272 case Expand: 273 VT = getTypeToTransformTo(VT); 274 break; 275 default: 276 assert(false && "Type is not legal nor is it to be expanded!"); 277 return VT; 278 } 279 } 280 return VT; 281 } 282 283 /// getVectorTypeBreakdown - Vector types are broken down into some number of 284 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 285 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 286 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 287 /// 288 /// This method returns the number of registers needed, and the VT for each 289 /// register. It also returns the VT and quantity of the intermediate values 290 /// before they are promoted/expanded. 291 /// 292 unsigned getVectorTypeBreakdown(MVT VT, 293 MVT &IntermediateVT, 294 unsigned &NumIntermediates, 295 MVT &RegisterVT) const; 296 297 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 298 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 299 /// this is the case, it returns true and store the intrinsic 300 /// information into the IntrinsicInfo that was passed to the function. 301 typedef struct IntrinsicInfo { 302 unsigned opc; // target opcode 303 MVT memVT; // memory VT 304 const Value* ptrVal; // value representing memory location 305 int offset; // offset off of ptrVal 306 unsigned align; // alignment 307 bool vol; // is volatile? 308 bool readMem; // reads memory? 309 bool writeMem; // writes memory? 310 } IntrinisicInfo; 311 312 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 313 CallInst &I, unsigned Intrinsic) { 314 return false; 315 } 316 317 /// getWidenVectorType: given a vector type, returns the type to widen to 318 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 319 /// If there is no vector type that we want to widen to, returns MVT::Other 320 /// When and were to widen is target dependent based on the cost of 321 /// scalarizing vs using the wider vector type. 322 virtual MVT getWidenVectorType(MVT VT) const; 323 324 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator; 325 legal_fpimm_iterator legal_fpimm_begin() const { 326 return LegalFPImmediates.begin(); 327 } 328 legal_fpimm_iterator legal_fpimm_end() const { 329 return LegalFPImmediates.end(); 330 } 331 332 /// isShuffleMaskLegal - Targets can use this to indicate that they only 333 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 334 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 335 /// are assumed to be legal. 336 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 337 MVT VT) const { 338 return true; 339 } 340 341 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 342 /// used by Targets can use this to indicate if there is a suitable 343 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 344 /// pool entry. 345 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 346 MVT VT) const { 347 return false; 348 } 349 350 /// getOperationAction - Return how this operation should be treated: either 351 /// it is legal, needs to be promoted to a larger size, needs to be 352 /// expanded to some other code sequence, or the target has a custom expander 353 /// for it. 354 LegalizeAction getOperationAction(unsigned Op, MVT VT) const { 355 if (VT.isExtended()) return Expand; 356 assert(Op < array_lengthof(OpActions) && 357 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*8 && 358 "Table isn't big enough!"); 359 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3); 360 } 361 362 /// isOperationLegalOrCustom - Return true if the specified operation is 363 /// legal on this target or can be made legal with custom lowering. This 364 /// is used to help guide high-level lowering decisions. 365 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const { 366 return (VT == MVT::Other || isTypeLegal(VT)) && 367 (getOperationAction(Op, VT) == Legal || 368 getOperationAction(Op, VT) == Custom); 369 } 370 371 /// isOperationLegal - Return true if the specified operation is legal on this 372 /// target. 373 bool isOperationLegal(unsigned Op, MVT VT) const { 374 return (VT == MVT::Other || isTypeLegal(VT)) && 375 getOperationAction(Op, VT) == Legal; 376 } 377 378 /// getLoadExtAction - Return how this load with extension should be treated: 379 /// either it is legal, needs to be promoted to a larger size, needs to be 380 /// expanded to some other code sequence, or the target has a custom expander 381 /// for it. 382 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const { 383 assert(LType < array_lengthof(LoadExtActions) && 384 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 385 "Table isn't big enough!"); 386 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3); 387 } 388 389 /// isLoadExtLegal - Return true if the specified load with extension is legal 390 /// on this target. 391 bool isLoadExtLegal(unsigned LType, MVT VT) const { 392 return VT.isSimple() && 393 (getLoadExtAction(LType, VT) == Legal || 394 getLoadExtAction(LType, VT) == Custom); 395 } 396 397 /// getTruncStoreAction - Return how this store with truncation should be 398 /// treated: either it is legal, needs to be promoted to a larger size, needs 399 /// to be expanded to some other code sequence, or the target has a custom 400 /// expander for it. 401 LegalizeAction getTruncStoreAction(MVT ValVT, 402 MVT MemVT) const { 403 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 404 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 405 "Table isn't big enough!"); 406 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >> 407 (2*MemVT.getSimpleVT())) & 3); 408 } 409 410 /// isTruncStoreLegal - Return true if the specified store with truncation is 411 /// legal on this target. 412 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const { 413 return isTypeLegal(ValVT) && MemVT.isSimple() && 414 (getTruncStoreAction(ValVT, MemVT) == Legal || 415 getTruncStoreAction(ValVT, MemVT) == Custom); 416 } 417 418 /// getIndexedLoadAction - Return how the indexed load should be treated: 419 /// either it is legal, needs to be promoted to a larger size, needs to be 420 /// expanded to some other code sequence, or the target has a custom expander 421 /// for it. 422 LegalizeAction 423 getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 424 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) && 425 ((unsigned)VT.getSimpleVT()) < MVT::LAST_VALUETYPE && 426 "Table isn't big enough!"); 427 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode])); 428 } 429 430 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 431 /// on this target. 432 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const { 433 return VT.isSimple() && 434 (getIndexedLoadAction(IdxMode, VT) == Legal || 435 getIndexedLoadAction(IdxMode, VT) == Custom); 436 } 437 438 /// getIndexedStoreAction - Return how the indexed store should be treated: 439 /// either it is legal, needs to be promoted to a larger size, needs to be 440 /// expanded to some other code sequence, or the target has a custom expander 441 /// for it. 442 LegalizeAction 443 getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 444 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) && 445 (unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE && 446 "Table isn't big enough!"); 447 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode])); 448 } 449 450 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 451 /// on this target. 452 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const { 453 return VT.isSimple() && 454 (getIndexedStoreAction(IdxMode, VT) == Legal || 455 getIndexedStoreAction(IdxMode, VT) == Custom); 456 } 457 458 /// getConvertAction - Return how the conversion should be treated: 459 /// either it is legal, needs to be promoted to a larger size, needs to be 460 /// expanded to some other code sequence, or the target has a custom expander 461 /// for it. 462 LegalizeAction 463 getConvertAction(MVT FromVT, MVT ToVT) const { 464 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 465 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 466 "Table isn't big enough!"); 467 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >> 468 (2*ToVT.getSimpleVT())) & 3); 469 } 470 471 /// isConvertLegal - Return true if the specified conversion is legal 472 /// on this target. 473 bool isConvertLegal(MVT FromVT, MVT ToVT) const { 474 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 475 (getConvertAction(FromVT, ToVT) == Legal || 476 getConvertAction(FromVT, ToVT) == Custom); 477 } 478 479 /// getCondCodeAction - Return how the condition code should be treated: 480 /// either it is legal, needs to be expanded to some other code sequence, 481 /// or the target has a custom expander for it. 482 LegalizeAction 483 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 484 assert((unsigned)CC < array_lengthof(CondCodeActions) && 485 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 486 "Table isn't big enough!"); 487 LegalizeAction Action = (LegalizeAction) 488 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3); 489 assert(Action != Promote && "Can't promote condition code!"); 490 return Action; 491 } 492 493 /// isCondCodeLegal - Return true if the specified condition code is legal 494 /// on this target. 495 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 496 return getCondCodeAction(CC, VT) == Legal || 497 getCondCodeAction(CC, VT) == Custom; 498 } 499 500 501 /// getTypeToPromoteTo - If the action for this operation is to promote, this 502 /// method returns the ValueType to promote to. 503 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 504 assert(getOperationAction(Op, VT) == Promote && 505 "This operation isn't promoted!"); 506 507 // See if this has an explicit type specified. 508 std::map<std::pair<unsigned, MVT::SimpleValueType>, 509 MVT::SimpleValueType>::const_iterator PTTI = 510 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT())); 511 if (PTTI != PromoteToType.end()) return PTTI->second; 512 513 assert((VT.isInteger() || VT.isFloatingPoint()) && 514 "Cannot autopromote this type, add it with AddPromotedToType."); 515 516 MVT NVT = VT; 517 do { 518 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1); 519 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 520 "Didn't find type to promote to!"); 521 } while (!isTypeLegal(NVT) || 522 getOperationAction(Op, NVT) == Promote); 523 return NVT; 524 } 525 526 /// getValueType - Return the MVT corresponding to this LLVM type. 527 /// This is fixed by the LLVM operations except for the pointer size. If 528 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 529 /// counterpart (e.g. structs), otherwise it will assert. 530 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 531 MVT VT = MVT::getMVT(Ty, AllowUnknown); 532 return VT == MVT::iPTR ? PointerTy : VT; 533 } 534 535 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 536 /// function arguments in the caller parameter area. This is the actual 537 /// alignment, not its logarithm. 538 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 539 540 /// getRegisterType - Return the type of registers that this ValueType will 541 /// eventually require. 542 MVT getRegisterType(MVT VT) const { 543 if (VT.isSimple()) { 544 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT)); 545 return RegisterTypeForVT[VT.getSimpleVT()]; 546 } 547 if (VT.isVector()) { 548 MVT VT1, RegisterVT; 549 unsigned NumIntermediates; 550 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); 551 return RegisterVT; 552 } 553 if (VT.isInteger()) { 554 return getRegisterType(getTypeToTransformTo(VT)); 555 } 556 assert(0 && "Unsupported extended type!"); 557 return MVT(); // Not reached 558 } 559 560 /// getNumRegisters - Return the number of registers that this ValueType will 561 /// eventually require. This is one for any types promoted to live in larger 562 /// registers, but may be more than one for types (like i64) that are split 563 /// into pieces. For types like i140, which are first promoted then expanded, 564 /// it is the number of registers needed to hold all the bits of the original 565 /// type. For an i140 on a 32 bit machine this means 5 registers. 566 unsigned getNumRegisters(MVT VT) const { 567 if (VT.isSimple()) { 568 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT)); 569 return NumRegistersForVT[VT.getSimpleVT()]; 570 } 571 if (VT.isVector()) { 572 MVT VT1, VT2; 573 unsigned NumIntermediates; 574 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); 575 } 576 if (VT.isInteger()) { 577 unsigned BitWidth = VT.getSizeInBits(); 578 unsigned RegWidth = getRegisterType(VT).getSizeInBits(); 579 return (BitWidth + RegWidth - 1) / RegWidth; 580 } 581 assert(0 && "Unsupported extended type!"); 582 return 0; // Not reached 583 } 584 585 /// ShouldShrinkFPConstant - If true, then instruction selection should 586 /// seek to shrink the FP constant of the specified type to a smaller type 587 /// in order to save space and / or reduce runtime. 588 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; } 589 590 /// hasTargetDAGCombine - If true, the target has custom DAG combine 591 /// transformations that it can perform for the specified node. 592 bool hasTargetDAGCombine(ISD::NodeType NT) const { 593 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 594 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 595 } 596 597 /// This function returns the maximum number of store operations permitted 598 /// to replace a call to llvm.memset. The value is set by the target at the 599 /// performance threshold for such a replacement. 600 /// @brief Get maximum # of store operations permitted for llvm.memset 601 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 602 603 /// This function returns the maximum number of store operations permitted 604 /// to replace a call to llvm.memcpy. The value is set by the target at the 605 /// performance threshold for such a replacement. 606 /// @brief Get maximum # of store operations permitted for llvm.memcpy 607 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 608 609 /// This function returns the maximum number of store operations permitted 610 /// to replace a call to llvm.memmove. The value is set by the target at the 611 /// performance threshold for such a replacement. 612 /// @brief Get maximum # of store operations permitted for llvm.memmove 613 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 614 615 /// This function returns true if the target allows unaligned memory accesses. 616 /// This is used, for example, in situations where an array copy/move/set is 617 /// converted to a sequence of store operations. It's use helps to ensure that 618 /// such replacements don't generate code that causes an alignment error 619 /// (trap) on the target machine. 620 /// @brief Determine if the target supports unaligned memory accesses. 621 bool allowsUnalignedMemoryAccesses() const { 622 return allowUnalignedMemoryAccesses; 623 } 624 625 /// This function returns true if the target would benefit from code placement 626 /// optimization. 627 /// @brief Determine if the target should perform code placement optimization. 628 bool shouldOptimizeCodePlacement() const { 629 return benefitFromCodePlacementOpt; 630 } 631 632 /// getOptimalMemOpType - Returns the target specific optimal type for load 633 /// and store operations as a result of memset, memcpy, and memmove lowering. 634 /// It returns MVT::iAny if SelectionDAG should be responsible for 635 /// determining it. 636 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, 637 bool isSrcConst, bool isSrcStr, 638 SelectionDAG &DAG) const { 639 return MVT::iAny; 640 } 641 642 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 643 /// to implement llvm.setjmp. 644 bool usesUnderscoreSetJmp() const { 645 return UseUnderscoreSetJmp; 646 } 647 648 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 649 /// to implement llvm.longjmp. 650 bool usesUnderscoreLongJmp() const { 651 return UseUnderscoreLongJmp; 652 } 653 654 /// getStackPointerRegisterToSaveRestore - If a physical register, this 655 /// specifies the register that llvm.savestack/llvm.restorestack should save 656 /// and restore. 657 unsigned getStackPointerRegisterToSaveRestore() const { 658 return StackPointerRegisterToSaveRestore; 659 } 660 661 /// getExceptionAddressRegister - If a physical register, this returns 662 /// the register that receives the exception address on entry to a landing 663 /// pad. 664 unsigned getExceptionAddressRegister() const { 665 return ExceptionPointerRegister; 666 } 667 668 /// getExceptionSelectorRegister - If a physical register, this returns 669 /// the register that receives the exception typeid on entry to a landing 670 /// pad. 671 unsigned getExceptionSelectorRegister() const { 672 return ExceptionSelectorRegister; 673 } 674 675 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 676 /// set, the default is 200) 677 unsigned getJumpBufSize() const { 678 return JumpBufSize; 679 } 680 681 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 682 /// (if never set, the default is 0) 683 unsigned getJumpBufAlignment() const { 684 return JumpBufAlignment; 685 } 686 687 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 688 /// limit. Any block whose size is greater should not be predicated. 689 unsigned getIfCvtBlockSizeLimit() const { 690 return IfCvtBlockSizeLimit; 691 } 692 693 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 694 /// block to be considered for duplication. Any block whose size is greater 695 /// should not be duplicated to facilitate its predication. 696 unsigned getIfCvtDupBlockSizeLimit() const { 697 return IfCvtDupBlockSizeLimit; 698 } 699 700 /// getPrefLoopAlignment - return the preferred loop alignment. 701 /// 702 unsigned getPrefLoopAlignment() const { 703 return PrefLoopAlignment; 704 } 705 706 /// getPreIndexedAddressParts - returns true by value, base pointer and 707 /// offset pointer and addressing mode by reference if the node's address 708 /// can be legally represented as pre-indexed load / store address. 709 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 710 SDValue &Offset, 711 ISD::MemIndexedMode &AM, 712 SelectionDAG &DAG) const { 713 return false; 714 } 715 716 /// getPostIndexedAddressParts - returns true by value, base pointer and 717 /// offset pointer and addressing mode by reference if this node can be 718 /// combined with a load / store to form a post-indexed load / store. 719 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 720 SDValue &Base, SDValue &Offset, 721 ISD::MemIndexedMode &AM, 722 SelectionDAG &DAG) const { 723 return false; 724 } 725 726 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 727 /// jumptable. 728 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 729 SelectionDAG &DAG) const; 730 731 /// isOffsetFoldingLegal - Return true if folding a constant offset 732 /// with the given GlobalAddress is legal. It is frequently not legal in 733 /// PIC relocation models. 734 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 735 736 //===--------------------------------------------------------------------===// 737 // TargetLowering Optimization Methods 738 // 739 740 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 741 /// SDValues for returning information from TargetLowering to its clients 742 /// that want to combine 743 struct TargetLoweringOpt { 744 SelectionDAG &DAG; 745 SDValue Old; 746 SDValue New; 747 748 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 749 750 bool CombineTo(SDValue O, SDValue N) { 751 Old = O; 752 New = N; 753 return true; 754 } 755 756 /// ShrinkDemandedConstant - Check to see if the specified operand of the 757 /// specified instruction is a constant integer. If so, check to see if 758 /// there are any bits set in the constant that are not demanded. If so, 759 /// shrink the constant and return true. 760 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 761 762 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 763 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 764 /// cast, but it could be generalized for targets with other types of 765 /// implicit widening casts. 766 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 767 DebugLoc dl); 768 }; 769 770 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 771 /// DemandedMask bits of the result of Op are ever used downstream. If we can 772 /// use this information to simplify Op, create a new simplified DAG node and 773 /// return true, returning the original and new nodes in Old and New. 774 /// Otherwise, analyze the expression and return a mask of KnownOne and 775 /// KnownZero bits for the expression (used to simplify the caller). 776 /// The KnownZero/One bits may only be accurate for those bits in the 777 /// DemandedMask. 778 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 779 APInt &KnownZero, APInt &KnownOne, 780 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 781 782 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 783 /// Mask are known to be either zero or one and return them in the 784 /// KnownZero/KnownOne bitsets. 785 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 786 const APInt &Mask, 787 APInt &KnownZero, 788 APInt &KnownOne, 789 const SelectionDAG &DAG, 790 unsigned Depth = 0) const; 791 792 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 793 /// targets that want to expose additional information about sign bits to the 794 /// DAG Combiner. 795 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 796 unsigned Depth = 0) const; 797 798 struct DAGCombinerInfo { 799 void *DC; // The DAG Combiner object. 800 bool BeforeLegalize; 801 bool CalledByLegalizer; 802 public: 803 SelectionDAG &DAG; 804 805 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 806 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 807 808 bool isBeforeLegalize() const { return BeforeLegalize; } 809 bool isCalledByLegalizer() const { return CalledByLegalizer; } 810 811 void AddToWorklist(SDNode *N); 812 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 813 bool AddTo = true); 814 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 815 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 816 817 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 818 }; 819 820 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 821 /// and cc. If it is unable to simplify it, return a null SDValue. 822 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 823 ISD::CondCode Cond, bool foldBooleans, 824 DAGCombinerInfo &DCI, DebugLoc dl) const; 825 826 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 827 /// node is a GlobalAddress + offset. 828 virtual bool 829 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 830 831 /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 832 /// location that is 'Dist' units away from the location that the 'Base' load 833 /// is loading from. 834 bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, 835 int Dist, const MachineFrameInfo *MFI) const; 836 837 /// PerformDAGCombine - This method will be invoked for all target nodes and 838 /// for any target-independent nodes that the target has registered with 839 /// invoke it for. 840 /// 841 /// The semantics are as follows: 842 /// Return Value: 843 /// SDValue.Val == 0 - No change was made 844 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 845 /// otherwise - N should be replaced by the returned Operand. 846 /// 847 /// In addition, methods provided by DAGCombinerInfo may be used to perform 848 /// more complex transformations. 849 /// 850 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 851 852 //===--------------------------------------------------------------------===// 853 // TargetLowering Configuration Methods - These methods should be invoked by 854 // the derived class constructor to configure this object for the target. 855 // 856 857protected: 858 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 859 /// GOT for PC-relative code. 860 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 861 862 /// setShiftAmountType - Describe the type that should be used for shift 863 /// amounts. This type defaults to the pointer type. 864 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 865 866 /// setBooleanContents - Specify how the target extends the result of a 867 /// boolean value from i1 to a wider type. See getBooleanContents. 868 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 869 870 /// setSchedulingPreference - Specify the target scheduling preference. 871 void setSchedulingPreference(SchedPreference Pref) { 872 SchedPreferenceInfo = Pref; 873 } 874 875 /// setShiftAmountFlavor - Describe how the target handles out of range shift 876 /// amounts. 877 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 878 ShiftAmtHandling = OORSA; 879 } 880 881 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 882 /// use _setjmp to implement llvm.setjmp or the non _ version. 883 /// Defaults to false. 884 void setUseUnderscoreSetJmp(bool Val) { 885 UseUnderscoreSetJmp = Val; 886 } 887 888 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 889 /// use _longjmp to implement llvm.longjmp or the non _ version. 890 /// Defaults to false. 891 void setUseUnderscoreLongJmp(bool Val) { 892 UseUnderscoreLongJmp = Val; 893 } 894 895 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 896 /// specifies the register that llvm.savestack/llvm.restorestack should save 897 /// and restore. 898 void setStackPointerRegisterToSaveRestore(unsigned R) { 899 StackPointerRegisterToSaveRestore = R; 900 } 901 902 /// setExceptionPointerRegister - If set to a physical register, this sets 903 /// the register that receives the exception address on entry to a landing 904 /// pad. 905 void setExceptionPointerRegister(unsigned R) { 906 ExceptionPointerRegister = R; 907 } 908 909 /// setExceptionSelectorRegister - If set to a physical register, this sets 910 /// the register that receives the exception typeid on entry to a landing 911 /// pad. 912 void setExceptionSelectorRegister(unsigned R) { 913 ExceptionSelectorRegister = R; 914 } 915 916 /// SelectIsExpensive - Tells the code generator not to expand operations 917 /// into sequences that use the select operations if possible. 918 void setSelectIsExpensive() { SelectIsExpensive = true; } 919 920 /// setIntDivIsCheap - Tells the code generator that integer divide is 921 /// expensive, and if possible, should be replaced by an alternate sequence 922 /// of instructions not containing an integer divide. 923 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 924 925 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 926 /// srl/add/sra for a signed divide by power of two, and let the target handle 927 /// it. 928 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 929 930 /// addRegisterClass - Add the specified register class as an available 931 /// regclass for the specified value type. This indicates the selector can 932 /// handle values of that class natively. 933 void addRegisterClass(MVT VT, TargetRegisterClass *RC) { 934 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); 935 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 936 RegClassForVT[VT.getSimpleVT()] = RC; 937 } 938 939 /// computeRegisterProperties - Once all of the register classes are added, 940 /// this allows us to compute derived properties we expose. 941 void computeRegisterProperties(); 942 943 /// setOperationAction - Indicate that the specified operation does not work 944 /// with the specified type and indicate what to do about it. 945 void setOperationAction(unsigned Op, MVT VT, 946 LegalizeAction Action) { 947 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*8 && 948 Op < array_lengthof(OpActions) && "Table isn't big enough!"); 949 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 950 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2; 951 } 952 953 /// setLoadExtAction - Indicate that the specified load with extension does 954 /// not work with the with specified type and indicate what to do about it. 955 void setLoadExtAction(unsigned ExtType, MVT VT, 956 LegalizeAction Action) { 957 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 && 958 ExtType < array_lengthof(LoadExtActions) && 959 "Table isn't big enough!"); 960 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 961 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2; 962 } 963 964 /// setTruncStoreAction - Indicate that the specified truncating store does 965 /// not work with the with specified type and indicate what to do about it. 966 void setTruncStoreAction(MVT ValVT, MVT MemVT, 967 LegalizeAction Action) { 968 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && 969 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && 970 "Table isn't big enough!"); 971 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) << 972 MemVT.getSimpleVT()*2); 973 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action << 974 MemVT.getSimpleVT()*2; 975 } 976 977 /// setIndexedLoadAction - Indicate that the specified indexed load does or 978 /// does not work with the with specified type and indicate what to do abort 979 /// it. NOTE: All indexed mode loads are initialized to Expand in 980 /// TargetLowering.cpp 981 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 982 LegalizeAction Action) { 983 assert((unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE && 984 IdxMode < array_lengthof(IndexedModeActions[0][0]) && 985 "Table isn't big enough!"); 986 IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode] = (uint8_t)Action; 987 } 988 989 /// setIndexedStoreAction - Indicate that the specified indexed store does or 990 /// does not work with the with specified type and indicate what to do about 991 /// it. NOTE: All indexed mode stores are initialized to Expand in 992 /// TargetLowering.cpp 993 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 994 LegalizeAction Action) { 995 assert((unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE && 996 IdxMode < array_lengthof(IndexedModeActions[0][1] ) && 997 "Table isn't big enough!"); 998 IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode] = (uint8_t)Action; 999 } 1000 1001 /// setConvertAction - Indicate that the specified conversion does or does 1002 /// not work with the with specified type and indicate what to do about it. 1003 void setConvertAction(MVT FromVT, MVT ToVT, 1004 LegalizeAction Action) { 1005 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && 1006 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && 1007 "Table isn't big enough!"); 1008 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) << 1009 ToVT.getSimpleVT()*2); 1010 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action << 1011 ToVT.getSimpleVT()*2; 1012 } 1013 1014 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1015 /// supported on the target and indicate what to do about it. 1016 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) { 1017 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 && 1018 (unsigned)CC < array_lengthof(CondCodeActions) && 1019 "Table isn't big enough!"); 1020 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); 1021 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2; 1022 } 1023 1024 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1025 /// promotion code defaults to trying a larger integer/fp until it can find 1026 /// one that works. If that default is insufficient, this method can be used 1027 /// by the target to override the default. 1028 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1029 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] = 1030 DestVT.getSimpleVT(); 1031 } 1032 1033 /// addLegalFPImmediate - Indicate that this target can instruction select 1034 /// the specified FP immediate natively. 1035 void addLegalFPImmediate(const APFloat& Imm) { 1036 LegalFPImmediates.push_back(Imm); 1037 } 1038 1039 /// setTargetDAGCombine - Targets should invoke this method for each target 1040 /// independent node that they want to provide a custom DAG combiner for by 1041 /// implementing the PerformDAGCombine virtual method. 1042 void setTargetDAGCombine(ISD::NodeType NT) { 1043 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1044 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1045 } 1046 1047 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1048 /// bytes); default is 200 1049 void setJumpBufSize(unsigned Size) { 1050 JumpBufSize = Size; 1051 } 1052 1053 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1054 /// alignment (in bytes); default is 0 1055 void setJumpBufAlignment(unsigned Align) { 1056 JumpBufAlignment = Align; 1057 } 1058 1059 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1060 /// limit (in number of instructions); default is 2. 1061 void setIfCvtBlockSizeLimit(unsigned Limit) { 1062 IfCvtBlockSizeLimit = Limit; 1063 } 1064 1065 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1066 /// of instructions) to be considered for code duplication during 1067 /// if-conversion; default is 2. 1068 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1069 IfCvtDupBlockSizeLimit = Limit; 1070 } 1071 1072 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1073 /// alignment is zero, it means the target does not care about loop alignment. 1074 void setPrefLoopAlignment(unsigned Align) { 1075 PrefLoopAlignment = Align; 1076 } 1077 1078public: 1079 1080 virtual const TargetSubtarget *getSubtarget() { 1081 assert(0 && "Not Implemented"); 1082 return NULL; // this is here to silence compiler errors 1083 } 1084 //===--------------------------------------------------------------------===// 1085 // Lowering methods - These methods must be implemented by targets so that 1086 // the SelectionDAGLowering code knows how to lower these. 1087 // 1088 1089 /// LowerArguments - This hook must be implemented to indicate how we should 1090 /// lower the arguments for the specified function, into the specified DAG. 1091 virtual void 1092 LowerArguments(Function &F, SelectionDAG &DAG, 1093 SmallVectorImpl<SDValue>& ArgValues, DebugLoc dl); 1094 1095 /// LowerCallTo - This hook lowers an abstract call to a function into an 1096 /// actual call. This returns a pair of operands. The first element is the 1097 /// return value for the function (if RetTy is not VoidTy). The second 1098 /// element is the outgoing token chain. 1099 struct ArgListEntry { 1100 SDValue Node; 1101 const Type* Ty; 1102 bool isSExt : 1; 1103 bool isZExt : 1; 1104 bool isInReg : 1; 1105 bool isSRet : 1; 1106 bool isNest : 1; 1107 bool isByVal : 1; 1108 uint16_t Alignment; 1109 1110 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1111 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1112 }; 1113 typedef std::vector<ArgListEntry> ArgListTy; 1114 virtual std::pair<SDValue, SDValue> 1115 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1116 bool isVarArg, bool isInreg, unsigned CallingConv, 1117 bool isTailCall, SDValue Callee, ArgListTy &Args, 1118 SelectionDAG &DAG, DebugLoc dl); 1119 1120 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1121 /// memcpy. This can be used by targets to provide code sequences for cases 1122 /// that don't fit the target's parameters for simple loads/stores and can be 1123 /// more efficient than using a library call. This function can return a null 1124 /// SDValue if the target declines to use custom code and a different 1125 /// lowering strategy should be used. 1126 /// 1127 /// If AlwaysInline is true, the size is constant and the target should not 1128 /// emit any calls and is strongly encouraged to attempt to emit inline code 1129 /// even if it is beyond the usual threshold because this intrinsic is being 1130 /// expanded in a place where calls are not feasible (e.g. within the prologue 1131 /// for another call). If the target chooses to decline an AlwaysInline 1132 /// request here, legalize will resort to using simple loads and stores. 1133 virtual SDValue 1134 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1135 SDValue Chain, 1136 SDValue Op1, SDValue Op2, 1137 SDValue Op3, unsigned Align, 1138 bool AlwaysInline, 1139 const Value *DstSV, uint64_t DstOff, 1140 const Value *SrcSV, uint64_t SrcOff) { 1141 return SDValue(); 1142 } 1143 1144 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1145 /// memmove. This can be used by targets to provide code sequences for cases 1146 /// that don't fit the target's parameters for simple loads/stores and can be 1147 /// more efficient than using a library call. This function can return a null 1148 /// SDValue if the target declines to use custom code and a different 1149 /// lowering strategy should be used. 1150 virtual SDValue 1151 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, 1152 SDValue Chain, 1153 SDValue Op1, SDValue Op2, 1154 SDValue Op3, unsigned Align, 1155 const Value *DstSV, uint64_t DstOff, 1156 const Value *SrcSV, uint64_t SrcOff) { 1157 return SDValue(); 1158 } 1159 1160 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1161 /// memset. This can be used by targets to provide code sequences for cases 1162 /// that don't fit the target's parameters for simple stores and can be more 1163 /// efficient than using a library call. This function can return a null 1164 /// SDValue if the target declines to use custom code and a different 1165 /// lowering strategy should be used. 1166 virtual SDValue 1167 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 1168 SDValue Chain, 1169 SDValue Op1, SDValue Op2, 1170 SDValue Op3, unsigned Align, 1171 const Value *DstSV, uint64_t DstOff) { 1172 return SDValue(); 1173 } 1174 1175 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1176 /// to legalize nodes with an illegal operand type but legal result types. 1177 /// It replaces the LowerOperation callback in the type Legalizer. 1178 /// The reason we can not do away with LowerOperation entirely is that 1179 /// LegalizeDAG isn't yet ready to use this callback. 1180 /// TODO: Consider merging with ReplaceNodeResults. 1181 1182 /// The target places new result values for the node in Results (their number 1183 /// and types must exactly match those of the original return values of 1184 /// the node), or leaves Results empty, which indicates that the node is not 1185 /// to be custom lowered after all. 1186 /// The default implementation calls LowerOperation. 1187 virtual void LowerOperationWrapper(SDNode *N, 1188 SmallVectorImpl<SDValue> &Results, 1189 SelectionDAG &DAG); 1190 1191 /// LowerOperation - This callback is invoked for operations that are 1192 /// unsupported by the target, which are registered to use 'custom' lowering, 1193 /// and whose defined values are all legal. 1194 /// If the target has no operations that require custom lowering, it need not 1195 /// implement this. The default implementation of this aborts. 1196 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1197 1198 /// ReplaceNodeResults - This callback is invoked when a node result type is 1199 /// illegal for the target, and the operation was registered to use 'custom' 1200 /// lowering for that result type. The target places new result values for 1201 /// the node in Results (their number and types must exactly match those of 1202 /// the original return values of the node), or leaves Results empty, which 1203 /// indicates that the node is not to be custom lowered after all. 1204 /// 1205 /// If the target has no operations that require custom lowering, it need not 1206 /// implement this. The default implementation aborts. 1207 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1208 SelectionDAG &DAG) { 1209 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1210 } 1211 1212 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for 1213 /// tail call optimization. Targets which want to do tail call optimization 1214 /// should override this function. 1215 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call, 1216 SDValue Ret, 1217 SelectionDAG &DAG) const { 1218 return false; 1219 } 1220 1221 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly 1222 /// preceeds the RET node and whether the return uses the result of the node 1223 /// or is a void return. This function can be used by the target to determine 1224 /// eligiblity of tail call optimization. 1225 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret); 1226 1227 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if 1228 /// it exists. Skip a possible ISD::TokenFactor. 1229 static SDValue GetPossiblePreceedingTailCall(SDValue Chain, 1230 unsigned TailCallNodeOpCode) { 1231 if (Chain.getOpcode() == TailCallNodeOpCode) { 1232 return Chain; 1233 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1234 if (Chain.getNumOperands() && 1235 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode) 1236 return Chain.getOperand(0); 1237 } 1238 return Chain; 1239 } 1240 1241 /// getTargetNodeName() - This method returns the name of a target specific 1242 /// DAG node. 1243 virtual const char *getTargetNodeName(unsigned Opcode) const; 1244 1245 /// createFastISel - This method returns a target specific FastISel object, 1246 /// or null if the target does not support "fast" ISel. 1247 virtual FastISel * 1248 createFastISel(MachineFunction &, 1249 MachineModuleInfo *, DwarfWriter *, 1250 DenseMap<const Value *, unsigned> &, 1251 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1252 DenseMap<const AllocaInst *, int> & 1253#ifndef NDEBUG 1254 , SmallSet<Instruction*, 8> &CatchInfoLost 1255#endif 1256 ) { 1257 return 0; 1258 } 1259 1260 //===--------------------------------------------------------------------===// 1261 // Inline Asm Support hooks 1262 // 1263 1264 enum ConstraintType { 1265 C_Register, // Constraint represents specific register(s). 1266 C_RegisterClass, // Constraint represents any of register(s) in class. 1267 C_Memory, // Memory constraint. 1268 C_Other, // Something else. 1269 C_Unknown // Unsupported constraint. 1270 }; 1271 1272 /// AsmOperandInfo - This contains information for each constraint that we are 1273 /// lowering. 1274 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1275 /// ConstraintCode - This contains the actual string for the code, like "m". 1276 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1277 /// most closely matches the operand. 1278 std::string ConstraintCode; 1279 1280 /// ConstraintType - Information about the constraint code, e.g. Register, 1281 /// RegisterClass, Memory, Other, Unknown. 1282 TargetLowering::ConstraintType ConstraintType; 1283 1284 /// CallOperandval - If this is the result output operand or a 1285 /// clobber, this is null, otherwise it is the incoming operand to the 1286 /// CallInst. This gets modified as the asm is processed. 1287 Value *CallOperandVal; 1288 1289 /// ConstraintVT - The ValueType for the operand value. 1290 MVT ConstraintVT; 1291 1292 /// isMatchingInputConstraint - Return true of this is an input operand that 1293 /// is a matching constraint like "4". 1294 bool isMatchingInputConstraint() const; 1295 1296 /// getMatchedOperand - If this is an input matching constraint, this method 1297 /// returns the output operand it matches. 1298 unsigned getMatchedOperand() const; 1299 1300 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1301 : InlineAsm::ConstraintInfo(info), 1302 ConstraintType(TargetLowering::C_Unknown), 1303 CallOperandVal(0), ConstraintVT(MVT::Other) { 1304 } 1305 }; 1306 1307 /// ComputeConstraintToUse - Determines the constraint code and constraint 1308 /// type to use for the specific AsmOperandInfo, setting 1309 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1310 /// being passed in is available, it can be passed in as Op, otherwise an 1311 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1312 /// constraint of the inline asm instruction being processed is 'm'. 1313 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1314 SDValue Op, 1315 bool hasMemory, 1316 SelectionDAG *DAG = 0) const; 1317 1318 /// getConstraintType - Given a constraint, return the type of constraint it 1319 /// is for this target. 1320 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1321 1322 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1323 /// return a list of registers that can be used to satisfy the constraint. 1324 /// This should only be used for C_RegisterClass constraints. 1325 virtual std::vector<unsigned> 1326 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1327 MVT VT) const; 1328 1329 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1330 /// {edx}), return the register number and the register class for the 1331 /// register. 1332 /// 1333 /// Given a register class constraint, like 'r', if this corresponds directly 1334 /// to an LLVM register class, return a register of 0 and the register class 1335 /// pointer. 1336 /// 1337 /// This should only be used for C_Register constraints. On error, 1338 /// this returns a register number of 0 and a null register class pointer.. 1339 virtual std::pair<unsigned, const TargetRegisterClass*> 1340 getRegForInlineAsmConstraint(const std::string &Constraint, 1341 MVT VT) const; 1342 1343 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1344 /// with another that has more specific requirements based on the type of the 1345 /// corresponding operand. This returns null if there is no replacement to 1346 /// make. 1347 virtual const char *LowerXConstraint(MVT ConstraintVT) const; 1348 1349 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1350 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1351 /// it means one of the asm constraint of the inline asm instruction being 1352 /// processed is 'm'. 1353 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1354 bool hasMemory, 1355 std::vector<SDValue> &Ops, 1356 SelectionDAG &DAG) const; 1357 1358 //===--------------------------------------------------------------------===// 1359 // Scheduler hooks 1360 // 1361 1362 // EmitInstrWithCustomInserter - This method should be implemented by targets 1363 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These 1364 // instructions are special in various ways, which require special support to 1365 // insert. The specified MachineInstr is created but not inserted into any 1366 // basic blocks, and the scheduler passes ownership of it to this method. 1367 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1368 MachineBasicBlock *MBB) const; 1369 1370 //===--------------------------------------------------------------------===// 1371 // Addressing mode description hooks (used by LSR etc). 1372 // 1373 1374 /// AddrMode - This represents an addressing mode of: 1375 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1376 /// If BaseGV is null, there is no BaseGV. 1377 /// If BaseOffs is zero, there is no base offset. 1378 /// If HasBaseReg is false, there is no base register. 1379 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1380 /// no scale. 1381 /// 1382 struct AddrMode { 1383 GlobalValue *BaseGV; 1384 int64_t BaseOffs; 1385 bool HasBaseReg; 1386 int64_t Scale; 1387 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1388 }; 1389 1390 /// isLegalAddressingMode - Return true if the addressing mode represented by 1391 /// AM is legal for this target, for a load/store of the specified type. 1392 /// The type may be VoidTy, in which case only return true if the addressing 1393 /// mode is legal for a load/store of any legal type. 1394 /// TODO: Handle pre/postinc as well. 1395 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1396 1397 /// isTruncateFree - Return true if it's free to truncate a value of 1398 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1399 /// register EAX to i16 by referencing its sub-register AX. 1400 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1401 return false; 1402 } 1403 1404 virtual bool isTruncateFree(MVT VT1, MVT VT2) const { 1405 return false; 1406 } 1407 1408 /// isZExtFree - Return true if any actual instruction that defines a 1409 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 1410 /// register. This does not necessarily include registers defined in 1411 /// unknown ways, such as incoming arguments, or copies from unknown 1412 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1413 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1414 /// all instructions that define 32-bit values implicit zero-extend the 1415 /// result out to 64 bits. 1416 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1417 return false; 1418 } 1419 1420 virtual bool isZExtFree(MVT VT1, MVT VT2) const { 1421 return false; 1422 } 1423 1424 /// isNarrowingProfitable - Return true if it's profitable to narrow 1425 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1426 /// from i32 to i8 but not from i32 to i16. 1427 virtual bool isNarrowingProfitable(MVT VT1, MVT VT2) const { 1428 return false; 1429 } 1430 1431 //===--------------------------------------------------------------------===// 1432 // Div utility functions 1433 // 1434 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1435 std::vector<SDNode*>* Created) const; 1436 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1437 std::vector<SDNode*>* Created) const; 1438 1439 1440 //===--------------------------------------------------------------------===// 1441 // Runtime Library hooks 1442 // 1443 1444 /// setLibcallName - Rename the default libcall routine name for the specified 1445 /// libcall. 1446 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1447 LibcallRoutineNames[Call] = Name; 1448 } 1449 1450 /// getLibcallName - Get the libcall routine name for the specified libcall. 1451 /// 1452 const char *getLibcallName(RTLIB::Libcall Call) const { 1453 return LibcallRoutineNames[Call]; 1454 } 1455 1456 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1457 /// result of the comparison libcall against zero. 1458 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1459 CmpLibcallCCs[Call] = CC; 1460 } 1461 1462 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1463 /// the comparison libcall against zero. 1464 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1465 return CmpLibcallCCs[Call]; 1466 } 1467 1468private: 1469 TargetMachine &TM; 1470 const TargetData *TD; 1471 1472 /// PointerTy - The type to use for pointers, usually i32 or i64. 1473 /// 1474 MVT PointerTy; 1475 1476 /// IsLittleEndian - True if this is a little endian target. 1477 /// 1478 bool IsLittleEndian; 1479 1480 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 1481 /// 1482 bool UsesGlobalOffsetTable; 1483 1484 /// SelectIsExpensive - Tells the code generator not to expand operations 1485 /// into sequences that use the select operations if possible. 1486 bool SelectIsExpensive; 1487 1488 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1489 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1490 /// a real cost model is in place. If we ever optimize for size, this will be 1491 /// set to true unconditionally. 1492 bool IntDivIsCheap; 1493 1494 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1495 /// srl/add/sra for a signed divide by power of two, and let the target handle 1496 /// it. 1497 bool Pow2DivIsCheap; 1498 1499 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1500 /// llvm.setjmp. Defaults to false. 1501 bool UseUnderscoreSetJmp; 1502 1503 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1504 /// llvm.longjmp. Defaults to false. 1505 bool UseUnderscoreLongJmp; 1506 1507 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1508 /// PointerTy is. 1509 MVT ShiftAmountTy; 1510 1511 OutOfRangeShiftAmount ShiftAmtHandling; 1512 1513 /// BooleanContents - Information about the contents of the high-bits in 1514 /// boolean values held in a type wider than i1. See getBooleanContents. 1515 BooleanContent BooleanContents; 1516 1517 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1518 /// total cycles or lowest register usage. 1519 SchedPreference SchedPreferenceInfo; 1520 1521 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1522 unsigned JumpBufSize; 1523 1524 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1525 /// buffers 1526 unsigned JumpBufAlignment; 1527 1528 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1529 /// if-converted. 1530 unsigned IfCvtBlockSizeLimit; 1531 1532 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1533 /// duplicated during if-conversion. 1534 unsigned IfCvtDupBlockSizeLimit; 1535 1536 /// PrefLoopAlignment - The perferred loop alignment. 1537 /// 1538 unsigned PrefLoopAlignment; 1539 1540 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1541 /// specifies the register that llvm.savestack/llvm.restorestack should save 1542 /// and restore. 1543 unsigned StackPointerRegisterToSaveRestore; 1544 1545 /// ExceptionPointerRegister - If set to a physical register, this specifies 1546 /// the register that receives the exception address on entry to a landing 1547 /// pad. 1548 unsigned ExceptionPointerRegister; 1549 1550 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1551 /// the register that receives the exception typeid on entry to a landing 1552 /// pad. 1553 unsigned ExceptionSelectorRegister; 1554 1555 /// RegClassForVT - This indicates the default register class to use for 1556 /// each ValueType the target supports natively. 1557 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1558 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1559 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1560 1561 /// TransformToType - For any value types we are promoting or expanding, this 1562 /// contains the value type that we are changing to. For Expanded types, this 1563 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1564 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1565 /// by the system, this holds the same type (e.g. i32 -> i32). 1566 MVT TransformToType[MVT::LAST_VALUETYPE]; 1567 1568 /// OpActions - For each operation and each value type, keep a LegalizeAction 1569 /// that indicates how instruction selection should deal with the operation. 1570 /// Most operations are Legal (aka, supported natively by the target), but 1571 /// operations that are not should be described. Note that operations on 1572 /// non-legal value types are not described here. 1573 uint64_t OpActions[ISD::BUILTIN_OP_END]; 1574 1575 /// LoadExtActions - For each load of load extension type and each value type, 1576 /// keep a LegalizeAction that indicates how instruction selection should deal 1577 /// with the load. 1578 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1579 1580 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1581 /// indicates how instruction selection should deal with the store. 1582 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1583 1584 /// IndexedModeActions - For each indexed mode and each value type, 1585 /// keep a pair of LegalizeAction that indicates how instruction 1586 /// selection should deal with the load / store. The first 1587 /// dimension is now the value_type for the reference. The second 1588 /// dimension is the load [0] vs. store[1]. The third dimension 1589 /// represents the various modes for load store. 1590 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE]; 1591 1592 /// ConvertActions - For each conversion from source type to destination type, 1593 /// keep a LegalizeAction that indicates how instruction selection should 1594 /// deal with the conversion. 1595 /// Currently, this is used only for floating->floating conversions 1596 /// (FP_EXTEND and FP_ROUND). 1597 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1598 1599 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1600 /// LegalizeAction that indicates how instruction selection should 1601 /// deal with the condition code. 1602 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1603 1604 ValueTypeActionImpl ValueTypeActions; 1605 1606 std::vector<APFloat> LegalFPImmediates; 1607 1608 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses; 1609 1610 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1611 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1612 /// which sets a bit in this array. 1613 unsigned char 1614 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1615 1616 /// PromoteToType - For operations that must be promoted to a specific type, 1617 /// this holds the destination type. This map should be sparse, so don't hold 1618 /// it as an array. 1619 /// 1620 /// Targets add entries to this map with AddPromotedToType(..), clients access 1621 /// this with getTypeToPromoteTo(..). 1622 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1623 PromoteToType; 1624 1625 /// LibcallRoutineNames - Stores the name each libcall. 1626 /// 1627 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1628 1629 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1630 /// of each of the comparison libcall against zero. 1631 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1632 1633protected: 1634 /// When lowering \@llvm.memset this field specifies the maximum number of 1635 /// store operations that may be substituted for the call to memset. Targets 1636 /// must set this value based on the cost threshold for that target. Targets 1637 /// should assume that the memset will be done using as many of the largest 1638 /// store operations first, followed by smaller ones, if necessary, per 1639 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1640 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1641 /// store. This only applies to setting a constant array of a constant size. 1642 /// @brief Specify maximum number of store instructions per memset call. 1643 unsigned maxStoresPerMemset; 1644 1645 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1646 /// store operations that may be substituted for a call to memcpy. Targets 1647 /// must set this value based on the cost threshold for that target. Targets 1648 /// should assume that the memcpy will be done using as many of the largest 1649 /// store operations first, followed by smaller ones, if necessary, per 1650 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1651 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1652 /// and one 1-byte store. This only applies to copying a constant array of 1653 /// constant size. 1654 /// @brief Specify maximum bytes of store instructions per memcpy call. 1655 unsigned maxStoresPerMemcpy; 1656 1657 /// When lowering \@llvm.memmove this field specifies the maximum number of 1658 /// store instructions that may be substituted for a call to memmove. Targets 1659 /// must set this value based on the cost threshold for that target. Targets 1660 /// should assume that the memmove will be done using as many of the largest 1661 /// store operations first, followed by smaller ones, if necessary, per 1662 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1663 /// with 8-bit alignment would result in nine 1-byte stores. This only 1664 /// applies to copying a constant array of constant size. 1665 /// @brief Specify maximum bytes of store instructions per memmove call. 1666 unsigned maxStoresPerMemmove; 1667 1668 /// This field specifies whether the target machine permits unaligned memory 1669 /// accesses. This is used, for example, to determine the size of store 1670 /// operations when copying small arrays and other similar tasks. 1671 /// @brief Indicate whether the target permits unaligned memory accesses. 1672 bool allowUnalignedMemoryAccesses; 1673 1674 /// This field specifies whether the target can benefit from code placement 1675 /// optimization. 1676 bool benefitFromCodePlacementOpt; 1677}; 1678} // end llvm namespace 1679 1680#endif 1681