TargetLowering.h revision f48ae4630bdf5c58dfca8f4d82a1ee1a88c3a767
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CodeGen/SelectionDAGNodes.h" 26#include "llvm/CodeGen/RuntimeLibcalls.h" 27#include <map> 28#include <vector> 29 30namespace llvm { 31 class Value; 32 class Function; 33 class TargetMachine; 34 class TargetData; 35 class TargetRegisterClass; 36 class SDNode; 37 class SDOperand; 38 class SelectionDAG; 39 class MachineBasicBlock; 40 class MachineInstr; 41 class VectorType; 42 43//===----------------------------------------------------------------------===// 44/// TargetLowering - This class defines information used to lower LLVM code to 45/// legal SelectionDAG operators that the target instruction selector can accept 46/// natively. 47/// 48/// This class also defines callbacks that targets must implement to lower 49/// target-specific constructs to SelectionDAG operators. 50/// 51class TargetLowering { 52public: 53 /// LegalizeAction - This enum indicates whether operations are valid for a 54 /// target, and if not, what action should be used to make them valid. 55 enum LegalizeAction { 56 Legal, // The target natively supports this operation. 57 Promote, // This operation should be executed in a larger type. 58 Expand, // Try to expand this to other ops, otherwise use a libcall. 59 Custom // Use the LowerOperation hook to implement custom lowering. 60 }; 61 62 enum OutOfRangeShiftAmount { 63 Undefined, // Oversized shift amounts are undefined (default). 64 Mask, // Shift amounts are auto masked (anded) to value size. 65 Extend // Oversized shift pulls in zeros or sign bits. 66 }; 67 68 enum SetCCResultValue { 69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend. 70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result. 71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result. 72 }; 73 74 enum SchedPreference { 75 SchedulingForLatency, // Scheduling for shortest total latency. 76 SchedulingForRegPressure // Scheduling for lowest register pressure. 77 }; 78 79 TargetLowering(TargetMachine &TM); 80 virtual ~TargetLowering(); 81 82 TargetMachine &getTargetMachine() const { return TM; } 83 const TargetData *getTargetData() const { return TD; } 84 85 bool isLittleEndian() const { return IsLittleEndian; } 86 MVT::ValueType getPointerTy() const { return PointerTy; } 87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } 88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } 89 90 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC 91 /// codegen. 92 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; } 93 94 /// isSelectExpensive - Return true if the select operation is expensive for 95 /// this target. 96 bool isSelectExpensive() const { return SelectIsExpensive; } 97 98 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 99 /// a sequence of several shifts, adds, and multiplies for this target. 100 bool isIntDivCheap() const { return IntDivIsCheap; } 101 102 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 103 /// srl/add/sra. 104 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 105 106 /// getSetCCResultTy - Return the ValueType of the result of setcc operations. 107 /// 108 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; } 109 110 /// getSetCCResultContents - For targets without boolean registers, this flag 111 /// returns information about the contents of the high-bits in the setcc 112 /// result register. 113 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;} 114 115 /// getSchedulingPreference - Return target scheduling preference. 116 SchedPreference getSchedulingPreference() const { 117 return SchedPreferenceInfo; 118 } 119 120 /// getRegClassFor - Return the register class that should be used for the 121 /// specified value type. This may only be called on legal types. 122 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { 123 TargetRegisterClass *RC = RegClassForVT[VT]; 124 assert(RC && "This value type is not natively supported!"); 125 return RC; 126 } 127 128 /// isTypeLegal - Return true if the target has native support for the 129 /// specified value type. This means that it has a register that directly 130 /// holds it without promotions or expansions. 131 bool isTypeLegal(MVT::ValueType VT) const { 132 return RegClassForVT[VT] != 0; 133 } 134 135 class ValueTypeActionImpl { 136 /// ValueTypeActions - This is a bitvector that contains two bits for each 137 /// value type, where the two bits correspond to the LegalizeAction enum. 138 /// This can be queried with "getTypeAction(VT)". 139 uint32_t ValueTypeActions[2]; 140 public: 141 ValueTypeActionImpl() { 142 ValueTypeActions[0] = ValueTypeActions[1] = 0; 143 } 144 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 145 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 146 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 147 } 148 149 LegalizeAction getTypeAction(MVT::ValueType VT) const { 150 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); 151 } 152 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { 153 assert(unsigned(VT >> 4) < 154 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0])); 155 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); 156 } 157 }; 158 159 const ValueTypeActionImpl &getValueTypeActions() const { 160 return ValueTypeActions; 161 } 162 163 /// getTypeAction - Return how we should legalize values of this type, either 164 /// it is already legal (return 'Legal') or we need to promote it to a larger 165 /// type (return 'Promote'), or we need to expand it into multiple registers 166 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 167 LegalizeAction getTypeAction(MVT::ValueType VT) const { 168 return ValueTypeActions.getTypeAction(VT); 169 } 170 171 /// getTypeToTransformTo - For types supported by the target, this is an 172 /// identity function. For types that must be promoted to larger types, this 173 /// returns the larger type to promote to. For integer types that are larger 174 /// than the largest integer register, this contains one step in the expansion 175 /// to get to the smaller register. For illegal floating point types, this 176 /// returns the integer type to transform to. 177 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { 178 return TransformToType[VT]; 179 } 180 181 /// getTypeToExpandTo - For types supported by the target, this is an 182 /// identity function. For types that must be expanded (i.e. integer types 183 /// that are larger than the largest integer register or illegal floating 184 /// point types), this returns the largest legal type it will be expanded to. 185 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { 186 while (true) { 187 switch (getTypeAction(VT)) { 188 case Legal: 189 return VT; 190 case Expand: 191 VT = TransformToType[VT]; 192 break; 193 default: 194 assert(false && "Type is not legal nor is it to be expanded!"); 195 return VT; 196 } 197 } 198 return VT; 199 } 200 201 /// getVectorTypeBreakdown - Vector types are broken down into some number of 202 /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32 203 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 204 /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86. 205 /// 206 /// This method returns the number of registers needed, and the VT for each 207 /// register. It also returns the VT of the VectorType elements before they 208 /// are promoted/expanded. 209 /// 210 unsigned getVectorTypeBreakdown(const VectorType *PTy, 211 MVT::ValueType &PTyElementVT, 212 MVT::ValueType &PTyLegalElementVT) const; 213 214 typedef std::vector<double>::const_iterator legal_fpimm_iterator; 215 legal_fpimm_iterator legal_fpimm_begin() const { 216 return LegalFPImmediates.begin(); 217 } 218 legal_fpimm_iterator legal_fpimm_end() const { 219 return LegalFPImmediates.end(); 220 } 221 222 /// isShuffleMaskLegal - Targets can use this to indicate that they only 223 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 224 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 225 /// are assumed to be legal. 226 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 227 return true; 228 } 229 230 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 231 /// used by Targets can use this to indicate if there is a suitable 232 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 233 /// pool entry. 234 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 235 MVT::ValueType EVT, 236 SelectionDAG &DAG) const { 237 return false; 238 } 239 240 /// getOperationAction - Return how this operation should be treated: either 241 /// it is legal, needs to be promoted to a larger size, needs to be 242 /// expanded to some other code sequence, or the target has a custom expander 243 /// for it. 244 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { 245 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); 246 } 247 248 /// isOperationLegal - Return true if the specified operation is legal on this 249 /// target. 250 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { 251 return getOperationAction(Op, VT) == Legal || 252 getOperationAction(Op, VT) == Custom; 253 } 254 255 /// getLoadXAction - Return how this load with extension should be treated: 256 /// either it is legal, needs to be promoted to a larger size, needs to be 257 /// expanded to some other code sequence, or the target has a custom expander 258 /// for it. 259 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { 260 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3); 261 } 262 263 /// isLoadXLegal - Return true if the specified load with extension is legal 264 /// on this target. 265 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { 266 return getLoadXAction(LType, VT) == Legal || 267 getLoadXAction(LType, VT) == Custom; 268 } 269 270 /// getStoreXAction - Return how this store with truncation should be treated: 271 /// either it is legal, needs to be promoted to a larger size, needs to be 272 /// expanded to some other code sequence, or the target has a custom expander 273 /// for it. 274 LegalizeAction getStoreXAction(MVT::ValueType VT) const { 275 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3); 276 } 277 278 /// isStoreXLegal - Return true if the specified store with truncation is 279 /// legal on this target. 280 bool isStoreXLegal(MVT::ValueType VT) const { 281 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom; 282 } 283 284 /// getIndexedLoadAction - Return how the indexed load should be treated: 285 /// either it is legal, needs to be promoted to a larger size, needs to be 286 /// expanded to some other code sequence, or the target has a custom expander 287 /// for it. 288 LegalizeAction 289 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { 290 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3); 291 } 292 293 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 294 /// on this target. 295 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { 296 return getIndexedLoadAction(IdxMode, VT) == Legal || 297 getIndexedLoadAction(IdxMode, VT) == Custom; 298 } 299 300 /// getIndexedStoreAction - Return how the indexed store should be treated: 301 /// either it is legal, needs to be promoted to a larger size, needs to be 302 /// expanded to some other code sequence, or the target has a custom expander 303 /// for it. 304 LegalizeAction 305 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { 306 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3); 307 } 308 309 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 310 /// on this target. 311 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { 312 return getIndexedStoreAction(IdxMode, VT) == Legal || 313 getIndexedStoreAction(IdxMode, VT) == Custom; 314 } 315 316 /// getTypeToPromoteTo - If the action for this operation is to promote, this 317 /// method returns the ValueType to promote to. 318 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { 319 assert(getOperationAction(Op, VT) == Promote && 320 "This operation isn't promoted!"); 321 322 // See if this has an explicit type specified. 323 std::map<std::pair<unsigned, MVT::ValueType>, 324 MVT::ValueType>::const_iterator PTTI = 325 PromoteToType.find(std::make_pair(Op, VT)); 326 if (PTTI != PromoteToType.end()) return PTTI->second; 327 328 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && 329 "Cannot autopromote this type, add it with AddPromotedToType."); 330 331 MVT::ValueType NVT = VT; 332 do { 333 NVT = (MVT::ValueType)(NVT+1); 334 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && 335 "Didn't find type to promote to!"); 336 } while (!isTypeLegal(NVT) || 337 getOperationAction(Op, NVT) == Promote); 338 return NVT; 339 } 340 341 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. 342 /// This is fixed by the LLVM operations except for the pointer size. If 343 /// AllowUnknown is true, this will return MVT::Other for types with no MVT 344 /// counterpart (e.g. structs), otherwise it will assert. 345 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const { 346 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown); 347 return VT == MVT::iPTR ? PointerTy : VT; 348 } 349 350 /// getNumElements - Return the number of registers that this ValueType will 351 /// eventually require. This is one for any types promoted to live in larger 352 /// registers, but may be more than one for types (like i64) that are split 353 /// into pieces. 354 unsigned getNumElements(MVT::ValueType VT) const { 355 return NumElementsForVT[VT]; 356 } 357 358 /// hasTargetDAGCombine - If true, the target has custom DAG combine 359 /// transformations that it can perform for the specified node. 360 bool hasTargetDAGCombine(ISD::NodeType NT) const { 361 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 362 } 363 364 /// This function returns the maximum number of store operations permitted 365 /// to replace a call to llvm.memset. The value is set by the target at the 366 /// performance threshold for such a replacement. 367 /// @brief Get maximum # of store operations permitted for llvm.memset 368 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 369 370 /// This function returns the maximum number of store operations permitted 371 /// to replace a call to llvm.memcpy. The value is set by the target at the 372 /// performance threshold for such a replacement. 373 /// @brief Get maximum # of store operations permitted for llvm.memcpy 374 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 375 376 /// This function returns the maximum number of store operations permitted 377 /// to replace a call to llvm.memmove. The value is set by the target at the 378 /// performance threshold for such a replacement. 379 /// @brief Get maximum # of store operations permitted for llvm.memmove 380 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 381 382 /// This function returns true if the target allows unaligned memory accesses. 383 /// This is used, for example, in situations where an array copy/move/set is 384 /// converted to a sequence of store operations. It's use helps to ensure that 385 /// such replacements don't generate code that causes an alignment error 386 /// (trap) on the target machine. 387 /// @brief Determine if the target supports unaligned memory accesses. 388 bool allowsUnalignedMemoryAccesses() const { 389 return allowUnalignedMemoryAccesses; 390 } 391 392 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 393 /// to implement llvm.setjmp. 394 bool usesUnderscoreSetJmp() const { 395 return UseUnderscoreSetJmp; 396 } 397 398 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 399 /// to implement llvm.longjmp. 400 bool usesUnderscoreLongJmp() const { 401 return UseUnderscoreLongJmp; 402 } 403 404 /// getStackPointerRegisterToSaveRestore - If a physical register, this 405 /// specifies the register that llvm.savestack/llvm.restorestack should save 406 /// and restore. 407 unsigned getStackPointerRegisterToSaveRestore() const { 408 return StackPointerRegisterToSaveRestore; 409 } 410 411 /// getExceptionAddressRegister - If a physical register, this returns 412 /// the register that receives the exception address on entry to a landing 413 /// pad. 414 unsigned getExceptionAddressRegister() const { 415 return ExceptionPointerRegister; 416 } 417 418 /// getExceptionSelectorRegister - If a physical register, this returns 419 /// the register that receives the exception typeid on entry to a landing 420 /// pad. 421 unsigned getExceptionSelectorRegister() const { 422 return ExceptionSelectorRegister; 423 } 424 425 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 426 /// set, the default is 200) 427 unsigned getJumpBufSize() const { 428 return JumpBufSize; 429 } 430 431 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 432 /// (if never set, the default is 0) 433 unsigned getJumpBufAlignment() const { 434 return JumpBufAlignment; 435 } 436 437 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 438 /// limit. Any block whose size is greater should not be predicated. 439 virtual unsigned getIfCvtBlockSizeLimit() const { 440 return IfCvtBlockSizeLimit; 441 } 442 443 /// getPreIndexedAddressParts - returns true by value, base pointer and 444 /// offset pointer and addressing mode by reference if the node's address 445 /// can be legally represented as pre-indexed load / store address. 446 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 447 SDOperand &Offset, 448 ISD::MemIndexedMode &AM, 449 SelectionDAG &DAG) { 450 return false; 451 } 452 453 /// getPostIndexedAddressParts - returns true by value, base pointer and 454 /// offset pointer and addressing mode by reference if this node can be 455 /// combined with a load / store to form a post-indexed load / store. 456 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 457 SDOperand &Base, SDOperand &Offset, 458 ISD::MemIndexedMode &AM, 459 SelectionDAG &DAG) { 460 return false; 461 } 462 463 //===--------------------------------------------------------------------===// 464 // TargetLowering Optimization Methods 465 // 466 467 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 468 /// SDOperands for returning information from TargetLowering to its clients 469 /// that want to combine 470 struct TargetLoweringOpt { 471 SelectionDAG &DAG; 472 SDOperand Old; 473 SDOperand New; 474 475 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} 476 477 bool CombineTo(SDOperand O, SDOperand N) { 478 Old = O; 479 New = N; 480 return true; 481 } 482 483 /// ShrinkDemandedConstant - Check to see if the specified operand of the 484 /// specified instruction is a constant integer. If so, check to see if there 485 /// are any bits set in the constant that are not demanded. If so, shrink the 486 /// constant and return true. 487 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); 488 }; 489 490 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We 491 /// use this predicate to simplify operations downstream. Op and Mask are 492 /// known to be the same type. 493 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0) 494 const; 495 496 /// ComputeMaskedBits - Determine which of the bits specified in Mask are 497 /// known to be either zero or one and return them in the KnownZero/KnownOne 498 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit 499 /// processing. Targets can implement the computeMaskedBitsForTargetNode 500 /// method, to allow target nodes to be understood. 501 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, 502 uint64_t &KnownOne, unsigned Depth = 0) const; 503 504 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 505 /// DemandedMask bits of the result of Op are ever used downstream. If we can 506 /// use this information to simplify Op, create a new simplified DAG node and 507 /// return true, returning the original and new nodes in Old and New. 508 /// Otherwise, analyze the expression and return a mask of KnownOne and 509 /// KnownZero bits for the expression (used to simplify the caller). 510 /// The KnownZero/One bits may only be accurate for those bits in the 511 /// DemandedMask. 512 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 513 uint64_t &KnownZero, uint64_t &KnownOne, 514 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 515 516 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 517 /// Mask are known to be either zero or one and return them in the 518 /// KnownZero/KnownOne bitsets. 519 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 520 uint64_t Mask, 521 uint64_t &KnownZero, 522 uint64_t &KnownOne, 523 unsigned Depth = 0) const; 524 525 /// ComputeNumSignBits - Return the number of times the sign bit of the 526 /// register is replicated into the other bits. We know that at least 1 bit 527 /// is always equal to the sign bit (itself), but other cases can give us 528 /// information. For example, immediately after an "SRA X, 2", we know that 529 /// the top 3 bits are all equal to each other, so we return 3. 530 unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const; 531 532 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 533 /// targets that want to expose additional information about sign bits to the 534 /// DAG Combiner. 535 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, 536 unsigned Depth = 0) const; 537 538 struct DAGCombinerInfo { 539 void *DC; // The DAG Combiner object. 540 bool BeforeLegalize; 541 bool CalledByLegalizer; 542 public: 543 SelectionDAG &DAG; 544 545 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc) 546 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {} 547 548 bool isBeforeLegalize() const { return BeforeLegalize; } 549 bool isCalledByLegalizer() const { return CalledByLegalizer; } 550 551 void AddToWorklist(SDNode *N); 552 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To); 553 SDOperand CombineTo(SDNode *N, SDOperand Res); 554 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1); 555 }; 556 557 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 558 /// and cc. If it is unable to simplify it, return a null SDOperand. 559 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 560 ISD::CondCode Cond, bool foldBooleans, 561 DAGCombinerInfo &DCI) const; 562 563 /// PerformDAGCombine - This method will be invoked for all target nodes and 564 /// for any target-independent nodes that the target has registered with 565 /// invoke it for. 566 /// 567 /// The semantics are as follows: 568 /// Return Value: 569 /// SDOperand.Val == 0 - No change was made 570 /// SDOperand.Val == N - N was replaced, is dead, and is already handled. 571 /// otherwise - N should be replaced by the returned Operand. 572 /// 573 /// In addition, methods provided by DAGCombinerInfo may be used to perform 574 /// more complex transformations. 575 /// 576 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 577 578 //===--------------------------------------------------------------------===// 579 // TargetLowering Configuration Methods - These methods should be invoked by 580 // the derived class constructor to configure this object for the target. 581 // 582 583protected: 584 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a 585 /// GOT for PC-relative code. 586 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; } 587 588 /// setShiftAmountType - Describe the type that should be used for shift 589 /// amounts. This type defaults to the pointer type. 590 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } 591 592 /// setSetCCResultType - Describe the type that shoudl be used as the result 593 /// of a setcc operation. This defaults to the pointer type. 594 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; } 595 596 /// setSetCCResultContents - Specify how the target extends the result of a 597 /// setcc operation in a register. 598 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; } 599 600 /// setSchedulingPreference - Specify the target scheduling preference. 601 void setSchedulingPreference(SchedPreference Pref) { 602 SchedPreferenceInfo = Pref; 603 } 604 605 /// setShiftAmountFlavor - Describe how the target handles out of range shift 606 /// amounts. 607 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) { 608 ShiftAmtHandling = OORSA; 609 } 610 611 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 612 /// use _setjmp to implement llvm.setjmp or the non _ version. 613 /// Defaults to false. 614 void setUseUnderscoreSetJmp(bool Val) { 615 UseUnderscoreSetJmp = Val; 616 } 617 618 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 619 /// use _longjmp to implement llvm.longjmp or the non _ version. 620 /// Defaults to false. 621 void setUseUnderscoreLongJmp(bool Val) { 622 UseUnderscoreLongJmp = Val; 623 } 624 625 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 626 /// specifies the register that llvm.savestack/llvm.restorestack should save 627 /// and restore. 628 void setStackPointerRegisterToSaveRestore(unsigned R) { 629 StackPointerRegisterToSaveRestore = R; 630 } 631 632 /// setExceptionPointerRegister - If set to a physical register, this sets 633 /// the register that receives the exception address on entry to a landing 634 /// pad. 635 void setExceptionPointerRegister(unsigned R) { 636 ExceptionPointerRegister = R; 637 } 638 639 /// setExceptionSelectorRegister - If set to a physical register, this sets 640 /// the register that receives the exception typeid on entry to a landing 641 /// pad. 642 void setExceptionSelectorRegister(unsigned R) { 643 ExceptionSelectorRegister = R; 644 } 645 646 /// SelectIsExpensive - Tells the code generator not to expand operations 647 /// into sequences that use the select operations if possible. 648 void setSelectIsExpensive() { SelectIsExpensive = true; } 649 650 /// setIntDivIsCheap - Tells the code generator that integer divide is 651 /// expensive, and if possible, should be replaced by an alternate sequence 652 /// of instructions not containing an integer divide. 653 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 654 655 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 656 /// srl/add/sra for a signed divide by power of two, and let the target handle 657 /// it. 658 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 659 660 /// addRegisterClass - Add the specified register class as an available 661 /// regclass for the specified value type. This indicates the selector can 662 /// handle values of that class natively. 663 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { 664 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 665 RegClassForVT[VT] = RC; 666 } 667 668 /// computeRegisterProperties - Once all of the register classes are added, 669 /// this allows us to compute derived properties we expose. 670 void computeRegisterProperties(); 671 672 /// setOperationAction - Indicate that the specified operation does not work 673 /// with the specified type and indicate what to do about it. 674 void setOperationAction(unsigned Op, MVT::ValueType VT, 675 LegalizeAction Action) { 676 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) && 677 "Table isn't big enough!"); 678 OpActions[Op] &= ~(uint64_t(3UL) << VT*2); 679 OpActions[Op] |= (uint64_t)Action << VT*2; 680 } 681 682 /// setLoadXAction - Indicate that the specified load with extension does not 683 /// work with the with specified type and indicate what to do about it. 684 void setLoadXAction(unsigned ExtType, MVT::ValueType VT, 685 LegalizeAction Action) { 686 assert(VT < 32 && ExtType < sizeof(LoadXActions)/sizeof(LoadXActions[0]) && 687 "Table isn't big enough!"); 688 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); 689 LoadXActions[ExtType] |= (uint64_t)Action << VT*2; 690 } 691 692 /// setStoreXAction - Indicate that the specified store with truncation does 693 /// not work with the with specified type and indicate what to do about it. 694 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) { 695 assert(VT < 32 && "Table isn't big enough!"); 696 StoreXActions &= ~(uint64_t(3UL) << VT*2); 697 StoreXActions |= (uint64_t)Action << VT*2; 698 } 699 700 /// setIndexedLoadAction - Indicate that the specified indexed load does or 701 /// does not work with the with specified type and indicate what to do abort 702 /// it. NOTE: All indexed mode loads are initialized to Expand in 703 /// TargetLowering.cpp 704 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, 705 LegalizeAction Action) { 706 assert(VT < 32 && IdxMode < 707 sizeof(IndexedModeActions[0]) / sizeof(IndexedModeActions[0][0]) && 708 "Table isn't big enough!"); 709 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); 710 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; 711 } 712 713 /// setIndexedStoreAction - Indicate that the specified indexed store does or 714 /// does not work with the with specified type and indicate what to do about 715 /// it. NOTE: All indexed mode stores are initialized to Expand in 716 /// TargetLowering.cpp 717 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, 718 LegalizeAction Action) { 719 assert(VT < 32 && IdxMode < 720 sizeof(IndexedModeActions[1]) / sizeof(IndexedModeActions[1][0]) && 721 "Table isn't big enough!"); 722 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); 723 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; 724 } 725 726 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 727 /// promotion code defaults to trying a larger integer/fp until it can find 728 /// one that works. If that default is insufficient, this method can be used 729 /// by the target to override the default. 730 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, 731 MVT::ValueType DestVT) { 732 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; 733 } 734 735 /// addLegalFPImmediate - Indicate that this target can instruction select 736 /// the specified FP immediate natively. 737 void addLegalFPImmediate(double Imm) { 738 LegalFPImmediates.push_back(Imm); 739 } 740 741 /// setTargetDAGCombine - Targets should invoke this method for each target 742 /// independent node that they want to provide a custom DAG combiner for by 743 /// implementing the PerformDAGCombine virtual method. 744 void setTargetDAGCombine(ISD::NodeType NT) { 745 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 746 } 747 748 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 749 /// bytes); default is 200 750 void setJumpBufSize(unsigned Size) { 751 JumpBufSize = Size; 752 } 753 754 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 755 /// alignment (in bytes); default is 0 756 void setJumpBufAlignment(unsigned Align) { 757 JumpBufAlignment = Align; 758 } 759 760 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 761 /// (in number of instructions); default is 2. 762 void setIfCvtBlockSizeLimit(unsigned Limit) { 763 IfCvtBlockSizeLimit = Limit; 764 } 765 766public: 767 768 //===--------------------------------------------------------------------===// 769 // Lowering methods - These methods must be implemented by targets so that 770 // the SelectionDAGLowering code knows how to lower these. 771 // 772 773 /// LowerArguments - This hook must be implemented to indicate how we should 774 /// lower the arguments for the specified function, into the specified DAG. 775 virtual std::vector<SDOperand> 776 LowerArguments(Function &F, SelectionDAG &DAG); 777 778 /// LowerCallTo - This hook lowers an abstract call to a function into an 779 /// actual call. This returns a pair of operands. The first element is the 780 /// return value for the function (if RetTy is not VoidTy). The second 781 /// element is the outgoing token chain. 782 struct ArgListEntry { 783 SDOperand Node; 784 const Type* Ty; 785 bool isSExt; 786 bool isZExt; 787 bool isInReg; 788 bool isSRet; 789 790 ArgListEntry():isSExt(false), isZExt(false), isInReg(false), isSRet(false) { }; 791 }; 792 typedef std::vector<ArgListEntry> ArgListTy; 793 virtual std::pair<SDOperand, SDOperand> 794 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 795 bool isVarArg, unsigned CallingConv, bool isTailCall, 796 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); 797 798 /// LowerOperation - This callback is invoked for operations that are 799 /// unsupported by the target, which are registered to use 'custom' lowering, 800 /// and whose defined values are all legal. 801 /// If the target has no operations that require custom lowering, it need not 802 /// implement this. The default implementation of this aborts. 803 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 804 805 /// CustomPromoteOperation - This callback is invoked for operations that are 806 /// unsupported by the target, are registered to use 'custom' lowering, and 807 /// whose type needs to be promoted. 808 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG); 809 810 /// getTargetNodeName() - This method returns the name of a target specific 811 /// DAG node. 812 virtual const char *getTargetNodeName(unsigned Opcode) const; 813 814 //===--------------------------------------------------------------------===// 815 // Inline Asm Support hooks 816 // 817 818 enum ConstraintType { 819 C_Register, // Constraint represents a single register. 820 C_RegisterClass, // Constraint represents one or more registers. 821 C_Memory, // Memory constraint. 822 C_Other, // Something else. 823 C_Unknown // Unsupported constraint. 824 }; 825 826 /// getConstraintType - Given a constraint, return the type of constraint it 827 /// is for this target. 828 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 829 830 831 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 832 /// return a list of registers that can be used to satisfy the constraint. 833 /// This should only be used for C_RegisterClass constraints. 834 virtual std::vector<unsigned> 835 getRegClassForInlineAsmConstraint(const std::string &Constraint, 836 MVT::ValueType VT) const; 837 838 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 839 /// {edx}), return the register number and the register class for the 840 /// register. 841 /// 842 /// Given a register class constraint, like 'r', if this corresponds directly 843 /// to an LLVM register class, return a register of 0 and the register class 844 /// pointer. 845 /// 846 /// This should only be used for C_Register constraints. On error, 847 /// this returns a register number of 0 and a null register class pointer.. 848 virtual std::pair<unsigned, const TargetRegisterClass*> 849 getRegForInlineAsmConstraint(const std::string &Constraint, 850 MVT::ValueType VT) const; 851 852 853 /// isOperandValidForConstraint - Return the specified operand (possibly 854 /// modified) if the specified SDOperand is valid for the specified target 855 /// constraint letter, otherwise return null. 856 virtual SDOperand 857 isOperandValidForConstraint(SDOperand Op, char ConstraintLetter, 858 SelectionDAG &DAG); 859 860 //===--------------------------------------------------------------------===// 861 // Scheduler hooks 862 // 863 864 // InsertAtEndOfBasicBlock - This method should be implemented by targets that 865 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These 866 // instructions are special in various ways, which require special support to 867 // insert. The specified MachineInstr is created but not inserted into any 868 // basic blocks, and the scheduler passes ownership of it to this method. 869 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 870 MachineBasicBlock *MBB); 871 872 //===--------------------------------------------------------------------===// 873 // Addressing mode description hooks (used by LSR etc). 874 // 875 876 /// AddrMode - This represents an addressing mode of: 877 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 878 /// If BaseGV is null, there is no BaseGV. 879 /// If BaseOffs is zero, there is no base offset. 880 /// If HasBaseReg is false, there is no base register. 881 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 882 /// no scale. 883 /// 884 struct AddrMode { 885 GlobalValue *BaseGV; 886 int64_t BaseOffs; 887 bool HasBaseReg; 888 int64_t Scale; 889 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 890 }; 891 892 /// isLegalAddressingMode - Return true if the addressing mode represented by 893 /// AM is legal for this target, for a load/store of the specified type. 894 /// TODO: Handle pre/postinc as well. 895 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 896 897 //===--------------------------------------------------------------------===// 898 // Div utility functions 899 // 900 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, 901 std::vector<SDNode*>* Created) const; 902 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, 903 std::vector<SDNode*>* Created) const; 904 905 906 //===--------------------------------------------------------------------===// 907 // Runtime Library hooks 908 // 909 910 /// setLibcallName - Rename the default libcall routine name for the specified 911 /// libcall. 912 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 913 LibcallRoutineNames[Call] = Name; 914 } 915 916 /// getLibcallName - Get the libcall routine name for the specified libcall. 917 /// 918 const char *getLibcallName(RTLIB::Libcall Call) const { 919 return LibcallRoutineNames[Call]; 920 } 921 922 /// setCmpLibcallCC - Override the default CondCode to be used to test the 923 /// result of the comparison libcall against zero. 924 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 925 CmpLibcallCCs[Call] = CC; 926 } 927 928 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 929 /// the comparison libcall against zero. 930 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 931 return CmpLibcallCCs[Call]; 932 } 933 934private: 935 TargetMachine &TM; 936 const TargetData *TD; 937 938 /// IsLittleEndian - True if this is a little endian target. 939 /// 940 bool IsLittleEndian; 941 942 /// PointerTy - The type to use for pointers, usually i32 or i64. 943 /// 944 MVT::ValueType PointerTy; 945 946 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. 947 /// 948 bool UsesGlobalOffsetTable; 949 950 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 951 /// PointerTy is. 952 MVT::ValueType ShiftAmountTy; 953 954 OutOfRangeShiftAmount ShiftAmtHandling; 955 956 /// SelectIsExpensive - Tells the code generator not to expand operations 957 /// into sequences that use the select operations if possible. 958 bool SelectIsExpensive; 959 960 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 961 /// constants into a sequence of muls, adds, and shifts. This is a hack until 962 /// a real cost model is in place. If we ever optimize for size, this will be 963 /// set to true unconditionally. 964 bool IntDivIsCheap; 965 966 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 967 /// srl/add/sra for a signed divide by power of two, and let the target handle 968 /// it. 969 bool Pow2DivIsCheap; 970 971 /// SetCCResultTy - The type that SetCC operations use. This defaults to the 972 /// PointerTy. 973 MVT::ValueType SetCCResultTy; 974 975 /// SetCCResultContents - Information about the contents of the high-bits in 976 /// the result of a setcc comparison operation. 977 SetCCResultValue SetCCResultContents; 978 979 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 980 /// total cycles or lowest register usage. 981 SchedPreference SchedPreferenceInfo; 982 983 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 984 /// llvm.setjmp. Defaults to false. 985 bool UseUnderscoreSetJmp; 986 987 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 988 /// llvm.longjmp. Defaults to false. 989 bool UseUnderscoreLongJmp; 990 991 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 992 unsigned JumpBufSize; 993 994 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 995 /// buffers 996 unsigned JumpBufAlignment; 997 998 /// IfCvtBlockSizeLimit - The maximum allowed block size for if-conversion. 999 /// 1000 unsigned IfCvtBlockSizeLimit; 1001 1002 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1003 /// specifies the register that llvm.savestack/llvm.restorestack should save 1004 /// and restore. 1005 unsigned StackPointerRegisterToSaveRestore; 1006 1007 /// ExceptionPointerRegister - If set to a physical register, this specifies 1008 /// the register that receives the exception address on entry to a landing 1009 /// pad. 1010 unsigned ExceptionPointerRegister; 1011 1012 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1013 /// the register that receives the exception typeid on entry to a landing 1014 /// pad. 1015 unsigned ExceptionSelectorRegister; 1016 1017 /// RegClassForVT - This indicates the default register class to use for 1018 /// each ValueType the target supports natively. 1019 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1020 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE]; 1021 1022 /// TransformToType - For any value types we are promoting or expanding, this 1023 /// contains the value type that we are changing to. For Expanded types, this 1024 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1025 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1026 /// by the system, this holds the same type (e.g. i32 -> i32). 1027 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; 1028 1029 /// OpActions - For each operation and each value type, keep a LegalizeAction 1030 /// that indicates how instruction selection should deal with the operation. 1031 /// Most operations are Legal (aka, supported natively by the target), but 1032 /// operations that are not should be described. Note that operations on 1033 /// non-legal value types are not described here. 1034 uint64_t OpActions[156]; 1035 1036 /// LoadXActions - For each load of load extension type and each value type, 1037 /// keep a LegalizeAction that indicates how instruction selection should deal 1038 /// with the load. 1039 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE]; 1040 1041 /// StoreXActions - For each store with truncation of each value type, keep a 1042 /// LegalizeAction that indicates how instruction selection should deal with 1043 /// the store. 1044 uint64_t StoreXActions; 1045 1046 /// IndexedModeActions - For each indexed mode and each value type, keep a 1047 /// pair of LegalizeAction that indicates how instruction selection should 1048 /// deal with the load / store. 1049 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE]; 1050 1051 ValueTypeActionImpl ValueTypeActions; 1052 1053 std::vector<double> LegalFPImmediates; 1054 1055 std::vector<std::pair<MVT::ValueType, 1056 TargetRegisterClass*> > AvailableRegClasses; 1057 1058 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1059 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1060 /// which sets a bit in this array. 1061 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)]; 1062 1063 /// PromoteToType - For operations that must be promoted to a specific type, 1064 /// this holds the destination type. This map should be sparse, so don't hold 1065 /// it as an array. 1066 /// 1067 /// Targets add entries to this map with AddPromotedToType(..), clients access 1068 /// this with getTypeToPromoteTo(..). 1069 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType; 1070 1071 /// LibcallRoutineNames - Stores the name each libcall. 1072 /// 1073 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1074 1075 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1076 /// of each of the comparison libcall against zero. 1077 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1078 1079protected: 1080 /// When lowering %llvm.memset this field specifies the maximum number of 1081 /// store operations that may be substituted for the call to memset. Targets 1082 /// must set this value based on the cost threshold for that target. Targets 1083 /// should assume that the memset will be done using as many of the largest 1084 /// store operations first, followed by smaller ones, if necessary, per 1085 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1086 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1087 /// store. This only applies to setting a constant array of a constant size. 1088 /// @brief Specify maximum number of store instructions per memset call. 1089 unsigned maxStoresPerMemset; 1090 1091 /// When lowering %llvm.memcpy this field specifies the maximum number of 1092 /// store operations that may be substituted for a call to memcpy. Targets 1093 /// must set this value based on the cost threshold for that target. Targets 1094 /// should assume that the memcpy will be done using as many of the largest 1095 /// store operations first, followed by smaller ones, if necessary, per 1096 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1097 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1098 /// and one 1-byte store. This only applies to copying a constant array of 1099 /// constant size. 1100 /// @brief Specify maximum bytes of store instructions per memcpy call. 1101 unsigned maxStoresPerMemcpy; 1102 1103 /// When lowering %llvm.memmove this field specifies the maximum number of 1104 /// store instructions that may be substituted for a call to memmove. Targets 1105 /// must set this value based on the cost threshold for that target. Targets 1106 /// should assume that the memmove will be done using as many of the largest 1107 /// store operations first, followed by smaller ones, if necessary, per 1108 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1109 /// with 8-bit alignment would result in nine 1-byte stores. This only 1110 /// applies to copying a constant array of constant size. 1111 /// @brief Specify maximum bytes of store instructions per memmove call. 1112 unsigned maxStoresPerMemmove; 1113 1114 /// This field specifies whether the target machine permits unaligned memory 1115 /// accesses. This is used, for example, to determine the size of store 1116 /// operations when copying small arrays and other similar tasks. 1117 /// @brief Indicate whether the target permits unaligned memory accesses. 1118 bool allowUnalignedMemoryAccesses; 1119}; 1120} // end llvm namespace 1121 1122#endif 1123