TargetLowering.h revision fb384d61c78b60787ed65475d8403aee65023962
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/AddressingMode.h" 26#include "llvm/CallingConv.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Attributes.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/Support/CallSite.h" 31#include "llvm/CodeGen/SelectionDAGNodes.h" 32#include "llvm/CodeGen/RuntimeLibcalls.h" 33#include "llvm/Support/DebugLoc.h" 34#include "llvm/Target/TargetCallingConv.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class CallInst; 42 class CCState; 43 class FastISel; 44 class FunctionLoweringInfo; 45 class ImmutableCallSite; 46 class IntrinsicInst; 47 class MachineBasicBlock; 48 class MachineFunction; 49 class MachineInstr; 50 class MachineJumpTableInfo; 51 class MCContext; 52 class MCExpr; 53 template<typename T> class SmallVectorImpl; 54 class DataLayout; 55 class TargetRegisterClass; 56 class TargetLibraryInfo; 57 class TargetLoweringObjectFile; 58 class Value; 59 60 namespace Sched { 61 enum Preference { 62 None, // No preference 63 Source, // Follow source order. 64 RegPressure, // Scheduling for lowest register pressure. 65 Hybrid, // Scheduling for both latency and register pressure. 66 ILP, // Scheduling for ILP in low register pressure mode. 67 VLIW // Scheduling for VLIW targets. 68 }; 69 } 70 71 72//===----------------------------------------------------------------------===// 73/// TargetLowering - This class defines information used to lower LLVM code to 74/// legal SelectionDAG operators that the target instruction selector can accept 75/// natively. 76/// 77/// This class also defines callbacks that targets must implement to lower 78/// target-specific constructs to SelectionDAG operators. 79/// 80class TargetLowering { 81 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION; 82 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION; 83public: 84 /// LegalizeAction - This enum indicates whether operations are valid for a 85 /// target, and if not, what action should be used to make them valid. 86 enum LegalizeAction { 87 Legal, // The target natively supports this operation. 88 Promote, // This operation should be executed in a larger type. 89 Expand, // Try to expand this to other ops, otherwise use a libcall. 90 Custom // Use the LowerOperation hook to implement custom lowering. 91 }; 92 93 /// LegalizeTypeAction - This enum indicates whether a types are legal for a 94 /// target, and if not, what action should be used to make them valid. 95 enum LegalizeTypeAction { 96 TypeLegal, // The target natively supports this type. 97 TypePromoteInteger, // Replace this integer with a larger one. 98 TypeExpandInteger, // Split this integer into two of half the size. 99 TypeSoftenFloat, // Convert this float to a same size integer type. 100 TypeExpandFloat, // Split this float into two of half the size. 101 TypeScalarizeVector, // Replace this one-element vector with its element. 102 TypeSplitVector, // Split this vector into two of half the size. 103 TypeWidenVector // This vector should be widened into a larger vector. 104 }; 105 106 enum BooleanContent { // How the target represents true/false values. 107 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 108 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 109 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 110 }; 111 112 enum SelectSupportKind { 113 ScalarValSelect, // The target supports scalar selects (ex: cmov). 114 ScalarCondVectorVal, // The target supports selects with a scalar condition 115 // and vector values (ex: cmov). 116 VectorMaskSelect // The target supports vector selects with a vector 117 // mask (ex: x86 blends). 118 }; 119 120 static ISD::NodeType getExtendForContent(BooleanContent Content) { 121 switch (Content) { 122 case UndefinedBooleanContent: 123 // Extend by adding rubbish bits. 124 return ISD::ANY_EXTEND; 125 case ZeroOrOneBooleanContent: 126 // Extend by adding zero bits. 127 return ISD::ZERO_EXTEND; 128 case ZeroOrNegativeOneBooleanContent: 129 // Extend by copying the sign bit. 130 return ISD::SIGN_EXTEND; 131 } 132 llvm_unreachable("Invalid content kind"); 133 } 134 135 /// NOTE: The constructor takes ownership of TLOF. 136 explicit TargetLowering(const TargetMachine &TM, 137 const TargetLoweringObjectFile *TLOF); 138 virtual ~TargetLowering(); 139 140 const TargetMachine &getTargetMachine() const { return TM; } 141 const DataLayout *getDataLayout() const { return TD; } 142 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 143 144 bool isBigEndian() const { return !IsLittleEndian; } 145 bool isLittleEndian() const { return IsLittleEndian; } 146 // Return the pointer type for the given address space, defaults to 147 // the pointer type from the data layout. 148 // FIXME: The default needs to be removed once all the code is updated. 149 virtual MVT getPointerTy(uint32_t addrspace = 0) const { return PointerTy; } 150 virtual MVT getShiftAmountTy(EVT LHSTy) const; 151 152 /// isSelectExpensive - Return true if the select operation is expensive for 153 /// this target. 154 bool isSelectExpensive() const { return SelectIsExpensive; } 155 156 virtual bool isSelectSupported(SelectSupportKind kind) const { return true; } 157 158 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 159 /// a sequence of several shifts, adds, and multiplies for this target. 160 bool isIntDivCheap() const { return IntDivIsCheap; } 161 162 /// isSlowDivBypassed - Returns true if target has indicated at least one 163 /// type should be bypassed. 164 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); } 165 166 /// getBypassSlowDivTypes - Returns map of slow types for division or 167 /// remainder with corresponding fast types 168 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const { 169 return BypassSlowDivWidths; 170 } 171 172 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 173 /// srl/add/sra. 174 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 175 176 /// isJumpExpensive() - Return true if Flow Control is an expensive operation 177 /// that should be avoided. 178 bool isJumpExpensive() const { return JumpIsExpensive; } 179 180 /// isPredictableSelectExpensive - Return true if selects are only cheaper 181 /// than branches if the branch is unlikely to be predicted right. 182 bool isPredictableSelectExpensive() const { 183 return predictableSelectIsExpensive; 184 } 185 186 /// getSetCCResultType - Return the ValueType of the result of SETCC 187 /// operations. Also used to obtain the target's preferred type for 188 /// the condition operand of SELECT and BRCOND nodes. In the case of 189 /// BRCOND the argument passed is MVT::Other since there are no other 190 /// operands to get a type hint from. 191 virtual EVT getSetCCResultType(EVT VT) const; 192 193 /// getCmpLibcallReturnType - Return the ValueType for comparison 194 /// libcalls. Comparions libcalls include floating point comparion calls, 195 /// and Ordered/Unordered check calls on floating point numbers. 196 virtual 197 MVT::SimpleValueType getCmpLibcallReturnType() const; 198 199 /// getBooleanContents - For targets without i1 registers, this gives the 200 /// nature of the high-bits of boolean values held in types wider than i1. 201 /// "Boolean values" are special true/false values produced by nodes like 202 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 203 /// Not to be confused with general values promoted from i1. 204 /// Some cpus distinguish between vectors of boolean and scalars; the isVec 205 /// parameter selects between the two kinds. For example on X86 a scalar 206 /// boolean should be zero extended from i1, while the elements of a vector 207 /// of booleans should be sign extended from i1. 208 BooleanContent getBooleanContents(bool isVec) const { 209 return isVec ? BooleanVectorContents : BooleanContents; 210 } 211 212 /// getSchedulingPreference - Return target scheduling preference. 213 Sched::Preference getSchedulingPreference() const { 214 return SchedPreferenceInfo; 215 } 216 217 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 218 /// different scheduling heuristics for different nodes. This function returns 219 /// the preference (or none) for the given node. 220 virtual Sched::Preference getSchedulingPreference(SDNode *) const { 221 return Sched::None; 222 } 223 224 /// getRegClassFor - Return the register class that should be used for the 225 /// specified value type. 226 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const { 227 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 228 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 229 assert(RC && "This value type is not natively supported!"); 230 return RC; 231 } 232 233 /// getRepRegClassFor - Return the 'representative' register class for the 234 /// specified value type. The 'representative' register class is the largest 235 /// legal super-reg register class for the register class of the value type. 236 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 237 /// while the rep register class is GR64 on x86_64. 238 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { 239 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!"); 240 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; 241 return RC; 242 } 243 244 /// getRepRegClassCostFor - Return the cost of the 'representative' register 245 /// class for the specified value type. 246 virtual uint8_t getRepRegClassCostFor(EVT VT) const { 247 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!"); 248 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; 249 } 250 251 /// isTypeLegal - Return true if the target has native support for the 252 /// specified value type. This means that it has a register that directly 253 /// holds it without promotions or expansions. 254 bool isTypeLegal(EVT VT) const { 255 assert(!VT.isSimple() || 256 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 257 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 258 } 259 260 class ValueTypeActionImpl { 261 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum 262 /// that indicates how instruction selection should deal with the type. 263 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 264 265 public: 266 ValueTypeActionImpl() { 267 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 268 } 269 270 LegalizeTypeAction getTypeAction(MVT VT) const { 271 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; 272 } 273 274 void setTypeAction(EVT VT, LegalizeTypeAction Action) { 275 unsigned I = VT.getSimpleVT().SimpleTy; 276 ValueTypeActions[I] = Action; 277 } 278 }; 279 280 const ValueTypeActionImpl &getValueTypeActions() const { 281 return ValueTypeActions; 282 } 283 284 /// getTypeAction - Return how we should legalize values of this type, either 285 /// it is already legal (return 'Legal') or we need to promote it to a larger 286 /// type (return 'Promote'), or we need to expand it into multiple registers 287 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 288 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { 289 return getTypeConversion(Context, VT).first; 290 } 291 LegalizeTypeAction getTypeAction(MVT VT) const { 292 return ValueTypeActions.getTypeAction(VT); 293 } 294 295 /// getTypeToTransformTo - For types supported by the target, this is an 296 /// identity function. For types that must be promoted to larger types, this 297 /// returns the larger type to promote to. For integer types that are larger 298 /// than the largest integer register, this contains one step in the expansion 299 /// to get to the smaller register. For illegal floating point types, this 300 /// returns the integer type to transform to. 301 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 302 return getTypeConversion(Context, VT).second; 303 } 304 305 /// getTypeToExpandTo - For types supported by the target, this is an 306 /// identity function. For types that must be expanded (i.e. integer types 307 /// that are larger than the largest integer register or illegal floating 308 /// point types), this returns the largest legal type it will be expanded to. 309 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 310 assert(!VT.isVector()); 311 while (true) { 312 switch (getTypeAction(Context, VT)) { 313 case TypeLegal: 314 return VT; 315 case TypeExpandInteger: 316 VT = getTypeToTransformTo(Context, VT); 317 break; 318 default: 319 llvm_unreachable("Type is not legal nor is it to be expanded!"); 320 } 321 } 322 } 323 324 /// getVectorTypeBreakdown - Vector types are broken down into some number of 325 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 326 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 327 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 328 /// 329 /// This method returns the number of registers needed, and the VT for each 330 /// register. It also returns the VT and quantity of the intermediate values 331 /// before they are promoted/expanded. 332 /// 333 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 334 EVT &IntermediateVT, 335 unsigned &NumIntermediates, 336 EVT &RegisterVT) const; 337 338 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 339 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 340 /// this is the case, it returns true and store the intrinsic 341 /// information into the IntrinsicInfo that was passed to the function. 342 struct IntrinsicInfo { 343 unsigned opc; // target opcode 344 EVT memVT; // memory VT 345 const Value* ptrVal; // value representing memory location 346 int offset; // offset off of ptrVal 347 unsigned align; // alignment 348 bool vol; // is volatile? 349 bool readMem; // reads memory? 350 bool writeMem; // writes memory? 351 }; 352 353 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 354 unsigned /*Intrinsic*/) const { 355 return false; 356 } 357 358 /// isFPImmLegal - Returns true if the target can instruction select the 359 /// specified FP immediate natively. If false, the legalizer will materialize 360 /// the FP immediate as a load from a constant pool. 361 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const { 362 return false; 363 } 364 365 /// isShuffleMaskLegal - Targets can use this to indicate that they only 366 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 367 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 368 /// are assumed to be legal. 369 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 370 EVT /*VT*/) const { 371 return true; 372 } 373 374 /// canOpTrap - Returns true if the operation can trap for the value type. 375 /// VT must be a legal type. By default, we optimistically assume most 376 /// operations don't trap except for divide and remainder. 377 virtual bool canOpTrap(unsigned Op, EVT VT) const; 378 379 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 380 /// used by Targets can use this to indicate if there is a suitable 381 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 382 /// pool entry. 383 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 384 EVT /*VT*/) const { 385 return false; 386 } 387 388 /// getOperationAction - Return how this operation should be treated: either 389 /// it is legal, needs to be promoted to a larger size, needs to be 390 /// expanded to some other code sequence, or the target has a custom expander 391 /// for it. 392 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 393 if (VT.isExtended()) return Expand; 394 // If a target-specific SDNode requires legalization, require the target 395 // to provide custom legalization for it. 396 if (Op > array_lengthof(OpActions[0])) return Custom; 397 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 398 return (LegalizeAction)OpActions[I][Op]; 399 } 400 401 /// isOperationLegalOrCustom - Return true if the specified operation is 402 /// legal on this target or can be made legal with custom lowering. This 403 /// is used to help guide high-level lowering decisions. 404 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 405 return (VT == MVT::Other || isTypeLegal(VT)) && 406 (getOperationAction(Op, VT) == Legal || 407 getOperationAction(Op, VT) == Custom); 408 } 409 410 /// isOperationLegal - Return true if the specified operation is legal on this 411 /// target. 412 bool isOperationLegal(unsigned Op, EVT VT) const { 413 return (VT == MVT::Other || isTypeLegal(VT)) && 414 getOperationAction(Op, VT) == Legal; 415 } 416 417 /// getLoadExtAction - Return how this load with extension should be treated: 418 /// either it is legal, needs to be promoted to a larger size, needs to be 419 /// expanded to some other code sequence, or the target has a custom expander 420 /// for it. 421 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { 422 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 423 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 424 "Table isn't big enough!"); 425 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 426 } 427 428 /// isLoadExtLegal - Return true if the specified load with extension is legal 429 /// on this target. 430 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 431 return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal; 432 } 433 434 /// getTruncStoreAction - Return how this store with truncation should be 435 /// treated: either it is legal, needs to be promoted to a larger size, needs 436 /// to be expanded to some other code sequence, or the target has a custom 437 /// expander for it. 438 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 439 assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE && 440 MemVT.getSimpleVT() < MVT::LAST_VALUETYPE && 441 "Table isn't big enough!"); 442 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] 443 [MemVT.getSimpleVT().SimpleTy]; 444 } 445 446 /// isTruncStoreLegal - Return true if the specified store with truncation is 447 /// legal on this target. 448 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 449 return isTypeLegal(ValVT) && MemVT.isSimple() && 450 getTruncStoreAction(ValVT, MemVT) == Legal; 451 } 452 453 /// getIndexedLoadAction - Return how the indexed load should be treated: 454 /// either it is legal, needs to be promoted to a larger size, needs to be 455 /// expanded to some other code sequence, or the target has a custom expander 456 /// for it. 457 LegalizeAction 458 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 459 assert(IdxMode < ISD::LAST_INDEXED_MODE && 460 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 461 "Table isn't big enough!"); 462 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 463 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 464 } 465 466 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 467 /// on this target. 468 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 469 return VT.isSimple() && 470 (getIndexedLoadAction(IdxMode, VT) == Legal || 471 getIndexedLoadAction(IdxMode, VT) == Custom); 472 } 473 474 /// getIndexedStoreAction - Return how the indexed store should be treated: 475 /// either it is legal, needs to be promoted to a larger size, needs to be 476 /// expanded to some other code sequence, or the target has a custom expander 477 /// for it. 478 LegalizeAction 479 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 480 assert(IdxMode < ISD::LAST_INDEXED_MODE && 481 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 482 "Table isn't big enough!"); 483 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 484 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 485 } 486 487 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 488 /// on this target. 489 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 490 return VT.isSimple() && 491 (getIndexedStoreAction(IdxMode, VT) == Legal || 492 getIndexedStoreAction(IdxMode, VT) == Custom); 493 } 494 495 /// getCondCodeAction - Return how the condition code should be treated: 496 /// either it is legal, needs to be expanded to some other code sequence, 497 /// or the target has a custom expander for it. 498 LegalizeAction 499 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 500 assert((unsigned)CC < array_lengthof(CondCodeActions) && 501 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 502 "Table isn't big enough!"); 503 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 504 /// value and the upper 27 bits index into the second dimension of the 505 /// array to select what 64bit value to use. 506 LegalizeAction Action = (LegalizeAction) 507 ((CondCodeActions[CC][VT.getSimpleVT().SimpleTy >> 5] 508 >> (2*(VT.getSimpleVT().SimpleTy & 0x1F))) & 3); 509 assert(Action != Promote && "Can't promote condition code!"); 510 return Action; 511 } 512 513 /// isCondCodeLegal - Return true if the specified condition code is legal 514 /// on this target. 515 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 516 return getCondCodeAction(CC, VT) == Legal || 517 getCondCodeAction(CC, VT) == Custom; 518 } 519 520 521 /// getTypeToPromoteTo - If the action for this operation is to promote, this 522 /// method returns the ValueType to promote to. 523 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 524 assert(getOperationAction(Op, VT) == Promote && 525 "This operation isn't promoted!"); 526 527 // See if this has an explicit type specified. 528 std::map<std::pair<unsigned, MVT::SimpleValueType>, 529 MVT::SimpleValueType>::const_iterator PTTI = 530 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 531 if (PTTI != PromoteToType.end()) return PTTI->second; 532 533 assert((VT.isInteger() || VT.isFloatingPoint()) && 534 "Cannot autopromote this type, add it with AddPromotedToType."); 535 536 EVT NVT = VT; 537 do { 538 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 539 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 540 "Didn't find type to promote to!"); 541 } while (!isTypeLegal(NVT) || 542 getOperationAction(Op, NVT) == Promote); 543 return NVT; 544 } 545 546 /// getValueType - Return the EVT corresponding to this LLVM type. 547 /// This is fixed by the LLVM operations except for the pointer size. If 548 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 549 /// counterpart (e.g. structs), otherwise it will assert. 550 EVT getValueType(Type *Ty, bool AllowUnknown = false) const { 551 // Lower scalar pointers to native pointer types. 552 if (Ty->isPointerTy()) return PointerTy; 553 554 if (Ty->isVectorTy()) { 555 VectorType *VTy = cast<VectorType>(Ty); 556 Type *Elm = VTy->getElementType(); 557 // Lower vectors of pointers to native pointer types. 558 if (Elm->isPointerTy()) 559 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext()); 560 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), 561 VTy->getNumElements()); 562 } 563 return EVT::getEVT(Ty, AllowUnknown); 564 } 565 566 567 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 568 /// function arguments in the caller parameter area. This is the actual 569 /// alignment, not its logarithm. 570 virtual unsigned getByValTypeAlignment(Type *Ty) const; 571 572 /// getRegisterType - Return the type of registers that this ValueType will 573 /// eventually require. 574 EVT getRegisterType(MVT VT) const { 575 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 576 return RegisterTypeForVT[VT.SimpleTy]; 577 } 578 579 /// getRegisterType - Return the type of registers that this ValueType will 580 /// eventually require. 581 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 582 if (VT.isSimple()) { 583 assert((unsigned)VT.getSimpleVT().SimpleTy < 584 array_lengthof(RegisterTypeForVT)); 585 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 586 } 587 if (VT.isVector()) { 588 EVT VT1, RegisterVT; 589 unsigned NumIntermediates; 590 (void)getVectorTypeBreakdown(Context, VT, VT1, 591 NumIntermediates, RegisterVT); 592 return RegisterVT; 593 } 594 if (VT.isInteger()) { 595 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 596 } 597 llvm_unreachable("Unsupported extended type!"); 598 } 599 600 /// getNumRegisters - Return the number of registers that this ValueType will 601 /// eventually require. This is one for any types promoted to live in larger 602 /// registers, but may be more than one for types (like i64) that are split 603 /// into pieces. For types like i140, which are first promoted then expanded, 604 /// it is the number of registers needed to hold all the bits of the original 605 /// type. For an i140 on a 32 bit machine this means 5 registers. 606 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 607 if (VT.isSimple()) { 608 assert((unsigned)VT.getSimpleVT().SimpleTy < 609 array_lengthof(NumRegistersForVT)); 610 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 611 } 612 if (VT.isVector()) { 613 EVT VT1, VT2; 614 unsigned NumIntermediates; 615 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 616 } 617 if (VT.isInteger()) { 618 unsigned BitWidth = VT.getSizeInBits(); 619 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 620 return (BitWidth + RegWidth - 1) / RegWidth; 621 } 622 llvm_unreachable("Unsupported extended type!"); 623 } 624 625 /// ShouldShrinkFPConstant - If true, then instruction selection should 626 /// seek to shrink the FP constant of the specified type to a smaller type 627 /// in order to save space and / or reduce runtime. 628 virtual bool ShouldShrinkFPConstant(EVT) const { return true; } 629 630 /// hasTargetDAGCombine - If true, the target has custom DAG combine 631 /// transformations that it can perform for the specified node. 632 bool hasTargetDAGCombine(ISD::NodeType NT) const { 633 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 634 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 635 } 636 637 /// This function returns the maximum number of store operations permitted 638 /// to replace a call to llvm.memset. The value is set by the target at the 639 /// performance threshold for such a replacement. If OptSize is true, 640 /// return the limit for functions that have OptSize attribute. 641 /// @brief Get maximum # of store operations permitted for llvm.memset 642 unsigned getMaxStoresPerMemset(bool OptSize) const { 643 return OptSize ? maxStoresPerMemsetOptSize : maxStoresPerMemset; 644 } 645 646 /// This function returns the maximum number of store operations permitted 647 /// to replace a call to llvm.memcpy. The value is set by the target at the 648 /// performance threshold for such a replacement. If OptSize is true, 649 /// return the limit for functions that have OptSize attribute. 650 /// @brief Get maximum # of store operations permitted for llvm.memcpy 651 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 652 return OptSize ? maxStoresPerMemcpyOptSize : maxStoresPerMemcpy; 653 } 654 655 /// This function returns the maximum number of store operations permitted 656 /// to replace a call to llvm.memmove. The value is set by the target at the 657 /// performance threshold for such a replacement. If OptSize is true, 658 /// return the limit for functions that have OptSize attribute. 659 /// @brief Get maximum # of store operations permitted for llvm.memmove 660 unsigned getMaxStoresPerMemmove(bool OptSize) const { 661 return OptSize ? maxStoresPerMemmoveOptSize : maxStoresPerMemmove; 662 } 663 664 /// This function returns true if the target allows unaligned memory accesses. 665 /// of the specified type. This is used, for example, in situations where an 666 /// array copy/move/set is converted to a sequence of store operations. It's 667 /// use helps to ensure that such replacements don't generate code that causes 668 /// an alignment error (trap) on the target machine. 669 /// @brief Determine if the target supports unaligned memory accesses. 670 virtual bool allowsUnalignedMemoryAccesses(EVT) const { 671 return false; 672 } 673 674 /// This function returns true if the target would benefit from code placement 675 /// optimization. 676 /// @brief Determine if the target should perform code placement optimization. 677 bool shouldOptimizeCodePlacement() const { 678 return benefitFromCodePlacementOpt; 679 } 680 681 /// getOptimalMemOpType - Returns the target specific optimal type for load 682 /// and store operations as a result of memset, memcpy, and memmove 683 /// lowering. If DstAlign is zero that means it's safe to destination 684 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 685 /// means there isn't a need to check it against alignment requirement, 686 /// probably because the source does not need to be loaded. If 687 /// 'IsZeroVal' is true, that means it's safe to return a 688 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 689 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 690 /// constant so it does not need to be loaded. 691 /// It returns EVT::Other if the type should be determined using generic 692 /// target-independent logic. 693 virtual EVT getOptimalMemOpType(uint64_t /*Size*/, 694 unsigned /*DstAlign*/, unsigned /*SrcAlign*/, 695 bool /*IsZeroVal*/, 696 bool /*MemcpyStrSrc*/, 697 MachineFunction &/*MF*/) const { 698 return MVT::Other; 699 } 700 701 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 702 /// to implement llvm.setjmp. 703 bool usesUnderscoreSetJmp() const { 704 return UseUnderscoreSetJmp; 705 } 706 707 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 708 /// to implement llvm.longjmp. 709 bool usesUnderscoreLongJmp() const { 710 return UseUnderscoreLongJmp; 711 } 712 713 /// supportJumpTables - return whether the target can generate code for 714 /// jump tables. 715 bool supportJumpTables() const { 716 return SupportJumpTables; 717 } 718 719 /// getMinimumJumpTableEntries - return integer threshold on number of 720 /// blocks to use jump tables rather than if sequence. 721 int getMinimumJumpTableEntries() const { 722 return MinimumJumpTableEntries; 723 } 724 725 /// getStackPointerRegisterToSaveRestore - If a physical register, this 726 /// specifies the register that llvm.savestack/llvm.restorestack should save 727 /// and restore. 728 unsigned getStackPointerRegisterToSaveRestore() const { 729 return StackPointerRegisterToSaveRestore; 730 } 731 732 /// getExceptionPointerRegister - If a physical register, this returns 733 /// the register that receives the exception address on entry to a landing 734 /// pad. 735 unsigned getExceptionPointerRegister() const { 736 return ExceptionPointerRegister; 737 } 738 739 /// getExceptionSelectorRegister - If a physical register, this returns 740 /// the register that receives the exception typeid on entry to a landing 741 /// pad. 742 unsigned getExceptionSelectorRegister() const { 743 return ExceptionSelectorRegister; 744 } 745 746 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 747 /// set, the default is 200) 748 unsigned getJumpBufSize() const { 749 return JumpBufSize; 750 } 751 752 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 753 /// (if never set, the default is 0) 754 unsigned getJumpBufAlignment() const { 755 return JumpBufAlignment; 756 } 757 758 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 759 /// argument. 760 unsigned getMinStackArgumentAlignment() const { 761 return MinStackArgumentAlignment; 762 } 763 764 /// getMinFunctionAlignment - return the minimum function alignment. 765 /// 766 unsigned getMinFunctionAlignment() const { 767 return MinFunctionAlignment; 768 } 769 770 /// getPrefFunctionAlignment - return the preferred function alignment. 771 /// 772 unsigned getPrefFunctionAlignment() const { 773 return PrefFunctionAlignment; 774 } 775 776 /// getPrefLoopAlignment - return the preferred loop alignment. 777 /// 778 unsigned getPrefLoopAlignment() const { 779 return PrefLoopAlignment; 780 } 781 782 /// getShouldFoldAtomicFences - return whether the combiner should fold 783 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 784 /// 785 bool getShouldFoldAtomicFences() const { 786 return ShouldFoldAtomicFences; 787 } 788 789 /// getInsertFencesFor - return whether the DAG builder should automatically 790 /// insert fences and reduce ordering for atomics. 791 /// 792 bool getInsertFencesForAtomic() const { 793 return InsertFencesForAtomic; 794 } 795 796 /// getPreIndexedAddressParts - returns true by value, base pointer and 797 /// offset pointer and addressing mode by reference if the node's address 798 /// can be legally represented as pre-indexed load / store address. 799 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, 800 SDValue &/*Offset*/, 801 ISD::MemIndexedMode &/*AM*/, 802 SelectionDAG &/*DAG*/) const { 803 return false; 804 } 805 806 /// getPostIndexedAddressParts - returns true by value, base pointer and 807 /// offset pointer and addressing mode by reference if this node can be 808 /// combined with a load / store to form a post-indexed load / store. 809 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, 810 SDValue &/*Base*/, SDValue &/*Offset*/, 811 ISD::MemIndexedMode &/*AM*/, 812 SelectionDAG &/*DAG*/) const { 813 return false; 814 } 815 816 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 817 /// current function. The returned value is a member of the 818 /// MachineJumpTableInfo::JTEntryKind enum. 819 virtual unsigned getJumpTableEncoding() const; 820 821 virtual const MCExpr * 822 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/, 823 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/, 824 MCContext &/*Ctx*/) const { 825 llvm_unreachable("Need to implement this hook if target has custom JTIs"); 826 } 827 828 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 829 /// jumptable. 830 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 831 SelectionDAG &DAG) const; 832 833 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 834 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 835 /// MCExpr. 836 virtual const MCExpr * 837 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 838 unsigned JTI, MCContext &Ctx) const; 839 840 /// isOffsetFoldingLegal - Return true if folding a constant offset 841 /// with the given GlobalAddress is legal. It is frequently not legal in 842 /// PIC relocation models. 843 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 844 845 /// getStackCookieLocation - Return true if the target stores stack 846 /// protector cookies at a fixed offset in some non-standard address 847 /// space, and populates the address space and offset as 848 /// appropriate. 849 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/, 850 unsigned &/*Offset*/) const { 851 return false; 852 } 853 854 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be 855 /// used for loads / stores from the global. 856 virtual unsigned getMaximalGlobalOffset() const { 857 return 0; 858 } 859 860 //===--------------------------------------------------------------------===// 861 // TargetLowering Optimization Methods 862 // 863 864 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 865 /// SDValues for returning information from TargetLowering to its clients 866 /// that want to combine 867 struct TargetLoweringOpt { 868 SelectionDAG &DAG; 869 bool LegalTys; 870 bool LegalOps; 871 SDValue Old; 872 SDValue New; 873 874 explicit TargetLoweringOpt(SelectionDAG &InDAG, 875 bool LT, bool LO) : 876 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 877 878 bool LegalTypes() const { return LegalTys; } 879 bool LegalOperations() const { return LegalOps; } 880 881 bool CombineTo(SDValue O, SDValue N) { 882 Old = O; 883 New = N; 884 return true; 885 } 886 887 /// ShrinkDemandedConstant - Check to see if the specified operand of the 888 /// specified instruction is a constant integer. If so, check to see if 889 /// there are any bits set in the constant that are not demanded. If so, 890 /// shrink the constant and return true. 891 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 892 893 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 894 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 895 /// cast, but it could be generalized for targets with other types of 896 /// implicit widening casts. 897 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 898 DebugLoc dl); 899 }; 900 901 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 902 /// DemandedMask bits of the result of Op are ever used downstream. If we can 903 /// use this information to simplify Op, create a new simplified DAG node and 904 /// return true, returning the original and new nodes in Old and New. 905 /// Otherwise, analyze the expression and return a mask of KnownOne and 906 /// KnownZero bits for the expression (used to simplify the caller). 907 /// The KnownZero/One bits may only be accurate for those bits in the 908 /// DemandedMask. 909 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 910 APInt &KnownZero, APInt &KnownOne, 911 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 912 913 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 914 /// Mask are known to be either zero or one and return them in the 915 /// KnownZero/KnownOne bitsets. 916 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 917 APInt &KnownZero, 918 APInt &KnownOne, 919 const SelectionDAG &DAG, 920 unsigned Depth = 0) const; 921 922 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 923 /// targets that want to expose additional information about sign bits to the 924 /// DAG Combiner. 925 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 926 unsigned Depth = 0) const; 927 928 struct DAGCombinerInfo { 929 void *DC; // The DAG Combiner object. 930 bool BeforeLegalize; 931 bool BeforeLegalizeOps; 932 bool CalledByLegalizer; 933 public: 934 SelectionDAG &DAG; 935 936 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 937 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 938 CalledByLegalizer(cl), DAG(dag) {} 939 940 bool isBeforeLegalize() const { return BeforeLegalize; } 941 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 942 bool isCalledByLegalizer() const { return CalledByLegalizer; } 943 944 void AddToWorklist(SDNode *N); 945 void RemoveFromWorklist(SDNode *N); 946 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 947 bool AddTo = true); 948 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 949 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 950 951 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 952 }; 953 954 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 955 /// and cc. If it is unable to simplify it, return a null SDValue. 956 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 957 ISD::CondCode Cond, bool foldBooleans, 958 DAGCombinerInfo &DCI, DebugLoc dl) const; 959 960 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 961 /// node is a GlobalAddress + offset. 962 virtual bool 963 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 964 965 /// PerformDAGCombine - This method will be invoked for all target nodes and 966 /// for any target-independent nodes that the target has registered with 967 /// invoke it for. 968 /// 969 /// The semantics are as follows: 970 /// Return Value: 971 /// SDValue.Val == 0 - No change was made 972 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 973 /// otherwise - N should be replaced by the returned Operand. 974 /// 975 /// In addition, methods provided by DAGCombinerInfo may be used to perform 976 /// more complex transformations. 977 /// 978 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 979 980 /// isTypeDesirableForOp - Return true if the target has native support for 981 /// the specified value type and it is 'desirable' to use the type for the 982 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 983 /// instruction encodings are longer and some i16 instructions are slow. 984 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { 985 // By default, assume all legal types are desirable. 986 return isTypeLegal(VT); 987 } 988 989 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner 990 /// to transform a floating point op of specified opcode to a equivalent op of 991 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM. 992 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, 993 EVT /*VT*/) const { 994 return false; 995 } 996 997 /// IsDesirableToPromoteOp - This method query the target whether it is 998 /// beneficial for dag combiner to promote the specified node. If true, it 999 /// should return the desired promotion type by reference. 1000 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { 1001 return false; 1002 } 1003 1004 //===--------------------------------------------------------------------===// 1005 // TargetLowering Configuration Methods - These methods should be invoked by 1006 // the derived class constructor to configure this object for the target. 1007 // 1008 1009protected: 1010 /// setBooleanContents - Specify how the target extends the result of a 1011 /// boolean value from i1 to a wider type. See getBooleanContents. 1012 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 1013 /// setBooleanVectorContents - Specify how the target extends the result 1014 /// of a vector boolean value from a vector of i1 to a wider type. See 1015 /// getBooleanContents. 1016 void setBooleanVectorContents(BooleanContent Ty) { 1017 BooleanVectorContents = Ty; 1018 } 1019 1020 /// setSchedulingPreference - Specify the target scheduling preference. 1021 void setSchedulingPreference(Sched::Preference Pref) { 1022 SchedPreferenceInfo = Pref; 1023 } 1024 1025 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 1026 /// use _setjmp to implement llvm.setjmp or the non _ version. 1027 /// Defaults to false. 1028 void setUseUnderscoreSetJmp(bool Val) { 1029 UseUnderscoreSetJmp = Val; 1030 } 1031 1032 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 1033 /// use _longjmp to implement llvm.longjmp or the non _ version. 1034 /// Defaults to false. 1035 void setUseUnderscoreLongJmp(bool Val) { 1036 UseUnderscoreLongJmp = Val; 1037 } 1038 1039 /// setSupportJumpTables - Indicate whether the target can generate code for 1040 /// jump tables. 1041 void setSupportJumpTables(bool Val) { 1042 SupportJumpTables = Val; 1043 } 1044 1045 /// setMinimumJumpTableEntries - Indicate the number of blocks to generate 1046 /// jump tables rather than if sequence. 1047 void setMinimumJumpTableEntries(int Val) { 1048 MinimumJumpTableEntries = Val; 1049 } 1050 1051 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 1052 /// specifies the register that llvm.savestack/llvm.restorestack should save 1053 /// and restore. 1054 void setStackPointerRegisterToSaveRestore(unsigned R) { 1055 StackPointerRegisterToSaveRestore = R; 1056 } 1057 1058 /// setExceptionPointerRegister - If set to a physical register, this sets 1059 /// the register that receives the exception address on entry to a landing 1060 /// pad. 1061 void setExceptionPointerRegister(unsigned R) { 1062 ExceptionPointerRegister = R; 1063 } 1064 1065 /// setExceptionSelectorRegister - If set to a physical register, this sets 1066 /// the register that receives the exception typeid on entry to a landing 1067 /// pad. 1068 void setExceptionSelectorRegister(unsigned R) { 1069 ExceptionSelectorRegister = R; 1070 } 1071 1072 /// SelectIsExpensive - Tells the code generator not to expand operations 1073 /// into sequences that use the select operations if possible. 1074 void setSelectIsExpensive(bool isExpensive = true) { 1075 SelectIsExpensive = isExpensive; 1076 } 1077 1078 /// JumpIsExpensive - Tells the code generator not to expand sequence of 1079 /// operations into a separate sequences that increases the amount of 1080 /// flow control. 1081 void setJumpIsExpensive(bool isExpensive = true) { 1082 JumpIsExpensive = isExpensive; 1083 } 1084 1085 /// setIntDivIsCheap - Tells the code generator that integer divide is 1086 /// expensive, and if possible, should be replaced by an alternate sequence 1087 /// of instructions not containing an integer divide. 1088 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 1089 1090 /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass. 1091 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { 1092 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; 1093 } 1094 1095 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 1096 /// srl/add/sra for a signed divide by power of two, and let the target handle 1097 /// it. 1098 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 1099 1100 /// addRegisterClass - Add the specified register class as an available 1101 /// regclass for the specified value type. This indicates the selector can 1102 /// handle values of that class natively. 1103 void addRegisterClass(EVT VT, const TargetRegisterClass *RC) { 1104 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 1105 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 1106 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 1107 } 1108 1109 /// findRepresentativeClass - Return the largest legal super-reg register class 1110 /// of the register class for the specified type and its associated "cost". 1111 virtual std::pair<const TargetRegisterClass*, uint8_t> 1112 findRepresentativeClass(EVT VT) const; 1113 1114 /// computeRegisterProperties - Once all of the register classes are added, 1115 /// this allows us to compute derived properties we expose. 1116 void computeRegisterProperties(); 1117 1118 /// setOperationAction - Indicate that the specified operation does not work 1119 /// with the specified type and indicate what to do about it. 1120 void setOperationAction(unsigned Op, MVT VT, 1121 LegalizeAction Action) { 1122 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 1123 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 1124 } 1125 1126 /// setLoadExtAction - Indicate that the specified load with extension does 1127 /// not work with the specified type and indicate what to do about it. 1128 void setLoadExtAction(unsigned ExtType, MVT VT, 1129 LegalizeAction Action) { 1130 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 1131 "Table isn't big enough!"); 1132 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 1133 } 1134 1135 /// setTruncStoreAction - Indicate that the specified truncating store does 1136 /// not work with the specified type and indicate what to do about it. 1137 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1138 LegalizeAction Action) { 1139 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 1140 "Table isn't big enough!"); 1141 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 1142 } 1143 1144 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1145 /// does not work with the specified type and indicate what to do abort 1146 /// it. NOTE: All indexed mode loads are initialized to Expand in 1147 /// TargetLowering.cpp 1148 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1149 LegalizeAction Action) { 1150 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1151 (unsigned)Action < 0xf && "Table isn't big enough!"); 1152 // Load action are kept in the upper half. 1153 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1154 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1155 } 1156 1157 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1158 /// does not work with the specified type and indicate what to do about 1159 /// it. NOTE: All indexed mode stores are initialized to Expand in 1160 /// TargetLowering.cpp 1161 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1162 LegalizeAction Action) { 1163 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1164 (unsigned)Action < 0xf && "Table isn't big enough!"); 1165 // Store action are kept in the lower half. 1166 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1167 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1168 } 1169 1170 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1171 /// supported on the target and indicate what to do about it. 1172 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1173 LegalizeAction Action) { 1174 assert(VT < MVT::LAST_VALUETYPE && 1175 (unsigned)CC < array_lengthof(CondCodeActions) && 1176 "Table isn't big enough!"); 1177 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit 1178 /// value and the upper 27 bits index into the second dimension of the 1179 /// array to select what 64bit value to use. 1180 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1181 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2); 1182 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] 1183 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2; 1184 } 1185 1186 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1187 /// promotion code defaults to trying a larger integer/fp until it can find 1188 /// one that works. If that default is insufficient, this method can be used 1189 /// by the target to override the default. 1190 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1191 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1192 } 1193 1194 /// setTargetDAGCombine - Targets should invoke this method for each target 1195 /// independent node that they want to provide a custom DAG combiner for by 1196 /// implementing the PerformDAGCombine virtual method. 1197 void setTargetDAGCombine(ISD::NodeType NT) { 1198 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1199 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1200 } 1201 1202 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1203 /// bytes); default is 200 1204 void setJumpBufSize(unsigned Size) { 1205 JumpBufSize = Size; 1206 } 1207 1208 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1209 /// alignment (in bytes); default is 0 1210 void setJumpBufAlignment(unsigned Align) { 1211 JumpBufAlignment = Align; 1212 } 1213 1214 /// setMinFunctionAlignment - Set the target's minimum function alignment (in 1215 /// log2(bytes)) 1216 void setMinFunctionAlignment(unsigned Align) { 1217 MinFunctionAlignment = Align; 1218 } 1219 1220 /// setPrefFunctionAlignment - Set the target's preferred function alignment. 1221 /// This should be set if there is a performance benefit to 1222 /// higher-than-minimum alignment (in log2(bytes)) 1223 void setPrefFunctionAlignment(unsigned Align) { 1224 PrefFunctionAlignment = Align; 1225 } 1226 1227 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1228 /// alignment is zero, it means the target does not care about loop alignment. 1229 /// The alignment is specified in log2(bytes). 1230 void setPrefLoopAlignment(unsigned Align) { 1231 PrefLoopAlignment = Align; 1232 } 1233 1234 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1235 /// argument (in log2(bytes)). 1236 void setMinStackArgumentAlignment(unsigned Align) { 1237 MinStackArgumentAlignment = Align; 1238 } 1239 1240 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1241 /// atomic operation intrinsics includes locking. Default is false. 1242 void setShouldFoldAtomicFences(bool fold) { 1243 ShouldFoldAtomicFences = fold; 1244 } 1245 1246 /// setInsertFencesForAtomic - Set if the DAG builder should 1247 /// automatically insert fences and reduce the order of atomic memory 1248 /// operations to Monotonic. 1249 void setInsertFencesForAtomic(bool fence) { 1250 InsertFencesForAtomic = fence; 1251 } 1252 1253public: 1254 //===--------------------------------------------------------------------===// 1255 // Lowering methods - These methods must be implemented by targets so that 1256 // the SelectionDAGLowering code knows how to lower these. 1257 // 1258 1259 /// LowerFormalArguments - This hook must be implemented to lower the 1260 /// incoming (formal) arguments, described by the Ins array, into the 1261 /// specified DAG. The implementation should fill in the InVals array 1262 /// with legal-type argument values, and return the resulting token 1263 /// chain value. 1264 /// 1265 virtual SDValue 1266 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1267 bool /*isVarArg*/, 1268 const SmallVectorImpl<ISD::InputArg> &/*Ins*/, 1269 DebugLoc /*dl*/, SelectionDAG &/*DAG*/, 1270 SmallVectorImpl<SDValue> &/*InVals*/) const { 1271 llvm_unreachable("Not Implemented"); 1272 } 1273 1274 struct ArgListEntry { 1275 SDValue Node; 1276 Type* Ty; 1277 bool isSExt : 1; 1278 bool isZExt : 1; 1279 bool isInReg : 1; 1280 bool isSRet : 1; 1281 bool isNest : 1; 1282 bool isByVal : 1; 1283 uint16_t Alignment; 1284 1285 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1286 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1287 }; 1288 typedef std::vector<ArgListEntry> ArgListTy; 1289 1290 /// CallLoweringInfo - This structure contains all information that is 1291 /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the 1292 /// SelectionDAG builder needs to lower a call, and targets will see this 1293 /// struct in their LowerCall implementation. 1294 struct CallLoweringInfo { 1295 SDValue Chain; 1296 Type *RetTy; 1297 bool RetSExt : 1; 1298 bool RetZExt : 1; 1299 bool IsVarArg : 1; 1300 bool IsInReg : 1; 1301 bool DoesNotReturn : 1; 1302 bool IsReturnValueUsed : 1; 1303 1304 // IsTailCall should be modified by implementations of 1305 // TargetLowering::LowerCall that perform tail call conversions. 1306 bool IsTailCall; 1307 1308 unsigned NumFixedArgs; 1309 CallingConv::ID CallConv; 1310 SDValue Callee; 1311 ArgListTy &Args; 1312 SelectionDAG &DAG; 1313 DebugLoc DL; 1314 ImmutableCallSite *CS; 1315 SmallVector<ISD::OutputArg, 32> Outs; 1316 SmallVector<SDValue, 32> OutVals; 1317 SmallVector<ISD::InputArg, 32> Ins; 1318 1319 1320 /// CallLoweringInfo - Constructs a call lowering context based on the 1321 /// ImmutableCallSite \p cs. 1322 CallLoweringInfo(SDValue chain, Type *retTy, 1323 FunctionType *FTy, bool isTailCall, SDValue callee, 1324 ArgListTy &args, SelectionDAG &dag, DebugLoc dl, 1325 ImmutableCallSite &cs) 1326 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attributes::SExt)), 1327 RetZExt(cs.paramHasAttr(0, Attributes::ZExt)), IsVarArg(FTy->isVarArg()), 1328 IsInReg(cs.paramHasAttr(0, Attributes::InReg)), 1329 DoesNotReturn(cs.doesNotReturn()), 1330 IsReturnValueUsed(!cs.getInstruction()->use_empty()), 1331 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()), 1332 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag), 1333 DL(dl), CS(&cs) {} 1334 1335 /// CallLoweringInfo - Constructs a call lowering context based on the 1336 /// provided call information. 1337 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt, 1338 bool isVarArg, bool isInReg, unsigned numFixedArgs, 1339 CallingConv::ID callConv, bool isTailCall, 1340 bool doesNotReturn, bool isReturnValueUsed, SDValue callee, 1341 ArgListTy &args, SelectionDAG &dag, DebugLoc dl) 1342 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt), 1343 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn), 1344 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall), 1345 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee), 1346 Args(args), DAG(dag), DL(dl), CS(NULL) {} 1347 }; 1348 1349 /// LowerCallTo - This function lowers an abstract call to a function into an 1350 /// actual call. This returns a pair of operands. The first element is the 1351 /// return value for the function (if RetTy is not VoidTy). The second 1352 /// element is the outgoing token chain. It calls LowerCall to do the actual 1353 /// lowering. 1354 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const; 1355 1356 /// LowerCall - This hook must be implemented to lower calls into the 1357 /// the specified DAG. The outgoing arguments to the call are described 1358 /// by the Outs array, and the values to be returned by the call are 1359 /// described by the Ins array. The implementation should fill in the 1360 /// InVals array with legal-type return values from the call, and return 1361 /// the resulting token chain value. 1362 virtual SDValue 1363 LowerCall(CallLoweringInfo &/*CLI*/, 1364 SmallVectorImpl<SDValue> &/*InVals*/) const { 1365 llvm_unreachable("Not Implemented"); 1366 } 1367 1368 /// HandleByVal - Target-specific cleanup for formal ByVal parameters. 1369 virtual void HandleByVal(CCState *, unsigned &) const {} 1370 1371 /// CanLowerReturn - This hook should be implemented to check whether the 1372 /// return values described by the Outs array can fit into the return 1373 /// registers. If false is returned, an sret-demotion is performed. 1374 /// 1375 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, 1376 MachineFunction &/*MF*/, bool /*isVarArg*/, 1377 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 1378 LLVMContext &/*Context*/) const 1379 { 1380 // Return true by default to get preexisting behavior. 1381 return true; 1382 } 1383 1384 /// LowerReturn - This hook must be implemented to lower outgoing 1385 /// return values, described by the Outs array, into the specified 1386 /// DAG. The implementation should return the resulting token chain 1387 /// value. 1388 /// 1389 virtual SDValue 1390 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1391 bool /*isVarArg*/, 1392 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 1393 const SmallVectorImpl<SDValue> &/*OutVals*/, 1394 DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const { 1395 llvm_unreachable("Not Implemented"); 1396 } 1397 1398 /// isUsedByReturnOnly - Return true if result of the specified node is used 1399 /// by a return node only. It also compute and return the input chain for the 1400 /// tail call. 1401 /// This is used to determine whether it is possible 1402 /// to codegen a libcall as tail call at legalization time. 1403 virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const { 1404 return false; 1405 } 1406 1407 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the 1408 /// call instruction as a tail call. This is used by optimization passes to 1409 /// determine if it's profitable to duplicate return instructions to enable 1410 /// tailcall optimization. 1411 virtual bool mayBeEmittedAsTailCall(CallInst *) const { 1412 return false; 1413 } 1414 1415 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or 1416 /// sign extend a zeroext/signext integer argument or return value. 1417 /// FIXME: Most C calling convention requires the return type to be promoted, 1418 /// but this is not true all the time, e.g. i1 on x86-64. It is also not 1419 /// necessary for non-C calling conventions. The frontend should handle this 1420 /// and include all of the necessary information. 1421 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1422 ISD::NodeType /*ExtendKind*/) const { 1423 EVT MinVT = getRegisterType(Context, MVT::i32); 1424 return VT.bitsLT(MinVT) ? MinVT : VT; 1425 } 1426 1427 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1428 /// to legalize nodes with an illegal operand type but legal result types. 1429 /// It replaces the LowerOperation callback in the type Legalizer. 1430 /// The reason we can not do away with LowerOperation entirely is that 1431 /// LegalizeDAG isn't yet ready to use this callback. 1432 /// TODO: Consider merging with ReplaceNodeResults. 1433 1434 /// The target places new result values for the node in Results (their number 1435 /// and types must exactly match those of the original return values of 1436 /// the node), or leaves Results empty, which indicates that the node is not 1437 /// to be custom lowered after all. 1438 /// The default implementation calls LowerOperation. 1439 virtual void LowerOperationWrapper(SDNode *N, 1440 SmallVectorImpl<SDValue> &Results, 1441 SelectionDAG &DAG) const; 1442 1443 /// LowerOperation - This callback is invoked for operations that are 1444 /// unsupported by the target, which are registered to use 'custom' lowering, 1445 /// and whose defined values are all legal. 1446 /// If the target has no operations that require custom lowering, it need not 1447 /// implement this. The default implementation of this aborts. 1448 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1449 1450 /// ReplaceNodeResults - This callback is invoked when a node result type is 1451 /// illegal for the target, and the operation was registered to use 'custom' 1452 /// lowering for that result type. The target places new result values for 1453 /// the node in Results (their number and types must exactly match those of 1454 /// the original return values of the node), or leaves Results empty, which 1455 /// indicates that the node is not to be custom lowered after all. 1456 /// 1457 /// If the target has no operations that require custom lowering, it need not 1458 /// implement this. The default implementation aborts. 1459 virtual void ReplaceNodeResults(SDNode * /*N*/, 1460 SmallVectorImpl<SDValue> &/*Results*/, 1461 SelectionDAG &/*DAG*/) const { 1462 llvm_unreachable("ReplaceNodeResults not implemented for this target!"); 1463 } 1464 1465 /// getTargetNodeName() - This method returns the name of a target specific 1466 /// DAG node. 1467 virtual const char *getTargetNodeName(unsigned Opcode) const; 1468 1469 /// createFastISel - This method returns a target specific FastISel object, 1470 /// or null if the target does not support "fast" ISel. 1471 virtual FastISel *createFastISel(FunctionLoweringInfo &, 1472 const TargetLibraryInfo *) const { 1473 return 0; 1474 } 1475 1476 //===--------------------------------------------------------------------===// 1477 // Inline Asm Support hooks 1478 // 1479 1480 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1481 /// call to be explicit llvm code if it wants to. This is useful for 1482 /// turning simple inline asms into LLVM intrinsics, which gives the 1483 /// compiler more information about the behavior of the code. 1484 virtual bool ExpandInlineAsm(CallInst *) const { 1485 return false; 1486 } 1487 1488 enum ConstraintType { 1489 C_Register, // Constraint represents specific register(s). 1490 C_RegisterClass, // Constraint represents any of register(s) in class. 1491 C_Memory, // Memory constraint. 1492 C_Other, // Something else. 1493 C_Unknown // Unsupported constraint. 1494 }; 1495 1496 enum ConstraintWeight { 1497 // Generic weights. 1498 CW_Invalid = -1, // No match. 1499 CW_Okay = 0, // Acceptable. 1500 CW_Good = 1, // Good weight. 1501 CW_Better = 2, // Better weight. 1502 CW_Best = 3, // Best weight. 1503 1504 // Well-known weights. 1505 CW_SpecificReg = CW_Okay, // Specific register operands. 1506 CW_Register = CW_Good, // Register operands. 1507 CW_Memory = CW_Better, // Memory operands. 1508 CW_Constant = CW_Best, // Constant operand. 1509 CW_Default = CW_Okay // Default or don't know type. 1510 }; 1511 1512 /// AsmOperandInfo - This contains information for each constraint that we are 1513 /// lowering. 1514 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1515 /// ConstraintCode - This contains the actual string for the code, like "m". 1516 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1517 /// most closely matches the operand. 1518 std::string ConstraintCode; 1519 1520 /// ConstraintType - Information about the constraint code, e.g. Register, 1521 /// RegisterClass, Memory, Other, Unknown. 1522 TargetLowering::ConstraintType ConstraintType; 1523 1524 /// CallOperandval - If this is the result output operand or a 1525 /// clobber, this is null, otherwise it is the incoming operand to the 1526 /// CallInst. This gets modified as the asm is processed. 1527 Value *CallOperandVal; 1528 1529 /// ConstraintVT - The ValueType for the operand value. 1530 EVT ConstraintVT; 1531 1532 /// isMatchingInputConstraint - Return true of this is an input operand that 1533 /// is a matching constraint like "4". 1534 bool isMatchingInputConstraint() const; 1535 1536 /// getMatchedOperand - If this is an input matching constraint, this method 1537 /// returns the output operand it matches. 1538 unsigned getMatchedOperand() const; 1539 1540 /// Copy constructor for copying from an AsmOperandInfo. 1541 AsmOperandInfo(const AsmOperandInfo &info) 1542 : InlineAsm::ConstraintInfo(info), 1543 ConstraintCode(info.ConstraintCode), 1544 ConstraintType(info.ConstraintType), 1545 CallOperandVal(info.CallOperandVal), 1546 ConstraintVT(info.ConstraintVT) { 1547 } 1548 1549 /// Copy constructor for copying from a ConstraintInfo. 1550 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1551 : InlineAsm::ConstraintInfo(info), 1552 ConstraintType(TargetLowering::C_Unknown), 1553 CallOperandVal(0), ConstraintVT(MVT::Other) { 1554 } 1555 }; 1556 1557 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; 1558 1559 /// ParseConstraints - Split up the constraint string from the inline 1560 /// assembly value into the specific constraints and their prefixes, 1561 /// and also tie in the associated operand values. 1562 /// If this returns an empty vector, and if the constraint string itself 1563 /// isn't empty, there was an error parsing. 1564 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; 1565 1566 /// Examine constraint type and operand type and determine a weight value. 1567 /// The operand object must already have been set up with the operand type. 1568 virtual ConstraintWeight getMultipleConstraintMatchWeight( 1569 AsmOperandInfo &info, int maIndex) const; 1570 1571 /// Examine constraint string and operand type and determine a weight value. 1572 /// The operand object must already have been set up with the operand type. 1573 virtual ConstraintWeight getSingleConstraintMatchWeight( 1574 AsmOperandInfo &info, const char *constraint) const; 1575 1576 /// ComputeConstraintToUse - Determines the constraint code and constraint 1577 /// type to use for the specific AsmOperandInfo, setting 1578 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1579 /// being passed in is available, it can be passed in as Op, otherwise an 1580 /// empty SDValue can be passed. 1581 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1582 SDValue Op, 1583 SelectionDAG *DAG = 0) const; 1584 1585 /// getConstraintType - Given a constraint, return the type of constraint it 1586 /// is for this target. 1587 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1588 1589 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1590 /// {edx}), return the register number and the register class for the 1591 /// register. 1592 /// 1593 /// Given a register class constraint, like 'r', if this corresponds directly 1594 /// to an LLVM register class, return a register of 0 and the register class 1595 /// pointer. 1596 /// 1597 /// This should only be used for C_Register constraints. On error, 1598 /// this returns a register number of 0 and a null register class pointer.. 1599 virtual std::pair<unsigned, const TargetRegisterClass*> 1600 getRegForInlineAsmConstraint(const std::string &Constraint, 1601 EVT VT) const; 1602 1603 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1604 /// with another that has more specific requirements based on the type of the 1605 /// corresponding operand. This returns null if there is no replacement to 1606 /// make. 1607 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1608 1609 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1610 /// vector. If it is invalid, don't add anything to Ops. 1611 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 1612 std::vector<SDValue> &Ops, 1613 SelectionDAG &DAG) const; 1614 1615 //===--------------------------------------------------------------------===// 1616 // Instruction Emitting Hooks 1617 // 1618 1619 // EmitInstrWithCustomInserter - This method should be implemented by targets 1620 // that mark instructions with the 'usesCustomInserter' flag. These 1621 // instructions are special in various ways, which require special support to 1622 // insert. The specified MachineInstr is created but not inserted into any 1623 // basic blocks, and this method is called to expand it into a sequence of 1624 // instructions, potentially also creating new basic blocks and control flow. 1625 virtual MachineBasicBlock * 1626 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 1627 1628 /// AdjustInstrPostInstrSelection - This method should be implemented by 1629 /// targets that mark instructions with the 'hasPostISelHook' flag. These 1630 /// instructions must be adjusted after instruction selection by target hooks. 1631 /// e.g. To fill in optional defs for ARM 's' setting instructions. 1632 virtual void 1633 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 1634 1635 //===--------------------------------------------------------------------===// 1636 // Addressing mode description hooks (used by LSR etc). 1637 // 1638 1639 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the 1640 /// same BB as Load/Store instructions reading the address. This allows as 1641 /// much computation as possible to be done in the address mode for that 1642 /// operand. This hook lets targets also pass back when this should be done 1643 /// on intrinsics which load/store. 1644 virtual bool GetAddrModeArguments(IntrinsicInst *I, 1645 SmallVectorImpl<Value*> &Ops, 1646 Type *&AccessTy) const { 1647 return false; 1648 } 1649 1650 /// isLegalAddressingMode - Return true if the addressing mode represented by 1651 /// AM is legal for this target, for a load/store of the specified type. 1652 /// The type may be VoidTy, in which case only return true if the addressing 1653 /// mode is legal for a load/store of any legal type. 1654 /// TODO: Handle pre/postinc as well. 1655 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 1656 1657 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1658 /// icmp immediate, that is the target has icmp instructions which can compare 1659 /// a register against the immediate without having to materialize the 1660 /// immediate into a register. 1661 virtual bool isLegalICmpImmediate(int64_t) const { 1662 return true; 1663 } 1664 1665 /// isLegalAddImmediate - Return true if the specified immediate is legal 1666 /// add immediate, that is the target has add instructions which can add 1667 /// a register with the immediate without having to materialize the 1668 /// immediate into a register. 1669 virtual bool isLegalAddImmediate(int64_t) const { 1670 return true; 1671 } 1672 1673 /// isTruncateFree - Return true if it's free to truncate a value of 1674 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1675 /// register EAX to i16 by referencing its sub-register AX. 1676 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1677 return false; 1678 } 1679 1680 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const { 1681 return false; 1682 } 1683 1684 /// isZExtFree - Return true if any actual instruction that defines a 1685 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1686 /// register. This does not necessarily include registers defined in 1687 /// unknown ways, such as incoming arguments, or copies from unknown 1688 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1689 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1690 /// all instructions that define 32-bit values implicit zero-extend the 1691 /// result out to 64 bits. 1692 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1693 return false; 1694 } 1695 1696 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const { 1697 return false; 1698 } 1699 1700 /// isFNegFree - Return true if an fneg operation is free to the point where 1701 /// it is never worthwhile to replace it with a bitwise operation. 1702 virtual bool isFNegFree(EVT) const { 1703 return false; 1704 } 1705 1706 /// isFAbsFree - Return true if an fneg operation is free to the point where 1707 /// it is never worthwhile to replace it with a bitwise operation. 1708 virtual bool isFAbsFree(EVT) const { 1709 return false; 1710 } 1711 1712 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 1713 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 1714 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 1715 /// is expanded to mul + add. 1716 virtual bool isFMAFasterThanMulAndAdd(EVT) const { 1717 return false; 1718 } 1719 1720 /// isNarrowingProfitable - Return true if it's profitable to narrow 1721 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1722 /// from i32 to i8 but not from i32 to i16. 1723 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { 1724 return false; 1725 } 1726 1727 //===--------------------------------------------------------------------===// 1728 // Div utility functions 1729 // 1730 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 1731 SelectionDAG &DAG) const; 1732 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 1733 std::vector<SDNode*>* Created) const; 1734 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 1735 std::vector<SDNode*>* Created) const; 1736 1737 1738 //===--------------------------------------------------------------------===// 1739 // Runtime Library hooks 1740 // 1741 1742 /// setLibcallName - Rename the default libcall routine name for the specified 1743 /// libcall. 1744 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1745 LibcallRoutineNames[Call] = Name; 1746 } 1747 1748 /// getLibcallName - Get the libcall routine name for the specified libcall. 1749 /// 1750 const char *getLibcallName(RTLIB::Libcall Call) const { 1751 return LibcallRoutineNames[Call]; 1752 } 1753 1754 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1755 /// result of the comparison libcall against zero. 1756 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1757 CmpLibcallCCs[Call] = CC; 1758 } 1759 1760 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1761 /// the comparison libcall against zero. 1762 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1763 return CmpLibcallCCs[Call]; 1764 } 1765 1766 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1767 /// specified libcall. 1768 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1769 LibcallCallingConvs[Call] = CC; 1770 } 1771 1772 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1773 /// specified libcall. 1774 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1775 return LibcallCallingConvs[Call]; 1776 } 1777 1778private: 1779 const TargetMachine &TM; 1780 const DataLayout *TD; 1781 const TargetLoweringObjectFile &TLOF; 1782 1783 /// PointerTy - The type to use for pointers for the default address space, 1784 /// usually i32 or i64. 1785 /// 1786 MVT PointerTy; 1787 1788 /// IsLittleEndian - True if this is a little endian target. 1789 /// 1790 bool IsLittleEndian; 1791 1792 /// SelectIsExpensive - Tells the code generator not to expand operations 1793 /// into sequences that use the select operations if possible. 1794 bool SelectIsExpensive; 1795 1796 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1797 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1798 /// a real cost model is in place. If we ever optimize for size, this will be 1799 /// set to true unconditionally. 1800 bool IntDivIsCheap; 1801 1802 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or 1803 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the 1804 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned 1805 /// integer div/rem when the operands are positive and less than 256. 1806 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths; 1807 1808 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1809 /// srl/add/sra for a signed divide by power of two, and let the target handle 1810 /// it. 1811 bool Pow2DivIsCheap; 1812 1813 /// JumpIsExpensive - Tells the code generator that it shouldn't generate 1814 /// extra flow control instructions and should attempt to combine flow 1815 /// control instructions via predication. 1816 bool JumpIsExpensive; 1817 1818 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1819 /// llvm.setjmp. Defaults to false. 1820 bool UseUnderscoreSetJmp; 1821 1822 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1823 /// llvm.longjmp. Defaults to false. 1824 bool UseUnderscoreLongJmp; 1825 1826 /// SupportJumpTables - Whether the target can generate code for jumptables. 1827 /// If it's not true, then each jumptable must be lowered into if-then-else's. 1828 bool SupportJumpTables; 1829 1830 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables. 1831 int MinimumJumpTableEntries; 1832 1833 /// BooleanContents - Information about the contents of the high-bits in 1834 /// boolean values held in a type wider than i1. See getBooleanContents. 1835 BooleanContent BooleanContents; 1836 /// BooleanVectorContents - Information about the contents of the high-bits 1837 /// in boolean vector values when the element type is wider than i1. See 1838 /// getBooleanContents. 1839 BooleanContent BooleanVectorContents; 1840 1841 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1842 /// total cycles or lowest register usage. 1843 Sched::Preference SchedPreferenceInfo; 1844 1845 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1846 unsigned JumpBufSize; 1847 1848 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1849 /// buffers 1850 unsigned JumpBufAlignment; 1851 1852 /// MinStackArgumentAlignment - The minimum alignment that any argument 1853 /// on the stack needs to have. 1854 /// 1855 unsigned MinStackArgumentAlignment; 1856 1857 /// MinFunctionAlignment - The minimum function alignment (used when 1858 /// optimizing for size, and to prevent explicitly provided alignment 1859 /// from leading to incorrect code). 1860 /// 1861 unsigned MinFunctionAlignment; 1862 1863 /// PrefFunctionAlignment - The preferred function alignment (used when 1864 /// alignment unspecified and optimizing for speed). 1865 /// 1866 unsigned PrefFunctionAlignment; 1867 1868 /// PrefLoopAlignment - The preferred loop alignment. 1869 /// 1870 unsigned PrefLoopAlignment; 1871 1872 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1873 /// be folded into the enclosed atomic intrinsic instruction by the 1874 /// combiner. 1875 bool ShouldFoldAtomicFences; 1876 1877 /// InsertFencesForAtomic - Whether the DAG builder should automatically 1878 /// insert fences and reduce ordering for atomics. (This will be set for 1879 /// for most architectures with weak memory ordering.) 1880 bool InsertFencesForAtomic; 1881 1882 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1883 /// specifies the register that llvm.savestack/llvm.restorestack should save 1884 /// and restore. 1885 unsigned StackPointerRegisterToSaveRestore; 1886 1887 /// ExceptionPointerRegister - If set to a physical register, this specifies 1888 /// the register that receives the exception address on entry to a landing 1889 /// pad. 1890 unsigned ExceptionPointerRegister; 1891 1892 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1893 /// the register that receives the exception typeid on entry to a landing 1894 /// pad. 1895 unsigned ExceptionSelectorRegister; 1896 1897 /// RegClassForVT - This indicates the default register class to use for 1898 /// each ValueType the target supports natively. 1899 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1900 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1901 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1902 1903 /// RepRegClassForVT - This indicates the "representative" register class to 1904 /// use for each ValueType the target supports natively. This information is 1905 /// used by the scheduler to track register pressure. By default, the 1906 /// representative register class is the largest legal super-reg register 1907 /// class of the register class of the specified type. e.g. On x86, i8, i16, 1908 /// and i32's representative class would be GR32. 1909 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1910 1911 /// RepRegClassCostForVT - This indicates the "cost" of the "representative" 1912 /// register class for each ValueType. The cost is used by the scheduler to 1913 /// approximate register pressure. 1914 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1915 1916 /// TransformToType - For any value types we are promoting or expanding, this 1917 /// contains the value type that we are changing to. For Expanded types, this 1918 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1919 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1920 /// by the system, this holds the same type (e.g. i32 -> i32). 1921 EVT TransformToType[MVT::LAST_VALUETYPE]; 1922 1923 /// OpActions - For each operation and each value type, keep a LegalizeAction 1924 /// that indicates how instruction selection should deal with the operation. 1925 /// Most operations are Legal (aka, supported natively by the target), but 1926 /// operations that are not should be described. Note that operations on 1927 /// non-legal value types are not described here. 1928 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1929 1930 /// LoadExtActions - For each load extension type and each value type, 1931 /// keep a LegalizeAction that indicates how instruction selection should deal 1932 /// with a load of a specific value type and extension type. 1933 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1934 1935 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1936 /// indicates whether a truncating store of a specific value type and 1937 /// truncating type is legal. 1938 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1939 1940 /// IndexedModeActions - For each indexed mode and each value type, 1941 /// keep a pair of LegalizeAction that indicates how instruction 1942 /// selection should deal with the load / store. The first dimension is the 1943 /// value_type for the reference. The second dimension represents the various 1944 /// modes for load store. 1945 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1946 1947 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1948 /// LegalizeAction that indicates how instruction selection should 1949 /// deal with the condition code. 1950 /// Because each CC action takes up 2 bits, we need to have the array size 1951 /// be large enough to fit all of the value types. This can be done by 1952 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one. 1953 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1]; 1954 1955 ValueTypeActionImpl ValueTypeActions; 1956 1957 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; 1958 1959 LegalizeKind 1960 getTypeConversion(LLVMContext &Context, EVT VT) const { 1961 // If this is a simple type, use the ComputeRegisterProp mechanism. 1962 if (VT.isSimple()) { 1963 assert((unsigned)VT.getSimpleVT().SimpleTy < 1964 array_lengthof(TransformToType)); 1965 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 1966 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT()); 1967 1968 assert( 1969 (!(NVT.isSimple() && LA != TypeLegal) || 1970 ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != TypePromoteInteger) 1971 && "Promote may not follow Expand or Promote"); 1972 1973 return LegalizeKind(LA, NVT); 1974 } 1975 1976 // Handle Extended Scalar Types. 1977 if (!VT.isVector()) { 1978 assert(VT.isInteger() && "Float types must be simple"); 1979 unsigned BitSize = VT.getSizeInBits(); 1980 // First promote to a power-of-two size, then expand if necessary. 1981 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1982 EVT NVT = VT.getRoundIntegerType(Context); 1983 assert(NVT != VT && "Unable to round integer VT"); 1984 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1985 // Avoid multi-step promotion. 1986 if (NextStep.first == TypePromoteInteger) return NextStep; 1987 // Return rounded integer type. 1988 return LegalizeKind(TypePromoteInteger, NVT); 1989 } 1990 1991 return LegalizeKind(TypeExpandInteger, 1992 EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); 1993 } 1994 1995 // Handle vector types. 1996 unsigned NumElts = VT.getVectorNumElements(); 1997 EVT EltVT = VT.getVectorElementType(); 1998 1999 // Vectors with only one element are always scalarized. 2000 if (NumElts == 1) 2001 return LegalizeKind(TypeScalarizeVector, EltVT); 2002 2003 // Try to widen vector elements until a legal type is found. 2004 if (EltVT.isInteger()) { 2005 // Vectors with a number of elements that is not a power of two are always 2006 // widened, for example <3 x float> -> <4 x float>. 2007 if (!VT.isPow2VectorType()) { 2008 NumElts = (unsigned)NextPowerOf2(NumElts); 2009 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 2010 return LegalizeKind(TypeWidenVector, NVT); 2011 } 2012 2013 // Examine the element type. 2014 LegalizeKind LK = getTypeConversion(Context, EltVT); 2015 2016 // If type is to be expanded, split the vector. 2017 // <4 x i140> -> <2 x i140> 2018 if (LK.first == TypeExpandInteger) 2019 return LegalizeKind(TypeSplitVector, 2020 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 2021 2022 // Promote the integer element types until a legal vector type is found 2023 // or until the element integer type is too big. If a legal type was not 2024 // found, fallback to the usual mechanism of widening/splitting the 2025 // vector. 2026 while (1) { 2027 // Increase the bitwidth of the element to the next pow-of-two 2028 // (which is greater than 8 bits). 2029 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() 2030 ).getRoundIntegerType(Context); 2031 2032 // Stop trying when getting a non-simple element type. 2033 // Note that vector elements may be greater than legal vector element 2034 // types. Example: X86 XMM registers hold 64bit element on 32bit systems. 2035 if (!EltVT.isSimple()) break; 2036 2037 // Build a new vector type and check if it is legal. 2038 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 2039 // Found a legal promoted vector type. 2040 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 2041 return LegalizeKind(TypePromoteInteger, 2042 EVT::getVectorVT(Context, EltVT, NumElts)); 2043 } 2044 } 2045 2046 // Try to widen the vector until a legal type is found. 2047 // If there is no wider legal type, split the vector. 2048 while (1) { 2049 // Round up to the next power of 2. 2050 NumElts = (unsigned)NextPowerOf2(NumElts); 2051 2052 // If there is no simple vector type with this many elements then there 2053 // cannot be a larger legal vector type. Note that this assumes that 2054 // there are no skipped intermediate vector types in the simple types. 2055 if (!EltVT.isSimple()) break; 2056 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 2057 if (LargerVector == MVT()) break; 2058 2059 // If this type is legal then widen the vector. 2060 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 2061 return LegalizeKind(TypeWidenVector, LargerVector); 2062 } 2063 2064 // Widen odd vectors to next power of two. 2065 if (!VT.isPow2VectorType()) { 2066 EVT NVT = VT.getPow2VectorType(Context); 2067 return LegalizeKind(TypeWidenVector, NVT); 2068 } 2069 2070 // Vectors with illegal element types are expanded. 2071 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 2072 return LegalizeKind(TypeSplitVector, NVT); 2073 } 2074 2075 std::vector<std::pair<EVT, const TargetRegisterClass*> > AvailableRegClasses; 2076 2077 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 2078 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 2079 /// which sets a bit in this array. 2080 unsigned char 2081 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 2082 2083 /// PromoteToType - For operations that must be promoted to a specific type, 2084 /// this holds the destination type. This map should be sparse, so don't hold 2085 /// it as an array. 2086 /// 2087 /// Targets add entries to this map with AddPromotedToType(..), clients access 2088 /// this with getTypeToPromoteTo(..). 2089 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 2090 PromoteToType; 2091 2092 /// LibcallRoutineNames - Stores the name each libcall. 2093 /// 2094 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 2095 2096 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 2097 /// of each of the comparison libcall against zero. 2098 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 2099 2100 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 2101 /// libcall. 2102 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 2103 2104protected: 2105 /// When lowering \@llvm.memset this field specifies the maximum number of 2106 /// store operations that may be substituted for the call to memset. Targets 2107 /// must set this value based on the cost threshold for that target. Targets 2108 /// should assume that the memset will be done using as many of the largest 2109 /// store operations first, followed by smaller ones, if necessary, per 2110 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 2111 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 2112 /// store. This only applies to setting a constant array of a constant size. 2113 /// @brief Specify maximum number of store instructions per memset call. 2114 unsigned maxStoresPerMemset; 2115 2116 /// Maximum number of stores operations that may be substituted for the call 2117 /// to memset, used for functions with OptSize attribute. 2118 unsigned maxStoresPerMemsetOptSize; 2119 2120 /// When lowering \@llvm.memcpy this field specifies the maximum number of 2121 /// store operations that may be substituted for a call to memcpy. Targets 2122 /// must set this value based on the cost threshold for that target. Targets 2123 /// should assume that the memcpy will be done using as many of the largest 2124 /// store operations first, followed by smaller ones, if necessary, per 2125 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 2126 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 2127 /// and one 1-byte store. This only applies to copying a constant array of 2128 /// constant size. 2129 /// @brief Specify maximum bytes of store instructions per memcpy call. 2130 unsigned maxStoresPerMemcpy; 2131 2132 /// Maximum number of store operations that may be substituted for a call 2133 /// to memcpy, used for functions with OptSize attribute. 2134 unsigned maxStoresPerMemcpyOptSize; 2135 2136 /// When lowering \@llvm.memmove this field specifies the maximum number of 2137 /// store instructions that may be substituted for a call to memmove. Targets 2138 /// must set this value based on the cost threshold for that target. Targets 2139 /// should assume that the memmove will be done using as many of the largest 2140 /// store operations first, followed by smaller ones, if necessary, per 2141 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 2142 /// with 8-bit alignment would result in nine 1-byte stores. This only 2143 /// applies to copying a constant array of constant size. 2144 /// @brief Specify maximum bytes of store instructions per memmove call. 2145 unsigned maxStoresPerMemmove; 2146 2147 /// Maximum number of store instructions that may be substituted for a call 2148 /// to memmove, used for functions with OpSize attribute. 2149 unsigned maxStoresPerMemmoveOptSize; 2150 2151 /// This field specifies whether the target can benefit from code placement 2152 /// optimization. 2153 bool benefitFromCodePlacementOpt; 2154 2155 /// predictableSelectIsExpensive - Tells the code generator that select is 2156 /// more expensive than a branch if the branch is usually predicted right. 2157 bool predictableSelectIsExpensive; 2158 2159private: 2160 /// isLegalRC - Return true if the value types that can be represented by the 2161 /// specified register class are all legal. 2162 bool isLegalRC(const TargetRegisterClass *RC) const; 2163}; 2164 2165/// GetReturnInfo - Given an LLVM IR type and return type attributes, 2166/// compute the return value EVTs and flags, and optionally also 2167/// the offsets, if the return value is being lowered to memory. 2168void GetReturnInfo(Type* ReturnType, Attributes attr, 2169 SmallVectorImpl<ISD::OutputArg> &Outs, 2170 const TargetLowering &TLI); 2171 2172} // end llvm namespace 2173 2174#endif 2175