CriticalAntiDepBreaker.cpp revision 4de099d8ca651e00fa5fac22bace4f4dba2d0292
12e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin//===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===// 22e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 32e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// The LLVM Compiler Infrastructure 42e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 52e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// This file is distributed under the University of Illinois Open Source 62e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// License. See LICENSE.TXT for details. 72e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 82e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin//===----------------------------------------------------------------------===// 92e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// This file implements the CriticalAntiDepBreaker class, which 112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// implements register anti-dependence breaking along a blocks 122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// critical path during post-RA scheduler. 132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin//===----------------------------------------------------------------------===// 152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 164de099d8ca651e00fa5fac22bace4f4dba2d0292David Goodwin#define DEBUG_TYPE "post-RA-sched" 172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "CriticalAntiDepBreaker.h" 182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/CodeGen/MachineBasicBlock.h" 192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Target/TargetMachine.h" 212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Target/TargetRegisterInfo.h" 222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Support/Debug.h" 232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Support/ErrorHandling.h" 242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Support/raw_ostream.h" 252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinusing namespace llvm; 272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid GoodwinCriticalAntiDepBreaker:: 292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid GoodwinCriticalAntiDepBreaker(MachineFunction& MFi) : 302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepBreaker(), MF(MFi), 312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MRI(MF.getRegInfo()), 322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin TRI(MF.getTarget().getRegisterInfo()), 332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AllocatableSet(TRI->getAllocatableSet(MF)) 342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin{ 352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid GoodwinCriticalAntiDepBreaker::~CriticalAntiDepBreaker() { 382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { 412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Clear out the register class data. 422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin std::fill(Classes, array_endof(Classes), 432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin static_cast<const TargetRegisterClass *>(0)); 442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Initialize the indices to indicate that no registers are live. 462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin std::fill(KillIndices, array_endof(KillIndices), ~0u); 472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin std::fill(DefIndices, array_endof(DefIndices), BB->size()); 482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Clear "do not change" set. 502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KeepRegs.clear(); 512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn()); 532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Determine the live-out physregs for this block. 552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (IsReturnBlock) { 562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // In a return block, examine the function live-out regs. 572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(), 582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin E = MRI.liveout_end(); I != E; ++I) { 592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = *I; 602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[Reg] = BB->size(); 622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = ~0u; 632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Repeat, for all aliases. 642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AliasReg = *Alias; 662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AliasReg] = BB->size(); 682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AliasReg] = ~0u; 692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } else { 722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // In a non-return block, examine the live-in regs of all successors. 732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 742e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin SE = BB->succ_end(); SI != SE; ++SI) 752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), 762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin E = (*SI)->livein_end(); I != E; ++I) { 772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = *I; 782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[Reg] = BB->size(); 802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = ~0u; 812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Repeat, for all aliases. 822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AliasReg = *Alias; 842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AliasReg] = BB->size(); 862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AliasReg] = ~0u; 872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Mark live-out callee-saved registers. In a return block this is 922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // all callee-saved registers. In non-return this is any 932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // callee-saved register that is not saved in the prolog. 942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const MachineFrameInfo *MFI = MF.getFrameInfo(); 952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin BitVector Pristine = MFI->getPristineRegs(BB); 962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) { 972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = *I; 982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!IsReturnBlock && !Pristine.test(Reg)) continue; 992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 1002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[Reg] = BB->size(); 1012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = ~0u; 1022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Repeat, for all aliases. 1032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 1042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AliasReg = *Alias; 1052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 1062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AliasReg] = BB->size(); 1072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AliasReg] = ~0u; 1082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::FinishBlock() { 1132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.clear(); 1142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KeepRegs.clear(); 1152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, 1182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned InsertPosIndex) { 1192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(Count < InsertPosIndex && "Instruction index out of expected range!"); 1202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Any register which was defined within the previous scheduling region 1222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // may have been rescheduled and its lifetime may overlap with registers 1232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // in ways not reflected in our current liveness state. For each such 1242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // register, adjust the liveness state to be conservatively correct. 1252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) 1262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) { 1272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(KillIndices[Reg] == ~0u && "Clobbered register is live!"); 1282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Mark this register to be non-renamable. 1292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 1302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Move the def index to the end of the previous region, to reflect 1312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // that the def could theoretically have been scheduled at the end. 1322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = InsertPosIndex; 1332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin PrescanInstruction(MI); 1362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin ScanInstruction(MI, Count); 1372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin/// CriticalPathStep - Return the next SUnit after SU on the bottom-up 1402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin/// critical path. 1412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinstatic SDep *CriticalPathStep(SUnit *SU) { 1422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin SDep *Next = 0; 1432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned NextDepth = 0; 1442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Find the predecessor edge with the greatest depth. 1452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end(); 1462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin P != PE; ++P) { 1472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin SUnit *PredSU = P->getSUnit(); 1482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned PredLatency = P->getLatency(); 1492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned PredTotalLatency = PredSU->getDepth() + PredLatency; 1502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // In the case of a latency tie, prefer an anti-dependency edge over 1512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // other types of edges. 1522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (NextDepth < PredTotalLatency || 1532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) { 1542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin NextDepth = PredTotalLatency; 1552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Next = &*P; 1562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return Next; 1592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { 1622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Scan the register operands for this instruction and update 1632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Classes and RegRefs. 1642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 1662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 1672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 1682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 1692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const TargetRegisterClass *NewRC = 0; 1702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (i < MI->getDesc().getNumOperands()) 1722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); 1732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1742e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // For now, only allow the register to be changed if its register 1752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // class is consistent across all uses. 1762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!Classes[Reg] && NewRC) 1772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = NewRC; 1782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (!NewRC || Classes[Reg] != NewRC) 1792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 1802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Now check for aliases. 1822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 1832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If an alias of the reg is used during the live range, give up. 1842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Note that this allows us to skip checking if AntiDepReg 1852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // overlaps with any of the aliases, among other things. 1862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AliasReg = *Alias; 1872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Classes[AliasReg]) { 1882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 1892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 1902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If we're still willing to consider this register, note the reference. 1942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1)) 1952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.insert(std::make_pair(Reg, &MO)); 1962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // It's not safe to change register allocation for source operands of 1982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // that have special allocation requirements. 1992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (MO.isUse() && MI->getDesc().hasExtraSrcRegAllocReq()) { 2002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KeepRegs.insert(Reg)) { 2012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Subreg = TRI->getSubRegisters(Reg); 2022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin *Subreg; ++Subreg) 2032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KeepRegs.insert(*Subreg); 2042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 2082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI, 2102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Count) { 2112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Update liveness. 2122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Proceding upwards, registers that are defed but not used in this 2132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // instruction are now dead. 2142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 2162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 2172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 2182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 2192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isDef()) continue; 2202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Ignore two-addr defs. 2212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (MI->isRegTiedToUseOperand(i)) continue; 2222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = Count; 2242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[Reg] = ~0u; 2252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[Reg] == ~0u) != 2262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[Reg] == ~0u)) && 2272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for Reg!"); 2282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KeepRegs.erase(Reg); 2292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = 0; 2302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.erase(Reg); 2312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Repeat, for all subregs. 2322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Subreg = TRI->getSubRegisters(Reg); 2332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin *Subreg; ++Subreg) { 2342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned SubregReg = *Subreg; 2352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[SubregReg] = Count; 2362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[SubregReg] = ~0u; 2372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KeepRegs.erase(SubregReg); 2382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[SubregReg] = 0; 2392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.erase(SubregReg); 2402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Conservatively mark super-registers as unusable. 2422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Super = TRI->getSuperRegisters(Reg); 2432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin *Super; ++Super) { 2442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned SuperReg = *Super; 2452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1); 2462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 2502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 2512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 2522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 2532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isUse()) continue; 2542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const TargetRegisterClass *NewRC = 0; 2562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (i < MI->getDesc().getNumOperands()) 2572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); 2582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // For now, only allow the register to be changed if its register 2602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // class is consistent across all uses. 2612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!Classes[Reg] && NewRC) 2622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = NewRC; 2632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (!NewRC || Classes[Reg] != NewRC) 2642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 2652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.insert(std::make_pair(Reg, &MO)); 2672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // It wasn't previously live but now it is, this is a kill. 2692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[Reg] == ~0u) { 2702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[Reg] = Count; 2712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = ~0u; 2722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[Reg] == ~0u) != 2732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[Reg] == ~0u)) && 2742e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for Reg!"); 2752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Repeat, for all aliases. 2772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 2782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AliasReg = *Alias; 2792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[AliasReg] == ~0u) { 2802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AliasReg] = Count; 2812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AliasReg] = ~0u; 2822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 2862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinunsigned 2882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid GoodwinCriticalAntiDepBreaker::findSuitableFreeRegister(unsigned AntiDepReg, 2892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned LastNewReg, 2902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const TargetRegisterClass *RC) { 2912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF), 2922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RE = RC->allocation_order_end(MF); R != RE; ++R) { 2932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned NewReg = *R; 2942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't replace a register with itself. 2952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (NewReg == AntiDepReg) continue; 2962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't replace a register with one that was recently used to repair 2972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // an anti-dependence with this AntiDepReg, because that would 2982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // re-introduce that anti-dependence. 2992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (NewReg == LastNewReg) continue; 3002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If NewReg is dead and NewReg's most recent def is not before 3012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg. 3022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) && 3032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for AntiDepReg!"); 3042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) && 3052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for NewReg!"); 3062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[NewReg] != ~0u || 3072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) || 3082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AntiDepReg] > DefIndices[NewReg]) 3092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin continue; 3102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return NewReg; 3112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // No registers are free and available! 3142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return 0; 3152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 3162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinunsigned CriticalAntiDepBreaker:: 3182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid GoodwinBreakAntiDependencies(std::vector<SUnit>& SUnits, 3194de099d8ca651e00fa5fac22bace4f4dba2d0292David Goodwin CandidateMap& Candidates, 3202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineBasicBlock::iterator& Begin, 3212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineBasicBlock::iterator& End, 3222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned InsertPosIndex) { 3232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // The code below assumes that there is at least one instruction, 3242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // so just duck out immediately if the block is empty. 3252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (SUnits.empty()) return 0; 3262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Find the node at the bottom of the critical path. 3282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin SUnit *Max = 0; 3292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 3302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin SUnit *SU = &SUnits[i]; 3312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) 3322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Max = SU; 3332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#ifndef NDEBUG 3362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin { 3372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DEBUG(errs() << "Critical path has total latency " 3382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << (Max->getDepth() + Max->Latency) << "\n"); 3392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DEBUG(errs() << "Available regs:"); 3402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { 3412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[Reg] == ~0u) 3422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DEBUG(errs() << " " << TRI->getName(Reg)); 3432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DEBUG(errs() << '\n'); 3452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#endif 3472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Track progress along the critical path through the SUnit graph as we walk 3492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // the instructions. 3502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin SUnit *CriticalPathSU = Max; 3512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); 3522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Consider this pattern: 3542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 3552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 3562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 3572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 3582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 3592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 3602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 3612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 3622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // There are three anti-dependencies here, and without special care, 3632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // we'd break all of them using the same register: 3642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 3652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 3662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 3672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 3682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 3692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 3702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 3712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 3722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // because at each anti-dependence, B is the first register that 3732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // isn't A which is free. This re-introduces anti-dependencies 3742e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // at all but one of the original anti-dependencies that we were 3752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // trying to break. To avoid this, keep track of the most recent 3762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // register that each register was replaced with, avoid 3772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // using it to repair an anti-dependence on the same register. 3782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // This lets us produce this: 3792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 3802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 3812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 3822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 3832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // C = ... 3842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = C 3852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 3862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 3872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // This still has an anti-dependence on B, but at least it isn't on the 3882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // original critical path. 3892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 3902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // TODO: If we tracked more than one register here, we could potentially 3912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // fix that remaining critical edge too. This is a little more involved, 3922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // because unlike the most recent register, less recent registers should 3932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // still be considered, though only if no other registers are available. 3942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {}; 3952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Attempt to break anti-dependence edges on the critical path. Walk the 3972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // instructions from the bottom up, tracking information about liveness 3982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // as we go to help determine which registers are available. 3992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Broken = 0; 4002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Count = InsertPosIndex - 1; 4012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (MachineBasicBlock::iterator I = End, E = Begin; 4022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin I != E; --Count) { 4032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineInstr *MI = --I; 4042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Check if this instruction has a dependence on the critical path that 4062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // is an anti-dependence that we may be able to break. If it is, set 4072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // AntiDepReg to the non-zero register associated with the anti-dependence. 4082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 4092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // We limit our attention to the critical path as a heuristic to avoid 4102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // breaking anti-dependence edges that aren't going to significantly 4112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // impact the overall schedule. There are a limited number of registers 4122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // and we want to save them for the important edges. 4132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 4142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // TODO: Instructions with multiple defs could have multiple 4152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // anti-dependencies. The current code here only knows how to break one 4162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // edge per instruction. Note that we'd have to be able to break all of 4172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // the anti-dependencies in an instruction in order to be effective. 4182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AntiDepReg = 0; 4192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (MI == CriticalPathMI) { 4202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (SDep *Edge = CriticalPathStep(CriticalPathSU)) { 4212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin SUnit *NextSU = Edge->getSUnit(); 4222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Only consider anti-dependence edges. 4242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Edge->getKind() == SDep::Anti) { 4252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = Edge->getReg(); 4262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(AntiDepReg != 0 && "Anti-dependence on reg0?"); 4272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!AllocatableSet.test(AntiDepReg)) 4282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't break anti-dependencies on non-allocatable registers. 4292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 4302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (KeepRegs.count(AntiDepReg)) 4312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't break anti-dependencies if an use down below requires 4322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // this exact register. 4332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 4342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else { 4352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If the SUnit has other dependencies on the SUnit that it 4362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // anti-depends on, don't bother breaking the anti-dependency 4372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // since those edges would prevent such units from being 4382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // scheduled past each other regardless. 4392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 4402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Also, if there are dependencies on other SUnits with the 4412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // same register as the anti-dependency, don't attempt to 4422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // break it. 4432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (SUnit::pred_iterator P = CriticalPathSU->Preds.begin(), 4442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin PE = CriticalPathSU->Preds.end(); P != PE; ++P) 4452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (P->getSUnit() == NextSU ? 4462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : 4472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) { 4482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 4492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin break; 4502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathSU = NextSU; 4542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathMI = CriticalPathSU->getInstr(); 4552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } else { 4562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // We've reached the end of the critical path. 4572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathSU = 0; 4582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathMI = 0; 4592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin PrescanInstruction(MI); 4632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (MI->getDesc().hasExtraDefRegAllocReq()) 4652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If this instruction's defs have special allocation requirement, don't 4662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // break this anti-dependency. 4672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 4682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (AntiDepReg) { 4692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If this instruction has a use of AntiDepReg, breaking it 4702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // is invalid. 4712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 4732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 4742e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 4752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 4762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (MO.isUse() && AntiDepReg == Reg) { 4772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 4782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin break; 4792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Determine AntiDepReg's register class, if it is live and is 4842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // consistently used within a single class. 4852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0; 4862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert((AntiDepReg == 0 || RC != NULL) && 4872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Register should be live if it's causing an anti-dependence!"); 4882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 4892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 4902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Look for a suitable register to use to break the anti-depenence. 4922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 4932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // TODO: Instead of picking the first free register, consider which might 4942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // be the best. 4952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (AntiDepReg != 0) { 4962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (unsigned NewReg = findSuitableFreeRegister(AntiDepReg, 4972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin LastNewReg[AntiDepReg], 4982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RC)) { 4992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DEBUG(errs() << "Breaking anti-dependence edge on " 5002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << TRI->getName(AntiDepReg) 5012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << " with " << RegRefs.count(AntiDepReg) << " references" 5022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << " using " << TRI->getName(NewReg) << "!\n"); 5032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Update the references to the old register to refer to the new 5052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // register. 5062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin std::pair<std::multimap<unsigned, MachineOperand *>::iterator, 5072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin std::multimap<unsigned, MachineOperand *>::iterator> 5082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Range = RegRefs.equal_range(AntiDepReg); 5092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (std::multimap<unsigned, MachineOperand *>::iterator 5102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Q = Range.first, QE = Range.second; Q != QE; ++Q) 5112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Q->second->setReg(NewReg); 5122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // We just went back in time and modified history; the 5142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // liveness information for the anti-depenence reg is now 5152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // inconsistent. Set the state as if it were dead. 5162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[NewReg] = Classes[AntiDepReg]; 5172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[NewReg] = DefIndices[AntiDepReg]; 5182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[NewReg] = KillIndices[AntiDepReg]; 5192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[NewReg] == ~0u) != 5202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[NewReg] == ~0u)) && 5212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for NewReg!"); 5222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AntiDepReg] = 0; 5242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AntiDepReg] = KillIndices[AntiDepReg]; 5252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AntiDepReg] = ~0u; 5262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[AntiDepReg] == ~0u) != 5272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[AntiDepReg] == ~0u)) && 5282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for AntiDepReg!"); 5292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.erase(AntiDepReg); 5312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin LastNewReg[AntiDepReg] = NewReg; 5322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin ++Broken; 5332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin ScanInstruction(MI, Count); 5372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return Broken; 5402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 541