CriticalAntiDepBreaker.cpp revision b4566a999970b514d7c6973d99e293a6625d3f70
12e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin//===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===// 22e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 32e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// The LLVM Compiler Infrastructure 42e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 52e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// This file is distributed under the University of Illinois Open Source 62e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// License. See LICENSE.TXT for details. 72e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 82e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin//===----------------------------------------------------------------------===// 92e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// This file implements the CriticalAntiDepBreaker class, which 112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// implements register anti-dependence breaking along a blocks 122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// critical path during post-RA scheduler. 132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin//===----------------------------------------------------------------------===// 152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 164de099d8ca651e00fa5fac22bace4f4dba2d0292David Goodwin#define DEBUG_TYPE "post-RA-sched" 172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "CriticalAntiDepBreaker.h" 182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/CodeGen/MachineBasicBlock.h" 192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Target/TargetMachine.h" 2146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng#include "llvm/Target/TargetInstrInfo.h" 222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Target/TargetRegisterInfo.h" 232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Support/Debug.h" 242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Support/ErrorHandling.h" 252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Support/raw_ostream.h" 262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinusing namespace llvm; 282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid GoodwinCriticalAntiDepBreaker:: 30fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund OlesenCriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : 312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepBreaker(), MF(MFi), 322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MRI(MF.getRegInfo()), 3346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng TII(MF.getTarget().getInstrInfo()), 342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin TRI(MF.getTarget().getRegisterInfo()), 35fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund Olesen RegClassInfo(RCI), 369c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)), 379c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling KillIndices(TRI->getNumRegs(), 0), 389c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling DefIndices(TRI->getNumRegs(), 0) {} 392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid GoodwinCriticalAntiDepBreaker::~CriticalAntiDepBreaker() { 412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { 44990d2857654cb80e46d207533834be3047494830David Goodwin const unsigned BBSize = BB->size(); 459c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { 469c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling // Clear out the register class data. 479c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling Classes[i] = static_cast<const TargetRegisterClass *>(0); 489c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling 499c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling // Initialize the indices to indicate that no registers are live. 50990d2857654cb80e46d207533834be3047494830David Goodwin KillIndices[i] = ~0u; 51990d2857654cb80e46d207533834be3047494830David Goodwin DefIndices[i] = BBSize; 52990d2857654cb80e46d207533834be3047494830David Goodwin } 532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Clear "do not change" set. 552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KeepRegs.clear(); 562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 575a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool IsReturnBlock = (!BB->empty() && BB->back().isReturn()); 582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Determine the live-out physregs for this block. 602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (IsReturnBlock) { 612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // In a return block, examine the function live-out regs. 622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(), 632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin E = MRI.liveout_end(); I != E; ++I) { 642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = *I; 652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[Reg] = BB->size(); 672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = ~0u; 689c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling 692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Repeat, for all aliases. 702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AliasReg = *Alias; 722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AliasReg] = BB->size(); 742e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AliasReg] = ~0u; 752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 7746df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng } 7846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng 7946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // In a non-return block, examine the live-in regs of all successors. 8046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Note a return block can have successors if the return instruction is 8146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // predicated. 8246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin SE = BB->succ_end(); SI != SE; ++SI) 8446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), 852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin E = (*SI)->livein_end(); I != E; ++I) { 8646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng unsigned Reg = *I; 8746df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 8846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng KillIndices[Reg] = BB->size(); 8946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng DefIndices[Reg] = ~0u; 909c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling 9146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Repeat, for all aliases. 9246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 9346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng unsigned AliasReg = *Alias; 9446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 9546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng KillIndices[AliasReg] = BB->size(); 9646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng DefIndices[AliasReg] = ~0u; 972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 9846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng } 992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Mark live-out callee-saved registers. In a return block this is 1012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // all callee-saved registers. In non-return this is any 1022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // callee-saved register that is not saved in the prolog. 1032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const MachineFrameInfo *MFI = MF.getFrameInfo(); 1042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin BitVector Pristine = MFI->getPristineRegs(BB); 105977679d6034791fd48a344e5b990503ba50fc242Evan Cheng for (const unsigned *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { 1062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = *I; 1072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!IsReturnBlock && !Pristine.test(Reg)) continue; 1082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 1092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[Reg] = BB->size(); 1102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = ~0u; 1119c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling 1122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Repeat, for all aliases. 1132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 1142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AliasReg = *Alias; 1152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 1162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AliasReg] = BB->size(); 1172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AliasReg] = ~0u; 1182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::FinishBlock() { 1232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.clear(); 1242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KeepRegs.clear(); 1252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, 1282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned InsertPosIndex) { 129b0812f114b83a32c4b90a4b553c7177c557558b5Dale Johannesen if (MI->isDebugValue()) 130b0812f114b83a32c4b90a4b553c7177c557558b5Dale Johannesen return; 1312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(Count < InsertPosIndex && "Instruction index out of expected range!"); 1322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 133f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 134f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson if (KillIndices[Reg] != ~0u) { 135f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // If Reg is currently live, then mark that it can't be renamed as 136f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // we don't know the extent of its live-range anymore (now that it 137f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // has been scheduled). 138f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 139f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson KillIndices[Reg] = Count; 140f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) { 141f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // Any register which was defined within the previous scheduling region 142f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // may have been rescheduled and its lifetime may overlap with registers 143f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // in ways not reflected in our current liveness state. For each such 144f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // register, adjust the liveness state to be conservatively correct. 1452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 1469c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling 1472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Move the def index to the end of the previous region, to reflect 1482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // that the def could theoretically have been scheduled at the end. 1492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = InsertPosIndex; 1502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 151f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson } 1522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin PrescanInstruction(MI); 1542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin ScanInstruction(MI, Count); 1552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin/// CriticalPathStep - Return the next SUnit after SU on the bottom-up 1582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin/// critical path. 15966db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohmanstatic const SDep *CriticalPathStep(const SUnit *SU) { 16066db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SDep *Next = 0; 1612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned NextDepth = 0; 1622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Find the predecessor edge with the greatest depth. 16366db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end(); 1642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin P != PE; ++P) { 16566db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SUnit *PredSU = P->getSUnit(); 1662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned PredLatency = P->getLatency(); 1672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned PredTotalLatency = PredSU->getDepth() + PredLatency; 1682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // In the case of a latency tie, prefer an anti-dependency edge over 1692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // other types of edges. 1702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (NextDepth < PredTotalLatency || 1712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) { 1722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin NextDepth = PredTotalLatency; 1732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Next = &*P; 1742e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return Next; 1772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { 18046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // It's not safe to change register allocation for source operands of 18146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // that have special allocation requirements. Also assume all registers 18246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // used in a call must not be changed (ABI). 18346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // FIXME: The issue with predicated instruction is more complex. We are being 18459718a4f42551fc0034b860cb8119f728023c303Bob Wilson // conservative here because the kill markers cannot be trusted after 18546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // if-conversion: 18646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] 18746df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // ... 18846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395] 18946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12] 19046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) 19146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // 19246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // The first R6 kill is not really a kill since it's killed by a predicated 19346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // instruction which may not be executed. The second R6 def may or may not 19446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // re-define R6 so it's not safe to change it since the last R6 use cannot be 19546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // changed. 1965a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool Special = MI->isCall() || 1975a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng MI->hasExtraSrcRegAllocReq() || 19846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng TII->isPredicated(MI); 19946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng 2002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Scan the register operands for this instruction and update 2012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Classes and RegRefs. 2022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 2042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 2052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 2062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 2072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const TargetRegisterClass *NewRC = 0; 20801384ef159caa7eebff0e1d703638f2e2c862092Jim Grosbach 2092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (i < MI->getDesc().getNumOperands()) 21015993f83a419950f06d2879d6701530ae6449317Evan Cheng NewRC = TII->getRegClass(MI->getDesc(), i, TRI); 2112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // For now, only allow the register to be changed if its register 2132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // class is consistent across all uses. 2142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!Classes[Reg] && NewRC) 2152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = NewRC; 2162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (!NewRC || Classes[Reg] != NewRC) 2172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 2182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Now check for aliases. 2202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 2212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If an alias of the reg is used during the live range, give up. 2222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Note that this allows us to skip checking if AntiDepReg 2232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // overlaps with any of the aliases, among other things. 2242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AliasReg = *Alias; 2252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Classes[AliasReg]) { 2262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 2272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 2282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If we're still willing to consider this register, note the reference. 2322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1)) 2332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.insert(std::make_pair(Reg, &MO)); 2342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 23546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (MO.isUse() && Special) { 2362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KeepRegs.insert(Reg)) { 2372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Subreg = TRI->getSubRegisters(Reg); 2382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin *Subreg; ++Subreg) 2392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KeepRegs.insert(*Subreg); 2402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 2442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI, 2462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Count) { 2472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Update liveness. 2482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Proceding upwards, registers that are defed but not used in this 2492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // instruction are now dead. 25046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng 25146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (!TII->isPredicated(MI)) { 25246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Predicated defs are modeled as read + write, i.e. similar to two 25346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // address updates. 25446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 25546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng MachineOperand &MO = MI->getOperand(i); 25646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (!MO.isReg()) continue; 25746df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng unsigned Reg = MO.getReg(); 25846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (Reg == 0) continue; 25946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (!MO.isDef()) continue; 26046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Ignore two-addr defs. 26146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (MI->isRegTiedToUseOperand(i)) continue; 26246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng 26346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng DefIndices[Reg] = Count; 26446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng KillIndices[Reg] = ~0u; 26546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng assert(((KillIndices[Reg] == ~0u) != 26646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng (DefIndices[Reg] == ~0u)) && 26746df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng "Kill and Def maps aren't consistent for Reg!"); 26846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng KeepRegs.erase(Reg); 26946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng Classes[Reg] = 0; 27046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng RegRefs.erase(Reg); 27146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Repeat, for all subregs. 27246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng for (const unsigned *Subreg = TRI->getSubRegisters(Reg); 27346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng *Subreg; ++Subreg) { 27446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng unsigned SubregReg = *Subreg; 27546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng DefIndices[SubregReg] = Count; 27646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng KillIndices[SubregReg] = ~0u; 27746df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng KeepRegs.erase(SubregReg); 27846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng Classes[SubregReg] = 0; 27946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng RegRefs.erase(SubregReg); 28046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng } 28146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Conservatively mark super-registers as unusable. 28246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng for (const unsigned *Super = TRI->getSuperRegisters(Reg); 28346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng *Super; ++Super) { 28446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng unsigned SuperReg = *Super; 28546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1); 28646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng } 2872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 2912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 2922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 2932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 2942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isUse()) continue; 2952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const TargetRegisterClass *NewRC = 0; 2972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (i < MI->getDesc().getNumOperands()) 29815993f83a419950f06d2879d6701530ae6449317Evan Cheng NewRC = TII->getRegClass(MI->getDesc(), i, TRI); 2992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // For now, only allow the register to be changed if its register 3012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // class is consistent across all uses. 3022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!Classes[Reg] && NewRC) 3032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = NewRC; 3042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (!NewRC || Classes[Reg] != NewRC) 3052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 3062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.insert(std::make_pair(Reg, &MO)); 3082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // It wasn't previously live but now it is, this is a kill. 3102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[Reg] == ~0u) { 3112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[Reg] = Count; 3122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = ~0u; 3132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[Reg] == ~0u) != 3142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[Reg] == ~0u)) && 3152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for Reg!"); 3162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Repeat, for all aliases. 3182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 3192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AliasReg = *Alias; 3202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[AliasReg] == ~0u) { 3212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AliasReg] = Count; 3222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AliasReg] = ~0u; 3232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 3272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 328bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// Check all machine operands that reference the antidependent register and must 329bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// be replaced by NewReg. Return true if any of their parent instructions may 330bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// clobber the new register. 331bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// 332bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// Note: AntiDepReg may be referenced by a two-address instruction such that 333bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// it's use operand is tied to a def operand. We guard against the case in which 334bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// the two-address instruction also defines NewReg, as may happen with 335bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// pre/postincrement loads. In this case, both the use and def operands are in 336bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// RegRefs because the def is inserted by PrescanInstruction and not erased 337bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// during ScanInstruction. So checking for an instructions with definitions of 338bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// both NewReg and AntiDepReg covers it. 33946388526963aba92344ee8ebd9e86d3556baa088Andrew Trickbool 340bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew TrickCriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin, 341bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick RegRefIter RegRefEnd, 342bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick unsigned NewReg) 34346388526963aba92344ee8ebd9e86d3556baa088Andrew Trick{ 34446388526963aba92344ee8ebd9e86d3556baa088Andrew Trick for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) { 345bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick MachineOperand *RefOper = I->second; 346bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 347bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // Don't allow the instruction defining AntiDepReg to earlyclobber its 348bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // operands, in case they may be assigned to NewReg. In this case antidep 349bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // breaking must fail, but it's too rare to bother optimizing. 350bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (RefOper->isDef() && RefOper->isEarlyClobber()) 35146388526963aba92344ee8ebd9e86d3556baa088Andrew Trick return true; 352bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 353bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // Handle cases in which this instructions defines NewReg. 354bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick MachineInstr *MI = RefOper->getParent(); 355bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 356bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick const MachineOperand &CheckOper = MI->getOperand(i); 357bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 358bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (!CheckOper.isReg() || !CheckOper.isDef() || 359bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick CheckOper.getReg() != NewReg) 360bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick continue; 361bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 362bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // Don't allow the instruction to define NewReg and AntiDepReg. 363bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // When AntiDepReg is renamed it will be an illegal op. 364bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (RefOper->isDef()) 365bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick return true; 366bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 367bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // Don't allow an instruction using AntiDepReg to be earlyclobbered by 368bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // NewReg 369bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (CheckOper.isEarlyClobber()) 370bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick return true; 371bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 372bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // Don't allow inline asm to define NewReg at all. Who know what it's 373bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // doing with it. 374bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (MI->isInlineAsm()) 375bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick return true; 376bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick } 37746388526963aba92344ee8ebd9e86d3556baa088Andrew Trick } 37846388526963aba92344ee8ebd9e86d3556baa088Andrew Trick return false; 37946388526963aba92344ee8ebd9e86d3556baa088Andrew Trick} 38046388526963aba92344ee8ebd9e86d3556baa088Andrew Trick 3812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinunsigned 38246388526963aba92344ee8ebd9e86d3556baa088Andrew TrickCriticalAntiDepBreaker::findSuitableFreeRegister(RegRefIter RegRefBegin, 38346388526963aba92344ee8ebd9e86d3556baa088Andrew Trick RegRefIter RegRefEnd, 38480c2b0d9efc951b23f90a3cf12b9853177994961Jim Grosbach unsigned AntiDepReg, 3852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned LastNewReg, 3862973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach const TargetRegisterClass *RC) 3872973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach{ 388fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund Olesen ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC); 389fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund Olesen for (unsigned i = 0; i != Order.size(); ++i) { 390fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund Olesen unsigned NewReg = Order[i]; 3912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't replace a register with itself. 3922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (NewReg == AntiDepReg) continue; 3932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't replace a register with one that was recently used to repair 3942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // an anti-dependence with this AntiDepReg, because that would 3952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // re-introduce that anti-dependence. 3962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (NewReg == LastNewReg) continue; 39746388526963aba92344ee8ebd9e86d3556baa088Andrew Trick // If any instructions that define AntiDepReg also define the NewReg, it's 39846388526963aba92344ee8ebd9e86d3556baa088Andrew Trick // not suitable. For example, Instruction with multiple definitions can 39946388526963aba92344ee8ebd9e86d3556baa088Andrew Trick // result in this condition. 400bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue; 4012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If NewReg is dead and NewReg's most recent def is not before 4022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg. 4032973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) 4042973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach && "Kill and Def maps aren't consistent for AntiDepReg!"); 4052973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) 4062973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach && "Kill and Def maps aren't consistent for NewReg!"); 4072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[NewReg] != ~0u || 4082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) || 4092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AntiDepReg] > DefIndices[NewReg]) 4102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin continue; 4112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return NewReg; 4122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // No registers are free and available! 4152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return 0; 4162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 4172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinunsigned CriticalAntiDepBreaker:: 41966db3a0f10e96ae190c8a46a1a8d5242928d068cDan GohmanBreakAntiDependencies(const std::vector<SUnit>& SUnits, 42066db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman MachineBasicBlock::iterator Begin, 42166db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman MachineBasicBlock::iterator End, 422e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel unsigned InsertPosIndex, 423e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel DbgValueVector &DbgValues) { 4242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // The code below assumes that there is at least one instruction, 4252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // so just duck out immediately if the block is empty. 4262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (SUnits.empty()) return 0; 4272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 428533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // Keep a map of the MachineInstr*'s back to the SUnit representing them. 429533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // This is used for updating debug information. 430b4566a999970b514d7c6973d99e293a6625d3f70Andrew Trick // 431b4566a999970b514d7c6973d99e293a6625d3f70Andrew Trick // FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap 432533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach DenseMap<MachineInstr*,const SUnit*> MISUnitMap; 433533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach 4342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Find the node at the bottom of the critical path. 43566db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SUnit *Max = 0; 4362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 43766db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SUnit *SU = &SUnits[i]; 438533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach MISUnitMap[SU->getInstr()] = SU; 4392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) 4402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Max = SU; 4412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#ifndef NDEBUG 4442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin { 44589d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << "Critical path has total latency " 4462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << (Max->getDepth() + Max->Latency) << "\n"); 44789d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << "Available regs:"); 4482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { 4492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[Reg] == ~0u) 45089d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << " " << TRI->getName(Reg)); 4512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 45289d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << '\n'); 4532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#endif 4552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Track progress along the critical path through the SUnit graph as we walk 4572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // the instructions. 45866db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SUnit *CriticalPathSU = Max; 4592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); 4602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Consider this pattern: 4622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // There are three anti-dependencies here, and without special care, 4712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // we'd break all of them using the same register: 4722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4742e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 4752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 4762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 4772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 4782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 4792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 4802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // because at each anti-dependence, B is the first register that 4812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // isn't A which is free. This re-introduces anti-dependencies 4822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // at all but one of the original anti-dependencies that we were 4832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // trying to break. To avoid this, keep track of the most recent 4842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // register that each register was replaced with, avoid 4852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // using it to repair an anti-dependence on the same register. 4862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // This lets us produce this: 4872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 4902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 4912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // C = ... 4922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = C 4932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 4942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 4952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // This still has an anti-dependence on B, but at least it isn't on the 4962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // original critical path. 4972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 4982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // TODO: If we tracked more than one register here, we could potentially 4992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // fix that remaining critical edge too. This is a little more involved, 5002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // because unlike the most recent register, less recent registers should 5012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // still be considered, though only if no other registers are available. 5029c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0); 5032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Attempt to break anti-dependence edges on the critical path. Walk the 5052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // instructions from the bottom up, tracking information about liveness 5062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // as we go to help determine which registers are available. 5072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Broken = 0; 5082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Count = InsertPosIndex - 1; 5092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (MachineBasicBlock::iterator I = End, E = Begin; 5102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin I != E; --Count) { 5112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineInstr *MI = --I; 512b0812f114b83a32c4b90a4b553c7177c557558b5Dale Johannesen if (MI->isDebugValue()) 513b0812f114b83a32c4b90a4b553c7177c557558b5Dale Johannesen continue; 5142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Check if this instruction has a dependence on the critical path that 5162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // is an anti-dependence that we may be able to break. If it is, set 5172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // AntiDepReg to the non-zero register associated with the anti-dependence. 5182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 5192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // We limit our attention to the critical path as a heuristic to avoid 5202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // breaking anti-dependence edges that aren't going to significantly 5212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // impact the overall schedule. There are a limited number of registers 5222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // and we want to save them for the important edges. 52301384ef159caa7eebff0e1d703638f2e2c862092Jim Grosbach // 5242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // TODO: Instructions with multiple defs could have multiple 5252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // anti-dependencies. The current code here only knows how to break one 5262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // edge per instruction. Note that we'd have to be able to break all of 5272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // the anti-dependencies in an instruction in order to be effective. 5282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AntiDepReg = 0; 5292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (MI == CriticalPathMI) { 53066db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) { 53166db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SUnit *NextSU = Edge->getSUnit(); 5322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Only consider anti-dependence edges. 5342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Edge->getKind() == SDep::Anti) { 5352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = Edge->getReg(); 5362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(AntiDepReg != 0 && "Anti-dependence on reg0?"); 537fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund Olesen if (!RegClassInfo.isAllocatable(AntiDepReg)) 5382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't break anti-dependencies on non-allocatable registers. 5392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 5402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (KeepRegs.count(AntiDepReg)) 5412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't break anti-dependencies if an use down below requires 5422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // this exact register. 5432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 5442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else { 5452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If the SUnit has other dependencies on the SUnit that it 5462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // anti-depends on, don't bother breaking the anti-dependency 5472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // since those edges would prevent such units from being 5482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // scheduled past each other regardless. 5492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 5502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Also, if there are dependencies on other SUnits with the 5512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // same register as the anti-dependency, don't attempt to 5522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // break it. 55366db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(), 5542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin PE = CriticalPathSU->Preds.end(); P != PE; ++P) 5552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (P->getSUnit() == NextSU ? 5562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : 5572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) { 5582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 5592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin break; 5602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathSU = NextSU; 5642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathMI = CriticalPathSU->getInstr(); 5652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } else { 5662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // We've reached the end of the critical path. 5672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathSU = 0; 5682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathMI = 0; 5692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin PrescanInstruction(MI); 5732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 57446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // If MI's defs have a special allocation requirement, don't allow 57546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // any def registers to be changed. Also assume all registers 57646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // defined in a call must not be changed (ABI). 5775a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (MI->isCall() || MI->hasExtraDefRegAllocReq() || 57846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng TII->isPredicated(MI)) 5792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If this instruction's defs have special allocation requirement, don't 5802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // break this anti-dependency. 5812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 5822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (AntiDepReg) { 5832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If this instruction has a use of AntiDepReg, breaking it 5842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // is invalid. 5852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 5862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 5872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 5882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 5892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 59046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { 5912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 5922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin break; 5932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Determine AntiDepReg's register class, if it is live and is 5982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // consistently used within a single class. 5992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0; 6002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert((AntiDepReg == 0 || RC != NULL) && 6012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Register should be live if it's causing an anti-dependence!"); 6022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 6032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 6042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Look for a suitable register to use to break the anti-depenence. 6062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 6072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // TODO: Instead of picking the first free register, consider which might 6082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // be the best. 6092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (AntiDepReg != 0) { 61046388526963aba92344ee8ebd9e86d3556baa088Andrew Trick std::pair<std::multimap<unsigned, MachineOperand *>::iterator, 61146388526963aba92344ee8ebd9e86d3556baa088Andrew Trick std::multimap<unsigned, MachineOperand *>::iterator> 61246388526963aba92344ee8ebd9e86d3556baa088Andrew Trick Range = RegRefs.equal_range(AntiDepReg); 61346388526963aba92344ee8ebd9e86d3556baa088Andrew Trick if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second, 61446388526963aba92344ee8ebd9e86d3556baa088Andrew Trick AntiDepReg, 6152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin LastNewReg[AntiDepReg], 6162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RC)) { 61789d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << "Breaking anti-dependence edge on " 6182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << TRI->getName(AntiDepReg) 6192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << " with " << RegRefs.count(AntiDepReg) << " references" 6202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << " using " << TRI->getName(NewReg) << "!\n"); 6212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Update the references to the old register to refer to the new 6232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // register. 6242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (std::multimap<unsigned, MachineOperand *>::iterator 625533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach Q = Range.first, QE = Range.second; Q != QE; ++Q) { 6262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Q->second->setReg(NewReg); 627533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // If the SU for the instruction being updated has debug information 628533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // related to the anti-dependency register, make sure to update that 629533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // as well. 630533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach const SUnit *SU = MISUnitMap[Q->second->getParent()]; 631086723d244952aee690a8aa39485a0fa0d3a7700Jim Grosbach if (!SU) continue; 632e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel for (DbgValueVector::iterator DVI = DbgValues.begin(), 633e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel DVE = DbgValues.end(); DVI != DVE; ++DVI) 634e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel if (DVI->second == Q->second->getParent()) 635e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel UpdateDbgValue(DVI->first, AntiDepReg, NewReg); 636533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach } 6372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // We just went back in time and modified history; the 639f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // liveness information for the anti-dependence reg is now 6402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // inconsistent. Set the state as if it were dead. 6412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[NewReg] = Classes[AntiDepReg]; 6422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[NewReg] = DefIndices[AntiDepReg]; 6432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[NewReg] = KillIndices[AntiDepReg]; 6442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[NewReg] == ~0u) != 6452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[NewReg] == ~0u)) && 6462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for NewReg!"); 6472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AntiDepReg] = 0; 6492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AntiDepReg] = KillIndices[AntiDepReg]; 6502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AntiDepReg] = ~0u; 6512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[AntiDepReg] == ~0u) != 6522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[AntiDepReg] == ~0u)) && 6532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for AntiDepReg!"); 6542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.erase(AntiDepReg); 6562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin LastNewReg[AntiDepReg] = NewReg; 6572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin ++Broken; 6582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin ScanInstruction(MI, Count); 6622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6642e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return Broken; 6652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 666