CriticalAntiDepBreaker.h revision e10deca33e74a7c70ab585f78eee3fb52937f668 
1//=- llvm/CodeGen/CriticalAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the CriticalAntiDepBreaker class, which
11// implements register anti-dependence breaking along a blocks
12// critical path during post-RA scheduler.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_CODEGEN_CRITICALANTIDEPBREAKER_H
17#define LLVM_CODEGEN_CRITICALANTIDEPBREAKER_H
18
19#include "llvm/CodeGen/AntiDepBreaker.h"
20#include "llvm/CodeGen/MachineBasicBlock.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/ScheduleDAG.h"
25#include "llvm/Target/TargetRegisterInfo.h"
26#include "llvm/ADT/BitVector.h"
27#include "llvm/ADT/SmallSet.h"
28
29namespace llvm {
30  class CriticalAntiDepBreaker : public AntiDepBreaker {
31    MachineFunction& MF;
32    MachineRegisterInfo &MRI;
33    const TargetRegisterInfo *TRI;
34
35    /// AllocatableSet - The set of allocatable registers.
36    /// We'll be ignoring anti-dependencies on non-allocatable registers,
37    /// because they may not be safe to break.
38    const BitVector AllocatableSet;
39
40    /// Classes - For live regs that are only used in one register class in a
41    /// live range, the register class. If the register is not live, the
42    /// corresponding value is null. If the register is live but used in
43    /// multiple register classes, the corresponding value is -1 casted to a
44    /// pointer.
45    const TargetRegisterClass *
46      Classes[TargetRegisterInfo::FirstVirtualRegister];
47
48    /// RegRegs - Map registers to all their references within a live range.
49    std::multimap<unsigned, MachineOperand *> RegRefs;
50
51    /// KillIndices - The index of the most recent kill (proceding bottom-up),
52    /// or ~0u if the register is not live.
53    unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
54
55    /// DefIndices - The index of the most recent complete def (proceding bottom
56    /// up), or ~0u if the register is live.
57    unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
58
59    /// KeepRegs - A set of registers which are live and cannot be changed to
60    /// break anti-dependencies.
61    SmallSet<unsigned, 4> KeepRegs;
62
63  public:
64    CriticalAntiDepBreaker(MachineFunction& MFi);
65    ~CriticalAntiDepBreaker();
66
67    /// GetMaxTrials - Critical path anti-dependence breaking requires
68    /// only a single pass
69    unsigned GetMaxTrials() { return 1; }
70
71    /// Start - Initialize anti-dep breaking for a new basic block.
72    void StartBlock(MachineBasicBlock *BB);
73
74    /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
75    /// of the ScheduleDAG and break them by renaming registers.
76    ///
77    unsigned BreakAntiDependencies(std::vector<SUnit>& SUnits,
78                                   MachineBasicBlock::iterator& Begin,
79                                   MachineBasicBlock::iterator& End,
80                                   unsigned InsertPosIndex);
81
82    /// Observe - Update liveness information to account for the current
83    /// instruction, which will not be scheduled.
84    ///
85    void Observe(MachineInstr *MI, unsigned Count, unsigned InsertPosIndex);
86
87    /// Finish - Finish anti-dep breaking for a basic block.
88    void FinishBlock();
89
90  private:
91    void PrescanInstruction(MachineInstr *MI);
92    void ScanInstruction(MachineInstr *MI, unsigned Count);
93    unsigned findSuitableFreeRegister(unsigned AntiDepReg,
94                                      unsigned LastNewReg,
95                                      const TargetRegisterClass *);
96  };
97}
98
99#endif
100