InlineSpiller.cpp revision f44e6aff1024b3718394172fd85e74415e31c329 
1//===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// The inline spiller modifies the machine function directly instead of
11// inserting spills and restores in VirtRegMap.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "spiller"
16#include "Spiller.h"
17#include "SplitKit.h"
18#include "VirtRegMap.h"
19#include "llvm/CodeGen/LiveIntervalAnalysis.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineLoopInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/Target/TargetMachine.h"
25#include "llvm/Target/TargetInstrInfo.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/raw_ostream.h"
28
29using namespace llvm;
30
31namespace {
32class InlineSpiller : public Spiller {
33  MachineFunctionPass &pass_;
34  MachineFunction &mf_;
35  LiveIntervals &lis_;
36  MachineLoopInfo &loops_;
37  VirtRegMap &vrm_;
38  MachineFrameInfo &mfi_;
39  MachineRegisterInfo &mri_;
40  const TargetInstrInfo &tii_;
41  const TargetRegisterInfo &tri_;
42  const BitVector reserved_;
43
44  SplitAnalysis splitAnalysis_;
45
46  // Variables that are valid during spill(), but used by multiple methods.
47  LiveInterval *li_;
48  SmallVectorImpl<LiveInterval*> *newIntervals_;
49  const TargetRegisterClass *rc_;
50  int stackSlot_;
51  const SmallVectorImpl<LiveInterval*> *spillIs_;
52
53  // Values of the current interval that can potentially remat.
54  SmallPtrSet<VNInfo*, 8> reMattable_;
55
56  // Values in reMattable_ that failed to remat at some point.
57  SmallPtrSet<VNInfo*, 8> usedValues_;
58
59  ~InlineSpiller() {}
60
61public:
62  InlineSpiller(MachineFunctionPass &pass,
63                MachineFunction &mf,
64                VirtRegMap &vrm)
65    : pass_(pass),
66      mf_(mf),
67      lis_(pass.getAnalysis<LiveIntervals>()),
68      loops_(pass.getAnalysis<MachineLoopInfo>()),
69      vrm_(vrm),
70      mfi_(*mf.getFrameInfo()),
71      mri_(mf.getRegInfo()),
72      tii_(*mf.getTarget().getInstrInfo()),
73      tri_(*mf.getTarget().getRegisterInfo()),
74      reserved_(tri_.getReservedRegs(mf_)),
75      splitAnalysis_(mf, lis_, loops_) {}
76
77  void spill(LiveInterval *li,
78             SmallVectorImpl<LiveInterval*> &newIntervals,
79             SmallVectorImpl<LiveInterval*> &spillIs);
80
81private:
82  bool split();
83
84  bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
85                          SlotIndex UseIdx);
86  bool reMaterializeFor(MachineBasicBlock::iterator MI);
87  void reMaterializeAll();
88
89  bool coalesceStackAccess(MachineInstr *MI);
90  bool foldMemoryOperand(MachineBasicBlock::iterator MI,
91                         const SmallVectorImpl<unsigned> &Ops);
92  void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
93  void insertSpill(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
94};
95}
96
97namespace llvm {
98Spiller *createInlineSpiller(MachineFunctionPass &pass,
99                             MachineFunction &mf,
100                             VirtRegMap &vrm) {
101  return new InlineSpiller(pass, mf, vrm);
102}
103}
104
105/// split - try splitting the current interval into pieces that may allocate
106/// separately. Return true if successful.
107bool InlineSpiller::split() {
108  splitAnalysis_.analyze(li_);
109
110  if (const MachineLoop *loop = splitAnalysis_.getBestSplitLoop()) {
111    // We can split, but li_ may be left intact with fewer uses.
112    if (SplitEditor(splitAnalysis_, lis_, vrm_, *newIntervals_)
113          .splitAroundLoop(loop))
114      return true;
115  }
116
117  // Try splitting into single block intervals.
118  SplitAnalysis::BlockPtrSet blocks;
119  if (splitAnalysis_.getMultiUseBlocks(blocks)) {
120    if (SplitEditor(splitAnalysis_, lis_, vrm_, *newIntervals_)
121          .splitSingleBlocks(blocks))
122      return true;
123  }
124
125  // Try splitting inside a basic block.
126  if (const MachineBasicBlock *MBB = splitAnalysis_.getBlockForInsideSplit()) {
127    if (SplitEditor(splitAnalysis_, lis_, vrm_, *newIntervals_)
128          .splitInsideBlock(MBB))
129      return true;
130  }
131
132  // We may have been able to split out some uses, but the original interval is
133  // intact, and it should still be spilled.
134  return false;
135}
136
137/// allUsesAvailableAt - Return true if all registers used by OrigMI at
138/// OrigIdx are also available with the same value at UseIdx.
139bool InlineSpiller::allUsesAvailableAt(const MachineInstr *OrigMI,
140                                       SlotIndex OrigIdx,
141                                       SlotIndex UseIdx) {
142  OrigIdx = OrigIdx.getUseIndex();
143  UseIdx = UseIdx.getUseIndex();
144  for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
145    const MachineOperand &MO = OrigMI->getOperand(i);
146    if (!MO.isReg() || !MO.getReg() || MO.getReg() == li_->reg)
147      continue;
148    // Reserved registers are OK.
149    if (MO.isUndef() || !lis_.hasInterval(MO.getReg()))
150      continue;
151    // We don't want to move any defs.
152    if (MO.isDef())
153      return false;
154    // We cannot depend on virtual registers in spillIs_. They will be spilled.
155    for (unsigned si = 0, se = spillIs_->size(); si != se; ++si)
156      if ((*spillIs_)[si]->reg == MO.getReg())
157        return false;
158
159    LiveInterval &LI = lis_.getInterval(MO.getReg());
160    const VNInfo *OVNI = LI.getVNInfoAt(OrigIdx);
161    if (!OVNI)
162      continue;
163    if (OVNI != LI.getVNInfoAt(UseIdx))
164      return false;
165  }
166  return true;
167}
168
169/// reMaterializeFor - Attempt to rematerialize li_->reg before MI instead of
170/// reloading it.
171bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
172  SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
173  VNInfo *OrigVNI = li_->getVNInfoAt(UseIdx);
174  if (!OrigVNI) {
175    DEBUG(dbgs() << "\tadding <undef> flags: ");
176    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
177      MachineOperand &MO = MI->getOperand(i);
178      if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg)
179        MO.setIsUndef();
180    }
181    DEBUG(dbgs() << UseIdx << '\t' << *MI);
182    return true;
183  }
184  if (!reMattable_.count(OrigVNI)) {
185    DEBUG(dbgs() << "\tusing non-remat valno " << OrigVNI->id << ": "
186                 << UseIdx << '\t' << *MI);
187    return false;
188  }
189  MachineInstr *OrigMI = lis_.getInstructionFromIndex(OrigVNI->def);
190  if (!allUsesAvailableAt(OrigMI, OrigVNI->def, UseIdx)) {
191    usedValues_.insert(OrigVNI);
192    DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
193    return false;
194  }
195
196  // If the instruction also writes li_->reg, it had better not require the same
197  // register for uses and defs.
198  bool Reads, Writes;
199  SmallVector<unsigned, 8> Ops;
200  tie(Reads, Writes) = MI->readsWritesVirtualRegister(li_->reg, &Ops);
201  if (Writes) {
202    for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
203      MachineOperand &MO = MI->getOperand(Ops[i]);
204      if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
205        usedValues_.insert(OrigVNI);
206        DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
207        return false;
208      }
209    }
210  }
211
212  // Alocate a new register for the remat.
213  unsigned NewVReg = mri_.createVirtualRegister(rc_);
214  vrm_.grow();
215  LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
216  NewLI.markNotSpillable();
217  newIntervals_->push_back(&NewLI);
218
219  // Finally we can rematerialize OrigMI before MI.
220  MachineBasicBlock &MBB = *MI->getParent();
221  tii_.reMaterialize(MBB, MI, NewLI.reg, 0, OrigMI, tri_);
222  MachineBasicBlock::iterator RematMI = MI;
223  SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(--RematMI).getDefIndex();
224  DEBUG(dbgs() << "\tremat:  " << DefIdx << '\t' << *RematMI);
225
226  // Replace operands
227  for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
228    MachineOperand &MO = MI->getOperand(Ops[i]);
229    if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg) {
230      MO.setReg(NewVReg);
231      MO.setIsKill();
232    }
233  }
234  DEBUG(dbgs() << "\t        " << UseIdx << '\t' << *MI);
235
236  VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, true,
237                                       lis_.getVNInfoAllocator());
238  NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
239  DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
240  return true;
241}
242
243/// reMaterializeAll - Try to rematerialize as many uses of li_ as possible,
244/// and trim the live ranges after.
245void InlineSpiller::reMaterializeAll() {
246  // Do a quick scan of the interval values to find if any are remattable.
247  reMattable_.clear();
248  usedValues_.clear();
249  for (LiveInterval::const_vni_iterator I = li_->vni_begin(),
250       E = li_->vni_end(); I != E; ++I) {
251    VNInfo *VNI = *I;
252    if (VNI->isUnused() || !VNI->isDefAccurate())
253      continue;
254    MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
255    if (!DefMI || !tii_.isTriviallyReMaterializable(DefMI))
256      continue;
257    reMattable_.insert(VNI);
258  }
259
260  // Often, no defs are remattable.
261  if (reMattable_.empty())
262    return;
263
264  // Try to remat before all uses of li_->reg.
265  bool anyRemat = false;
266  for (MachineRegisterInfo::use_nodbg_iterator
267       RI = mri_.use_nodbg_begin(li_->reg);
268       MachineInstr *MI = RI.skipInstruction();)
269     anyRemat |= reMaterializeFor(MI);
270
271  if (!anyRemat)
272    return;
273
274  // Remove any values that were completely rematted.
275  bool anyRemoved = false;
276  for (SmallPtrSet<VNInfo*, 8>::iterator I = reMattable_.begin(),
277       E = reMattable_.end(); I != E; ++I) {
278    VNInfo *VNI = *I;
279    if (VNI->hasPHIKill() || usedValues_.count(VNI))
280      continue;
281    MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
282    DEBUG(dbgs() << "\tremoving dead def: " << VNI->def << '\t' << *DefMI);
283    lis_.RemoveMachineInstrFromMaps(DefMI);
284    vrm_.RemoveMachineInstrFromMaps(DefMI);
285    DefMI->eraseFromParent();
286    VNI->setIsDefAccurate(false);
287    anyRemoved = true;
288  }
289
290  if (!anyRemoved)
291    return;
292
293  // Removing values may cause debug uses where li_ is not live.
294  for (MachineRegisterInfo::use_iterator RI = mri_.use_begin(li_->reg);
295       MachineInstr *MI = RI.skipInstruction();) {
296    if (!MI->isDebugValue())
297      continue;
298    // Try to preserve the debug value if li_ is live immediately after it.
299    MachineBasicBlock::iterator NextMI = MI;
300    ++NextMI;
301    if (NextMI != MI->getParent()->end() && !lis_.isNotInMIMap(NextMI)) {
302      VNInfo *VNI = li_->getVNInfoAt(lis_.getInstructionIndex(NextMI));
303      if (VNI && (VNI->hasPHIKill() || usedValues_.count(VNI)))
304        continue;
305    }
306    DEBUG(dbgs() << "Removing debug info due to remat:" << "\t" << *MI);
307    MI->eraseFromParent();
308  }
309}
310
311/// If MI is a load or store of stackSlot_, it can be removed.
312bool InlineSpiller::coalesceStackAccess(MachineInstr *MI) {
313  int FI = 0;
314  unsigned reg;
315  if (!(reg = tii_.isLoadFromStackSlot(MI, FI)) &&
316      !(reg = tii_.isStoreToStackSlot(MI, FI)))
317    return false;
318
319  // We have a stack access. Is it the right register and slot?
320  if (reg != li_->reg || FI != stackSlot_)
321    return false;
322
323  DEBUG(dbgs() << "Coalescing stack access: " << *MI);
324  lis_.RemoveMachineInstrFromMaps(MI);
325  MI->eraseFromParent();
326  return true;
327}
328
329/// foldMemoryOperand - Try folding stack slot references in Ops into MI.
330/// Return true on success, and MI will be erased.
331bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
332                                      const SmallVectorImpl<unsigned> &Ops) {
333  // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
334  // operands.
335  SmallVector<unsigned, 8> FoldOps;
336  for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
337    unsigned Idx = Ops[i];
338    MachineOperand &MO = MI->getOperand(Idx);
339    if (MO.isImplicit())
340      continue;
341    // FIXME: Teach targets to deal with subregs.
342    if (MO.getSubReg())
343      return false;
344    // Tied use operands should not be passed to foldMemoryOperand.
345    if (!MI->isRegTiedToDefOperand(Idx))
346      FoldOps.push_back(Idx);
347  }
348
349  MachineInstr *FoldMI = tii_.foldMemoryOperand(MI, FoldOps, stackSlot_);
350  if (!FoldMI)
351    return false;
352  lis_.ReplaceMachineInstrInMaps(MI, FoldMI);
353  vrm_.addSpillSlotUse(stackSlot_, FoldMI);
354  MI->eraseFromParent();
355  DEBUG(dbgs() << "\tfolded: " << *FoldMI);
356  return true;
357}
358
359/// insertReload - Insert a reload of NewLI.reg before MI.
360void InlineSpiller::insertReload(LiveInterval &NewLI,
361                                 MachineBasicBlock::iterator MI) {
362  MachineBasicBlock &MBB = *MI->getParent();
363  SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
364  tii_.loadRegFromStackSlot(MBB, MI, NewLI.reg, stackSlot_, rc_, &tri_);
365  --MI; // Point to load instruction.
366  SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
367  vrm_.addSpillSlotUse(stackSlot_, MI);
368  DEBUG(dbgs() << "\treload:  " << LoadIdx << '\t' << *MI);
369  VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
370                                       lis_.getVNInfoAllocator());
371  NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
372}
373
374/// insertSpill - Insert a spill of NewLI.reg after MI.
375void InlineSpiller::insertSpill(LiveInterval &NewLI,
376                                MachineBasicBlock::iterator MI) {
377  MachineBasicBlock &MBB = *MI->getParent();
378  SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
379  tii_.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, stackSlot_, rc_, &tri_);
380  --MI; // Point to store instruction.
381  SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
382  vrm_.addSpillSlotUse(stackSlot_, MI);
383  DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
384  VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
385                                        lis_.getVNInfoAllocator());
386  NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
387}
388
389void InlineSpiller::spill(LiveInterval *li,
390                          SmallVectorImpl<LiveInterval*> &newIntervals,
391                          SmallVectorImpl<LiveInterval*> &spillIs) {
392  DEBUG(dbgs() << "Inline spilling " << *li << "\n");
393  assert(li->isSpillable() && "Attempting to spill already spilled value.");
394  assert(!li->isStackSlot() && "Trying to spill a stack slot.");
395
396  li_ = li;
397  newIntervals_ = &newIntervals;
398  rc_ = mri_.getRegClass(li->reg);
399  spillIs_ = &spillIs;
400
401  if (split())
402    return;
403
404  reMaterializeAll();
405
406  // Remat may handle everything.
407  if (li_->empty())
408    return;
409
410  stackSlot_ = vrm_.getStackSlot(li->reg);
411  if (stackSlot_ == VirtRegMap::NO_STACK_SLOT)
412    stackSlot_ = vrm_.assignVirt2StackSlot(li->reg);
413
414  // Iterate over instructions using register.
415  for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
416       MachineInstr *MI = RI.skipInstruction();) {
417
418    // Debug values are not allowed to affect codegen.
419    if (MI->isDebugValue()) {
420      // Modify DBG_VALUE now that the value is in a spill slot.
421      uint64_t Offset = MI->getOperand(1).getImm();
422      const MDNode *MDPtr = MI->getOperand(2).getMetadata();
423      DebugLoc DL = MI->getDebugLoc();
424      if (MachineInstr *NewDV = tii_.emitFrameIndexDebugValue(mf_, stackSlot_,
425                                                           Offset, MDPtr, DL)) {
426        DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
427        MachineBasicBlock *MBB = MI->getParent();
428        MBB->insert(MBB->erase(MI), NewDV);
429      } else {
430        DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
431        MI->eraseFromParent();
432      }
433      continue;
434    }
435
436    // Stack slot accesses may coalesce away.
437    if (coalesceStackAccess(MI))
438      continue;
439
440    // Analyze instruction.
441    bool Reads, Writes;
442    SmallVector<unsigned, 8> Ops;
443    tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
444
445    // Attempt to fold memory ops.
446    if (foldMemoryOperand(MI, Ops))
447      continue;
448
449    // Allocate interval around instruction.
450    // FIXME: Infer regclass from instruction alone.
451    unsigned NewVReg = mri_.createVirtualRegister(rc_);
452    vrm_.grow();
453    LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
454    NewLI.markNotSpillable();
455
456    if (Reads)
457      insertReload(NewLI, MI);
458
459    // Rewrite instruction operands.
460    bool hasLiveDef = false;
461    for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
462      MachineOperand &MO = MI->getOperand(Ops[i]);
463      MO.setReg(NewVReg);
464      if (MO.isUse()) {
465        if (!MI->isRegTiedToDefOperand(Ops[i]))
466          MO.setIsKill();
467      } else {
468        if (!MO.isDead())
469          hasLiveDef = true;
470      }
471    }
472
473    // FIXME: Use a second vreg if instruction has no tied ops.
474    if (Writes && hasLiveDef)
475      insertSpill(NewLI, MI);
476
477    DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
478    newIntervals.push_back(&NewLI);
479  }
480}
481